HD74HC164
8-bit Parallel-out Shift Register
Description
This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flip-
flop. Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits
entry of new data and resets the first flip-vlop to the low level at the next clock pulse. A high level on the
input enables the other input which will then determine the state of the first flip-flop. Data at the serial
inputs may be changed while the clock is high or low, but only information meeting the setup and hold time
requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive
going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at
the clear input.
Features
High Speed Operation: t
pd
(Clock to Q) = 14.5 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 A max
Low Quiescent Supply Current: I
CC
(static) = 4 A max
Function Table
Inputs
Outputs
Clear
Clock
A
B
Q
A
Q
B
Q
H
L
X
X
X
L
L
L
H
X
X
Q
Ao
Q
Bo
Q
Ho
H
L
X
L
Q
An
Q
Gn
H
X
L
L
Q
An
Q
Gn
H
H
H
H
Q
An
Q
Gn
Q
Ao
to Q
Ho
= Outputs remain unchanged.
Q
An
to Q
Gn
= Data shifted from the previous stage on a positive edge at the clock input.
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