Document Outline

Cover
Cautions
Preface
Contents
Section 1 Overview
- 1.1 Overview
- 1.2 Internal Block Diagram
- 1.3 Pin Arrangement and Functions
  - 1.3.1 Pin Arrangement
  - 1.3.2 Pin Functions
Section 2 CPU
- 2.1 Overview
  - 2.1.1 Features
  - 2.1.2 Address Space
  - 2.1.3 Register Configuration
- 2.2 Register Descriptions
  - 2.2.1 General Registers
  - 2.2.2 Control Registers
  - 2.2.3 Initial Register Values
- 2.3 Data Formats
  - 2.3.1 Data Formats in General Registers
  - 2.3.2 Memory Data Formats
- 2.4 Addressing Modes
  - 2.4.1 Addressing Modes
  - 2.4.2 Effective Address Calculation
- 2.5 Instruction Set
  - 2.5.1 Data Transfer Instructions
  - 2.5.2 Arithmetic Operations
  - 2.5.3 Logic Operations
  - 2.5.4 Shift Operations
  - 2.5.5 Bit Manipulations
  - 2.5.6 Branching Instructions
  - 2.5.7 System Control Instructions
  - 2.5.8 Block Data Transfer Instruction
- 2.6 Basic Operational Timing
  - 2.6.1 Access to On-Chip Memory (RAM, ROM)
  - 2.6.2 Access to On-Chip Peripheral Modules
- 2.7 CPU States
  - 2.7.1 Overview
  - 2.7.2 Program Execution State
  - 2.7.3 Program Halt State
  - 2.7.4 Exception-Handling State
- 2.8 Memory Map
- 2.9 Application Notes
  - 2.9.1 Notes on Data Access
  - 2.9.2 Notes on Bit Manipulation
  - 2.9.3 Notes on Use of the EEPMOV Instruction
Section 3 Exception Handling
- 3.1 Overview
- 3.2 Reset
  - 3.2.1 Overview
  - 3.2.2 Reset Sequence
  - 3.2.3 Interrupt Immediately after Reset
- 3.3 Interrupts
  - 3.3.1 Overview
  - 3.3.2 Interrupt Control Registers
  - 3.3.3 External Interrupts
  - 3.3.4 Internal Interrupts
  - 3.3.5 Interrupt Operations
  - 3.3.6 Interrupt Response Time
- 3.4 Application Notes
  - 3.4.1 Notes on Stack Area Use
  - 3.4.2 Notes on Rewriting Port Mode Registers
  - 3.4.3 Notes on Interrupt Request Flag Clearing Methods
Section 4 Clock Pulse Generators
- 4.1 Overview
  - 4.1.1 Block Diagram
  - 4.1.2 System Clock and Subclock
- 4.2 System Clock Generator
- 4.3 Subclock Generator
- 4.4 Prescalers
- 4.5 Note on Oscillators
  - 4.5.1 Definition of Oscillation Settling Standby Time
  - 4.5.2 Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
Section 5 Power-Down Modes
- 5.1 Overview
  - 5.1.1 System Control Registers
- 5.2 Sleep Mode
  - 5.2.1 Transition to Sleep Mode
  - 5.2.2 Clearing Sleep Mode
  - 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode
- 5.3 Standby Mode
  - 5.3.1 Transition to Standby Mode
  - 5.3.2 Clearing Standby Mode
  - 5.3.3 Oscillator Settling Time after Standby Mode is Cleared
  - 5.3.4 Standby Mode Transition and Pin States
  - 5.3.5 Notes on External Input Signal Changes before/after Standby Mode
- 5.4 Watch Mode
  - 5.4.1 Transition to Watch Mode
  - 5.4.2 Clearing Watch Mode
  - 5.4.3 Oscillator Settling Time after Watch Mode is Cleared
  - 5.4.4 Notes on External Input Signal Changes before/after Watch Mode
- 5.5 Subsleep Mode
  - 5.5.1 Transition to Subsleep Mode
  - 5.5.2 Clearing Subsleep Mode
- 5.6 Subactive Mode
  - 5.6.1 Transition to Subactive Mode
  - 5.6.2 Clearing Subactive Mode
  - 5.6.3 Operating Frequency in Subactive Mode
- 5.7 Active (Medium-Speed) Mode
  - 5.7.1 Transition to Active (Medium-Speed) Mode
  - 5.7.2 Clearing Active (Medium-Speed) Mode
  - 5.7.3 Operating Frequency in Active (Medium-Speed) Mode
- 5.8 Direct Transfer
  - 5.8.1 Overview of Direct Transfer
  - 5.8.2 Direct Transition Times
  - 5.8.3 Notes on External Input Signal Changes before/after Direct Transition
- 5.9 Module Standby Mode
  - 5.9.1 Setting Module Standby Mode
  - 5.9.2 Clearing Module Standby Mode
Section 6 ROM
- 6.1 Overview
  - 6.1.1 Block Diagram
- 6.2 PROM Mode
  - 6.2.1 Setting to PROM Mode
  - 6.2.2 Socket Adapter Pin Arrangement and Memory Map
- 6.3 Programming
  - 6.3.1 Writing and Verifying
  - 6.3.2 Programming Precautions
- 6.4 Reliability of Programmed Data
Section 7 RAM
- 7.1 Overview
  - 7.1.1 Block Diagram
Section 8 I/O Ports
- 8.1 Overview
- 8.2 Port 1
  - 8.2.1 Overview
  - 8.2.2 Register Configuration and Description
  - 8.2.3 Pin Functions
  - 8.2.4 Pin States
  - 8.2.5 MOS Input Pull-Up
- 8.3 Port 2 [Chip Internal I/O Port]
  - 8.3.1 Overview
  - 8.3.2 Register Configuration and Description
  - 8.3.3 Function
  - 8.3.4 States
- 8.3.4 States
- 8.4 Port 3
  - 8.4.1 Overview
  - 8.4.2 Register Configuration and Description
  - 8.4.3 Pin Functions
  - 8.4.4 Pin States
  - 8.4.5 MOS Input Pull-Up
- 8.5 Port 4*
  - 8.5.1 Overview
  - 8.5.2 Register Configuration and Description
  - 8.5.3 Pin Functions
  - 8.5.4 Pin States
- 8.6 Port 5
  - 8.6.1 Overview
  - 8.6.2 Register Configuration and Description
  - 8.6.3 Pin Functions
  - 8.6.4 Pin States
  - 8.6.5 MOS Input Pull-Up
- 8.7 Port 6
  - 8.7.1 Overview
  - 8.7.2 Register Configuration and Description
  - 8.7.3 Pin Functions
  - 8.7.4 Pin States
  - 8.7.5 MOS Input Pull-Up
- 8.8 Port 7
  - 8.8.1 Overview
  - 8.8.2 Register Configuration and Description
  - 8.8.3 Pin Functions
  - 8.8.4 Pin States
- 8.9 Port 8
  - 8.9.1 Overview
  - 8.9.2 Register Configuration and Description
  - 8.9.3 Pin Functions
  - 8.9.4 Pin States
- 8.10 Port 9
  - 8.10.1 Overview
  - 8.10.2 Register Configuration and Description
  - 8.10.3 Pin Functions
  - 8.10.4 Pin States
- 8.11 Port A
  - 8.11.1 Overview
  - 8.11.2 Register Configuration and Description
  - 8.11.3 Pin Functions
  - 8.11.4 Pin States
- 8.12 Port B
  - 8.12.1 Overview
  - 8.12.2 Register Configuration and Description
- 8.13 Input/Output Data Inversion Function
  - 8.13.1 Overview
  - 8.13.2 Register Configuration and Descriptions
  - 8.13.3 Note on Modification of Serial Port Control Register
- 8.14 Application Note
  - 8.14.1 The Management of the Un-Use Terminal
Section 9 Timers
- 9.1 Overview
- 9.2 Timer A
  - 9.2.1 Overview
  - 9.2.2 Register Descriptions
  - 9.2.3 Timer Operation
  - 9.2.4 Timer A Operation States
  - 9.2.5 Application Note
- 9.3 Timer C
  - 9.3.1 Overview
  - 9.3.2 Register Descriptions
  - 9.3.3 Timer Operation
  - 9.3.4 Timer C Operation States
- 9.4 Timer F
  - 9.4.1 Overview
  - 9.4.2 Register Descriptions
  - 9.4.3 CPU Interface
  - 9.4.4 Operation
  - 9.4.5 Application Notes
- 9.5 Timer G
  - 9.5.1 Overview
  - 9.5.2 Register Descriptions
  - 9.5.3 Noise Canceler
  - 9.5.4 Operation
  - 9.5.5 Application Notes
  - 9.5.6 Timer G Application Example
- 9.6 Watchdog Timer
  - 9.6.1 Overview
  - 9.6.2 Register Descriptions
  - 9.6.3 Timer Operation
  - 9.6.4 Watchdog Timer Operation States
Section 10 Serial Communication Interface
- 10.1 Overview
- 10.2 SCI1 [Chip Internal Function]
  - 10.2.1 Overview
  - 10.2.2 Register Descriptions
  - 10.2.3 Operation
  - 10.2.4 Interrupt Source
  - 10.2.5 Application Note
- 10.3 SCI3
  - 10.3.1 Overview
  - 10.3.2 Register Descriptions
  - 10.3.3 Operation
  - 10.3.4 Interrupts
  - 10.3.5 Application Notes
Section 11 A/D Converter
- 11.1 Overview
  - 11.1.1 Features
  - 11.1.2 Block Diagram
  - 11.1.3 Pin Configuration
  - 11.1.4 Register Configuration
- 11.2 Register Descriptions
  - 11.2.1 A/D Result Registers (ADRRH, ADRRL)
  - 11.2.2 A/D Mode Register (AMR)
  - 11.2.3 A/D Start Register (ADSR)
  - 11.2.4 Clock Stop Register 1 (CKSTPR1)
- 11.3 Operation
  - 11.3.1 A/D Conversion Operation
  - 11.3.2 Start of A/D Conversion by External Trigger Input
  - 11.3.3 A/D Converter Operation Modes
- 11.4 Interrupts
- 11.5 Typical Use
- 11.6 Application Notes
Section 12 FLEX TM Roaming Decoder II
- 12.1 Overview
  - 12.1.1 Features
  - 12.1.2 System Block Diagram
  - 12.1.3 Functional Block Diagram
- 12.2 SPI Packets
  - 12.2.1 Packet Communication Initiated by the Host
  - 12.2.2 Packet Communication Initiated by the FLEX decoder
  - 12.2.3 Host-to-Decoder Packet Map
  - 12.2.4 Decoder-to-Host Packet Map
- 12.3 Host-to-Decoder Packet Descriptions
  - 12.3.1 Checksum Packet
  - 12.3.2 Configuration Packet
  - 12.3.3 Control Packet
  - 12.3.4 All Frame Mode Packet
  - 12.3.5 Operator Messaging Address Enable Packet
  - 12.3.6 Roaming Control Packet
  - 12.3.7 Timing Control Packet
  - 12.3.8 Receiver Line Control Packet
  - 12.3.9 Receiver Control Configuration Packets
  - 12.3.10 Frame Assignment Packets
  - 12.3.11 User Address Enable Packet
  - 12.3.12 User Address Assignment Packets
- 12.4 Decoder-to-Host Packet Descriptions
  - 12.4.1 Block Information Word Packet
  - 12.4.2 Address Packet
  - 12.4.3 Vector Packet
  - 12.4.4 Message Packet
  - 12.4.5 Roaming Status Packet
  - 12.4.6 Receiver Shutdown Packet
  - 12.4.7 Status Packet
  - 12.4.8 Part ID Packet
- 12.5 Application Notes
  - 12.5.1 Receiver Control
  - 12.5.2 Message Building
  - 12.5.3 Building a Fragmented Message
  - 12.5.4 Operation of a Temporary Address
  - 12.5.5 Using the Receiver Shutdown Packet
- 12.6 Timing Diagrams (Reference Data)
  - 12.6.1 SPI Timing
  - 12.6.2 Start-up Timing
  - 12.6.3 Reset Timing
Section 13 Electrical Characteristics
- 13.1 Absolute Maximum Ratings
- 13.2 Electrical Characteristics
  - 13.2.1 Power Supply Voltage and Operating Range
  - 13.2.2 DC Characteristics
  - 13.2.3 AC Characteristics
  - 13.2.4 A/D Converter Characteristics
- 13.3 Operation Timing
- 13.4 Output Load Circuit
- 13.5 Resonator Equivalent Circuit
- 13.6 Usage Note
Appendix A CPU Instruction Set
- A.1 Instructions
- A.2 Operation Code Map
- A.3 Number of Execution States
Appendix B Internal I/O Registers
- B.1 Addresses
- B.2 Functions
Appendix C I/O Port Block Diagrams
- C.1 Block Diagrams of Port 1
- C.2 Block Diagrams of Port 2 [Chip Internal I/O Port]
- C.3 Block Diagrams of Port 3
- C.4 Block Diagrams of Port 4
- C.5 Block Diagram of Port 5
- C.6 Block Diagram of Port 6
- C.7 Block Diagram of Port 7
- C.8 Block Diagrams of Port 8
- C.9 Block Diagram of Port 9
- C.10 Block Diagram of Port A
- C.11 Block Diagram of Port B
Appendix D Port States in the Different Processing States
Appendix E List of Product Codes
Appendix F Package Dimensions
Colophon

Contents

Section 1

Overview

............................................................................................................

1.1 Overview ............................................................................................................................

1.2

Internal Block Diagram ......................................................................................................

1.3

Pin Arrangement and Functions.........................................................................................

1.3.1 Pin

Arrangement ...................................................................................................

1.3.2 Pin

Functions.........................................................................................................

Section 2

CPU

.....................................................................................................................

2.1 Overview ............................................................................................................................ 13

2.1.1 Features .................................................................................................................

2.1.2 Address

Space.......................................................................................................

2.1.3 Register

Configuration .......................................................................................... 14

2.2 Register

Descriptions .........................................................................................................

2.2.1 General

Registers .................................................................................................. 15

2.2.2 Control

Registers...................................................................................................

2.2.3

Initial Register Values...........................................................................................

2.3 Data

Formats ...................................................................................................................... 17

2.3.1

Data Formats in General Registers .......................................................................

2.3.2

Memory Data Formats .......................................................................................... 19

2.4 Addressing

Modes.............................................................................................................. 20

2.4.1 Addressing

Modes.................................................................................................

2.4.2

Effective Address Calculation...............................................................................

2.5 Instruction

Set .................................................................................................................... 26

2.5.1

Data Transfer Instructions.....................................................................................

2.5.2 Arithmetic

Operations...........................................................................................

2.5.3 Logic

Operations...................................................................................................

2.5.4

Shift Operations .................................................................................................... 31

2.5.5 Bit

Manipulations.................................................................................................. 33

2.5.6 Branching

Instructions .......................................................................................... 37

2.5.7

System Control Instructions.................................................................................. 39

2.5.8

Block Data Transfer Instruction............................................................................ 40

2.6

Basic Operational Timing .................................................................................................. 42
2.6.1

Access to On-Chip Memory (RAM, ROM) .........................................................

2.6.2

Access to On-Chip Peripheral Modules................................................................ 43

2.7 CPU

States .........................................................................................................................

2.7.1 Overview...............................................................................................................

2.7.2

Program Execution State.......................................................................................

2.7.3

Program Halt State ................................................................................................ 46

2.7.4 Exception-Handling State .....................................................................................

Электронный компонент: H83935R

Document Outline