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Электронный компонент: HB2881000A5

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Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi's Sales Dept. regarding specifications.
HB2881000A5
FLASH ATA Card
1 GByte
ADE-203-1182 (Z)
Preliminary
Rev. 0.0
May. 23, 2000
Description
HB2881000A5 is Flash ATA card. This card complies with PC card ATA standard and is suitable for the
usage of data storage memory medium for PC or any other electric equipment. This card is equipped with
Hitachi 256 Mega bit Flash memory. This card is suitable for ISA (Industry Standard Architecture) bus
interface standard, and read/write unit is 1 sector (512 bytes) sequential access. By using this card it is
possible to operate good performance for the system which have PC card slots.
Features
PC card ATA standard specification
68 pin two pieces connector and Type II (5 mm)
3.3 V/5 V single power supply operation
ISA standard and Read/Write unit is 512 bytes (sector) sequential access
Sector Read/Write transfer rate: 8MB/sec burst
Card density is 1 Giga bytes
This card is equipped Hitachi 256 Mega bit Flash memory
3 variations of mode access
Memory card mode
I/O card mode
True IDE mode
Internal self-diagnostic program operates at V
CC
power on
High reliability based on internal ECC (Error Correcting Code) function
Data write is 300,000 cycles
Data reliability is 1 error in 10
14
bits read.
Auto Sleep Function
HB2881000A5
2
Card Line Up*
1
Type No.
Card density Capacity*
4
Total sectors/
card
*
3
Sectors/
track
*
2
Number of
head
Number of
cylinder
HB2881000A5 1 GB
1,025,482,752 byte 2,002,896
63
16
1987
Notes: 1. These data are written in ID.
2. Total tracks = number of head
number of cylinder.
3. Total sectors/card = sectors/track
number of head
number of cylinder.
4. It is the logical address capacity including the area which is used for file system.
HB2881000A5
3
Card Pin Assignment
Memory card mode
I/O card mode
True IDE mode
Pin No.
Signal name
I/O
Signal name
I/O
Signal name
I/O
1
GND
--
GND
--
GND
--
2
D3
I/O
D3
I/O
D3
I/O
3
D4
I/O
D4
I/O
D4
I/O
4
D5
I/O
D5
I/O
D5
I/O
5
D6
I/O
D6
I/O
D6
I/O
6
D7
I/O
D7
I/O
D7
I/O
7
-CE1
I
-CE1
I
-CE1
I
8
A10
I
A10
I
A10
I
9
-OE
I
-OE
I
-ATASEL
I
10
--
--
--
--
--
--
11
A9
I
A9
I
A9
I
12
A8
I
A8
I
A8
I
13
--
--
--
--
--
--
14
--
--
--
--
--
--
15
-WE
I
-WE
I
-WE
I
16
RDY/-BSY
O
-IREQ
O
INTRQ
O
17
VCC
--
VCC
--
VCC
--
18
--
--
--
--
--
--
19
--
--
--
--
--
--
20
--
--
--
--
--
--
21
--
--
--
--
--
--
22
A7
I
A7
I
A7
I
23
A6
I
A6
I
A6
I
24
A5
I
A5
I
A5
I
25
A4
I
A4
I
A4
I
26
A3
I
A3
I
A3
I
27
A2
I
A2
I
A2
I
28
A1
I
A1
I
A1
I
29
A0
I
A0
I
A0
I
30
D0
I/O
D0
I/O
D0
I/O
31
D1
I/O
D1
I/O
D1
I/O
32
D2
I/O
D2
I/O
D2
I/O
33
WP
O
-IOIS16
O
-IOIS16
O
HB2881000A5
4
Memory card mode
I/O card mode
True IDE mode
Pin No.
Signal name
I/O
Signal name
I/O
Signal name
I/O
34
GND
--
GND
--
GND
--
35
GND
--
GND
--
GND
--
36
-CD1
O
-CD1
O
-CD1
O
37
D11
I/O
D11
I/O
D11
I/O
38
D12
I/O
D12
I/O
D12
I/O
39
D13
I/O
D13
I/O
D13
I/O
40
D14
I/O
D14
I/O
D14
I/O
41
D15
I/O
D15
I/O
D15
I/O
42
-CE2
I
-CE2
I
-CE2
I
43
-VS1
O
-VS1
O
-VS1
O
44
-IORD
I
-IORD
I
-IORD
I
45
-IOWR
I
-IOWR
I
-IOWR
I
46
--
--
--
--
--
--
47
--
--
--
--
--
--
48
--
--
--
--
--
--
49
--
--
--
--
--
--
50
--
--
--
--
--
--
51
VCC
--
VCC
--
VCC
--
52
--
--
--
--
--
--
53
--
--
--
--
--
--
54
--
--
--
--
--
--
55
--
--
--
--
--
--
56
-CSEL
I
-CSEL
I
-CSEL
I
57
-VS2
O
-VS2
O
-VS2
O
58
RESET
I
RESET
I
-RESET
I
59
-WAIT
O
-WAIT
O
IORDY
O
60
-INPACK
O
-INPACK
O
-INPACK
O
61
-REG
I
-REG
I
-REG
I
62
BVD2
I/O
-SPKR
I/O
-DASP
I/O
63
BVD1
I/O
-STSCHG
I/O
-PDIAG
I/O
64
D8
I/O
D8
I/O
D8
I/O
65
D9
I/O
D9
I/O
D9
I/O
66
D10
I/O
D10
I/O
D10
I/O
67
-CD2
O
-CD2
O
-CD2
O
68
GND
--
GND
--
GND
--
HB2881000A5
5
Card Pin Explanation
Signal name
Direction Pin No.
Description
A10 to A0
(PC Card Memory mode)
I
8, 11, 12, 22, 23,
24, 25, 26, 27,
28, 29
Address bus is A10 to A0. A10 is MSB and A0 is
LSB.
A10 to A0
(PC Card I/O mode)
A2 to A0
(True IDE mode)
27, 28, 29
Address bus is A10 to A0. Only A2 to A0 are used,
A10 to A3 should be grounded by the host.
BVD1
(PC Card Memory mode)
I/O
63
BVD1 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-STSCHG
(PC Card I/O mode)
-STSCHG is used for changing the status of
Configuration and status register in attribute area.
-PDIAG
(True IDE mode)
-PDIAG is the Pass Diagnostic signal in Master/Slave
handshake protocol.
BVD2
(PC Card Memory mode)
I/O
62
BVD2 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-SPKR
(PC Card I/O mode)
-SPKR outputs speaker signals. This output line is
constantly driven to a high state since this product
does not support the audio function.
-DASP
(True IDE mode)
-DASP is the Disk Active/Slave Present signal in the
Master/Slave handshake protocol.
-CD1, -CD2
(PC Card Memory mode)
O
36, 67
-CD1 and -CD2 are the card detection signals. -CD1
and -CD2 are connected to ground in this card, so
host can detect that the card is inserted or not.
-CD1, -CD2
(PC Card I/O mode)
-CD1, -CD2
(True IDE mode)
-CE1, -CE2
(PC Card Memory mode)
Card Enable
I
7, 42
-CE1 and -CE2 are low active card select signals.
Byte/Word/Odd byte mode are defined by combination
of -CE1, -CE2 and A0.
-CE1, -CE2
(PC Card I/O mode)
Card Enable
-CE1, -CE2
(True IDE mode)
-CE2 is used for select the Alternate Status Register
and the Device Control Register while -CE1 is the chip
select for the other task file registers.