HB56SW3272ESK-5/6

256MB Buffered EDO DRAM DIMM

32-Mword

72-bit, 4k Refresh, 2 Bank Module

(36 pcs of 16M

4 components)

ADE-203-872B (Z)

Rev. 1.0

June 23, 1998

Description

The HB56SW3272ESK belong to 8-byte DIMM (Dual in-line Memory Module) family , and have been
developed an optimized main memory solution for 4 and 8-byte processor applications. The
HB56SW3272ESK is 32 M

72 Dynamic RAM Module, mounted 36 pieces of 64-Mbit DRAM

(HM5165405) sealed in TCP package and 2 pieces of 16-bit BiCMOS line driver sealed in TSSOP
package. The HB56SW3272ESK offer Extended Data Out (EDO) Page Mode as a high speed access
mode. An outline of the HB56SW3272ESK are 168-pin socket type package (dual lead out). Therefore, the
HB56SW3272ESK make high density mounting possible without surface mount technology. The
HB56SW3272ESK provide common data inputs and outputs. Decoupling capacitors are mounted beside
each TCP on its module board.

Note:

Do not push the cover or drop the modules in order to protect from mechanical defects, which

would be electrical defects.

Features

168-pin socket type package (Dual lead out)

Lead pitch : 1.27 mm

Single 3.3 V supply (

0.3 V)

High speed

Access time: t

RAC

= 50 ns/60 ns (max)

Access time: t

CAC

= 18 ns/20 ns (max)

Low power dissipation

Active mode: 8.78 W/7.49 W (max)

Standby mode (TTL): 295.2 mW (max)

JEDEC standard outline buffered 8-byte DIMM

Buffered input except RAS and DQ

HB56SW3272ESK-5/6

Pin No.

Signal name Pin No.

Signal name

127

DQ0

DQ36

128

DQ1

DQ37

129

DQ2

DQ38

130

DQ3

DQ39

131

132

PDE

DQ4

DQ40

133

DQ5

DQ41

134

DQ6

DQ42

135

DQ7

DQ18

DQ43

136

DQ54

DQ8

DQ19

DQ44

137

DQ55

138

DQ9

DQ20

DQ45

139

DQ56

DQ10

DQ21

DQ46

140

DQ57

DQ11

DQ22

DQ47

141

DQ58

DQ12

DQ23

100

DQ48

142

DQ59

DQ13

101

DQ49

143

DQ24

102

144

DQ60

DQ14

103

DQ50

145

DQ15

104

DQ51

146

DQ16

105

DQ52

147

DQ17

106

DQ53

148

DQ25

107

149

DQ61

DQ26

108

150

DQ62

DQ27

109

151

DQ63

110

152

DQ28

111

153

DQ64

DQ29

112

154

DQ65

DQ30

113

155

DQ66

DQ31

114

156

DQ67

115

157

DQ32

116

158

DQ68

DQ33

117

159

DQ69

DQ34

118

160

DQ70

DQ35

119

161

DQ71

HB56SW3272ESK-5/6

Pin Arrangement (cont)

Pin No.

Signal name Pin No.

Signal name

120

162

PD1

121

163

PD2

A10

PD3

122

A11

164

PD4

PD5

123

165

PD6

PD7

124

166

PD8

ID0 (V

)

125

167

ID1 (V

)

126

168

Pin Description

Pin name

Function

A0 to A11, B0

Address input

Row address (D0 to D35)

A0 to A11, B0

Column address (D0 to D35)

A0 to A11, B0

Refresh address (D0 to D35)

A0 to A11, B0

DQ0 to DQ71

Data input/output

0 to

Row address strobe (

RAS

)

Column address strobe (

CAS

)

Read/Write enable

Output enable

PD1 to PD8

Presence detect

ID0 , ID1

ID bit

PDE

Presence detect enable

Power supply

Ground

No connection

HB56SW3272ESK-5/6

Block Diagram

D0 to D8 , D18 to D26

A1 to A11

D0 to D35

D9 to D17 , D27 to D35

Capacitor

20 pcs

D0 to D35, 16-bit driver

PD1 to PD8

SS or

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

I/O

D18

CAS RAS WE OE

D19

D20

D21

D22

D23

D24

D25

D26

I/O

D10

D11

D12

D13

D14

D15

D16

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ64

DQ65

DQ66

DQ67

DQ68

DQ69

DQ70

DQ71

D17

I/O

D27

D28

D29

D30

D31

D32

D33

D34

D35

I/O

* D0 to D35 : HM5165405

: 16-bit driver

HB56SW3272ESK-5/6

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

Terminal voltage on any pin relative to V

0.5 to +4.6

Power supply voltage relative to V

0.5 to +4.6

Short circuit output current

Iout

Power dissipation

Storage temperature range

Tstg

55 to +125

DC Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Supply voltage

3.0

3.3

3.6

1, 2

Input high voltage

2.0

+ 0.3

Input low voltage

0.3

0.8

Ambient temperature range

Ambient illuminance

100

Notes: 1. All voltage referred to V

2. The supply voltage with all V

pins must be on the same level. The supply voltage with all V

pins must be on the same level.

HB56SW3272ESK-5/6

DC Characteristics

50 ns

60 ns

Parameter

Symbol Min

Max

Min

Max

Unit

Test conditions

Operating current*

, *

CC1

2440

2080

= min

Standby current

CC2

TTL interface

RAS

CAS

= V

Dout = High-Z

CMOS interface

RAS

CAS

0.2 V

Dout = High-Z

RAS

-only refresh current*

CC3

2440

2080

= min

Standby current*

CC5

190

RAS

= V

CAS

= V

Dout = enable

CAS

-before-

RAS

refresh

current

CC6

2440

2080

= min

EDO page mode current*

CC7

2080

1900

RAS

= V

CAS

cycle,

HPC

= t

HPC

min

Input leakage current

0 V

Vin

+ 0.3 V

Output leakage current

0 V

Vout

Dout = disable

Output high voltage

2.4

High Iout = 2 mA

Output low voltage

0.4

Low Iout = 2 mA

Notes : 1. I

depends on output load condition when the device is selected. I

max is specified at the

output open condition.

2. Address can be changed once or less while

RAS

= V

3. Measured with one sequential address change per EDO cycle, t

HPC

Capacitance (Ta = 25

C, V

= 3.3 V

0.3 V)

Parameter

Symbol

Typ

Max

Unit

Notes

Input capacitance (Address)

Input capacitance (

CAS

)

Input capacitance (

RAS

)

I/O capacitance (DQ)

I/O

1, 2

Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

CAS

= V

to disable Dout.

HB56SW3272ESK-5/6

AC Characteristics (Ta = 0 to +70

C, V

= 3.3 V

0.3 V, V

= 0 V) *

, *

Test Conditions

Input rise and fall time: 2 ns

Input levels: V

= 0 V, V

= 3 V

Input timing reference levels: 0.8 V, 2.0 V

Output timing reference levels: 0.8 V, 2.0 V

Output load: 1 TTL gate + C

(100 pF) (Including scope and jig)

Ambient illuminance: Under 100 lx

Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)

50 ns

60 ns

Parameter

Symbol Min

Max

Min

Max

Unit

Notes

Random read or write cycle time

104

RAS

precharge time

CAS

precharge time

RAS

pulse width

RAS

10000

CAS

pulse width

CAS

10000

Row address setup time

ASR

Row address hold time

RAH

Column address setup time

ASC

Column address hold time

CAH

RAS

CAS

delay time

RCD

RAS

to column address delay time

RAD

RAS

hold time

RSH

CAS

hold time

CSH

CAS

RAS

precharge time

CRP

to Din delay time

OED

delay time from Din

DZO

CAS

delay time from Din

DZC

Transition time (rise and fall)

HB56SW3272ESK-5/6

Read Cycle

50 ns

60 ns

Parameter

Symbol Min

Max

Min

Max

Unit

Notes

Access time from

RAS

RAC

8, 9

Access time from

CAS

CAC

9, 10, 17

Access time from address

9, 11, 17

Access time from

OEA

Read command setup time

RCS

Read command hold time to

CAS

RCH

Read command hold time from

RAS

RCHR

Read command hold time to

RAS

RRH

Column address to

RAS

lead time

RAL

Column address to

CAS

lead time

CAL

CAS

to output in low-Z

CLZ

Output data hold time

Output data hold time from

OHO

Output buffer turn-off time

OFF

13, 21

Output buffer turn-off to

OEZ

CAS

to Din delay time

CDD

Output data hold time from

RAS

OHR

Output buffer turn-off to

RAS

OFR

13, 21

Output buffer turn-off to

WEZ

to Din delay time

WED

RAS

to Din delay time

RDD

Write Cycle

50 ns

60 ns

Parameter

Symbol Min

Max

Min

Max

Unit

Notes

Write command setup time

WCS

Write command hold time

WCH

Write command pulse width

Write command to

RAS

lead time

RWL

Write command to

CAS

lead time

CWL

Data-in setup time

Data-in hold time

HB56SW3272ESK-5/6

Read-Modify-Write Cycle

50 ns

60 ns

Parameter

Symbol Min

Max

Min

Max

Unit

Notes

Read-modify-write cycle time

RWC

116

140

RAS

delay time

RWD

CAS

delay time

CWD

Column address to

delay time

AWD

hold time from

OEH

Refresh Cycle

50 ns

60 ns

Parameter

Symbol Min

Max

Min

Max

Unit

Notes

CAS

setup time (CBR refresh cycle)

CSR

CAS

hold time (CBR refresh cycle)

CHR

setup time (CBR refresh cycle)

WRP

hold time (CBR refresh cycle)

WRH

RAS

precharge to

CAS

hold time

RPC

EDO Page Mode Cycle

50 ns

60 ns

Parameter

Symbol Min

Max

Min

Max

Unit

Notes

EDO page mode cycle time

HPC

EDO page mode

RAS

pulse width

RASP

100000 --

100000 ns

Access time from

CAS

precharge

CPA

9, 17

RAS

hold time from

CAS

precharge

CPRH

Output data hold time from

CAS

low

DOH

9, 22

CAS

hold time referred

COL

CAS

setup time

COP

Read command hold time from

CAS

precharge

RCHC

Write pulse width during

CAS

precharge

WPE

precharge time

OEP

HB56SW3272ESK-5/6

EDO Page Mode Read-Modify-Write Cycle

50 ns

60 ns

Parameter

Symbol Min

Max

Min

Max

Unit

Notes

EDO page mode read- modify-write
cycle time

HPRWC

delay time from

CAS

precharge

CPW

Refresh

Parameter

Symbol

Max

Unit

Notes

Refresh period

REF

4096 cycles

Notes: 1. AC measurements assume t

= 2 ns.

2. An initial pause of 200

s is required after power up followed by a minimum of eight initialization

cycles (any combination of cycles containing

RAS

-only refresh or

CAS

-before-

RAS

refresh).

3. Operation with the t

RCD

(max) limit insures that t

RAC

(max) can be met, t

RCD

(max) is specified as a

reference point only; if t

RCD

is greater than the specified t

RCD

(max) limit, than the access time is

controlled exclusively by t

CAC

4. Operation with the t

RAD

(max) limit insures that t

RAC

(max) can be met, t

RAD

(max) is specified as a

reference point only; if t

RAD

is greater than the specified t

RAD

(max) limit, then access time is

controlled exclusively by t

5. Either t

OED

or t

CDD

must be satisfied.

6. Either t

DZO

or t

DZC

must be satisfied.

7. V

(min) and V

(max) are reference levels for measuring timing of input signals. Also, transition

times are measured between V

(min) and V

(max).

8. Assumes that t

RCD

(max) and t

RAD

(max). If t

RCD

or t

RAD

is greater than the maximum

recommended value shown in this table, t

RAC

exceeds the value shown.

9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.

10. Assumes that t

RCD

(max) and t

RCD

+ t

CAC

(max)

RAD

+ t

(max).

11. Assumes that t

RAD

(max) and t

RCD

+ t

CAC

(max)

RAD

+ t

(max).

12. Either t

RCH

or t

RRH

must be satisfied for a read cycles.

13. t

OFF

(max), t

OEZ

(max), t

WEZ

(max) and t

OFR

(max) define the time at which the outputs achieve the

open circuit condition and are not referred to output voltage levels.

14. t

WCS

, t

RWD

, t

CWD

, t

AWD

and t

CPW

are not restrictive operating parameters. They are included in the

data sheet as electrical characteristics only; if t

WCS

(min), the cycle is an early write cycle

and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t

RWD

(min), t

CWD

(min), and t

AWD

(min), or t

CWD

(min), t

AWD

(min) and t

CPW

(min), the cycle is a read-modify-write and the data output will contain data read from the

selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.

15. t

and t

are referred to

CAS

leading edge in early write cycles and to

leading edge in

delayed write or read-modify-write cycles.

16. t

RASP

defines

RAS

pulse width in EDO page mode cycles.

17. Access time is determined by the longest among t

, t

CAC

and t

CPA

18. In delayed write or read-modify-write cycles,

must disable output buffer prior to applying data

to the device.

HB56SW3272ESK-5/6

19. When output buffers are enabled once, sustain the low impedance state until valid data is

obtained. When output buffer is turned on and off within a very short time, generally it causes
large V

line noise, which causes to degrade V

min/V

max level.

20. t

HPC

(min) can be achieved during a series of EDO page mode write cycles or EDO page mode

read cycles. If both write and read operation are mixed in a EDO page mode

RAS

cycle (EDO

page mode mix cycle (1), (2)), minimum value of

CAS

cycle (t

CAS

+ t

+ 2 t

) becomes greater

than the specified t

HPC

(min) value. The value of

CAS

cycle time of mixed EDO page mode is

shown in EDO page mode mix cycle (1) and (2).

21. Data output turns off and becomes high impedance from later rising edge of

RAS

and

CAS

Hold time and turn off time are specified by the timing specifications of later rising edge of

RAS

and

CAS

between t

OHR

and t

and between t

OFR

and t

OFF

22. t

DOH

defines the time at which the output level go cross. V

= 0.8 V, V

= 2.0 V of output timing

reference level.

23. XXX: H or L (H: V

(min)

(max), L: V

(min)

(max))

///////: Invalid Dout

When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V

or V

HB56SW3272ESK-5/6

EDO Page Mode Read Cycle (1)

Din

Dout

Address

RAS

CAS

RCH

RRH

DZC

CDD

RDD

High-Z

OFR

OEZ

OHO

OFF

OHR

COL

CPA

CAC

OEA

RAC

CAC

CPA

OEZ

OEA

OEZ

CAC

RASP

COP

CAS

CAL

CSH

HPC

CRP

ASR

RAH

Column 1

Column 2

Column 3

Column 4

CAH

ASC

CAH

ASC

CAH

ASC

WED

RAL

Row

Dout 2

Dout 4

Dout 1

CAS

RCS

Dout 3

OHO

CPRH

HPC

OEA

WEZ

DZO

OED

OHO

DOH

RCH

WPE

RCHR

CAL

RSH

RCHC

CPA

ASC

OEP

HB56SW3272ESK-5/6

EDO Page Mode Read Cycle (2)

Din

Address

DZC

CDD

RDD

High-Z

OFR

OEZ

OHO

OFF

OHR

COL

CPA

CAC

OEA

RAC

DOH

OEZ

CAC

COP

ASR

RAH

CAH

ASC

CAH

ASC

CAH

ASC

WED

RAL

Dout 2

Dout 4

Dout 1

RCS

OHO

OEA

DZO

OED

DOH

CAC

RCHC

CPA

ASC

RAS

CAS

RCH

RRH

RASP

CAS

CSH

HPC

CRP

CAS

CAL

RSH

Dout

Dout 3

Dout 2

OHO

OEA

CPA

Column 2

Column 1

Row

Column 3

Column 4

OEP

HB56SW3272ESK-5/6

EDO Page Mode Delayed Write Cycle*

Din

Dout

Address

RAS

RASP

CRP

RSH

CAS

HPC

CAS

CSH

RCD

ASC

CAH

ASC

CAH

ASC

CAH

RAD

ASR

RAH

RCS

RWL

CWL

DZC

DZO

OED

DZO

OED

DZO

OED

OEH

OEZ

CLZ

OEZ

CLZ

OEZ

Invalid Dout

Din

Column N

Column 2

Column 1

Row

High-Z

CAS

OEP

HB56SW3272ESK-5/6

EDO Page Mode Read-Modify-Write Cycle*

Din

Dout

Address

RAS

RASP

CRP

HPRWC

RCD

CAS

RAD

ASR

ASC

RAH

CAH

CWL

CPW

CWL

CPW

CWL

RWD

AWD

CWD

RCS

CWD

RCS

CWD

RCS

DZC

DZO

OEH

OEP

OEH

RAC

OEZ

CLZ

Dout N

Dout 2

Dout 1

Din

Column N

Column 2

Column 1

Row

RWL

OHO

OEA

CAC

OEZ

CLZ

OHO

OEA

CAC

CPA

OEZ

CLZ

OHO

OEA

CAC

CPA

High-Z

OED

RSH

CAS

HB56SW3272ESK-5/6

EDO Page Mode Mix Cycle (1)*

Dout

Address

RAS

CAS

RCH

RRH

CDD

RDD

High-Z

OFR

OEZ

OHO

OFF

CPA

CAC

CPA

OEZ

OEA

RASP

CAS

CRP

ASR

RAH

Column 1

Column 2

Column 3

Column 4

ASC

CAH

ASC

CAH

RAL

CAL

Row

Dout 2

Dout 4

CPA

CAS

WCS

Dout 3

CWL

WCH

WED

WEZ

Din 3

Din 1

OEA

OED

OEP

CAC

ASC

CPW

AWD

OHO

CAL

RCS

CSH

RCD

RSH

DOH

ASC

Din

HB56SW3272ESK-5/6

EDO Page Mode Mix Cycle (2) *

Din

Dout

Address

RAS

CAS

RCH

RRH

CDD

RDD

High-Z

OFR

OEZ

OHO

OFF

CPA

CAC

OEZ

OEA

RASP

CAS

CSH

CRP

ASR

RAH

Column 1

Column 2

Column 3

Column 4

ASC

CAH

ASC

CAH

ASC

CAH

RAL

RCS

Row

Dout 1

Dout 4

CPA

CAS

CWL

Dout 3

OHO

WED

WEZ

Din 3

Din 2

OEA

CAC

CPW

RCH

RCS

WCH

RAC

OED

COL

OEA

OHO

OEZ

OED

RCS

CAL

RCD

RCHR

WCS

RSH

ASC

OEP

COP

HB56SW3272ESK-5/6

Physical Outline

HB56SW3272ESK Series

3.00

133.35

0.118

5.250

127.35

5.014

3.00

0.118

8.89

11.43

36.83

54.61

0.350

0.450

2.150

1.450

Front side

Back side

1.27

0.10

4.00 min

0.157 min

0.050

0.004

4.80

0.189

4.00

0.157

17.80

0.701

38.10

1.500

168

3.00

0.118

Component area

(Front)

Component area

(Back)

6.35

0.250

Detail B and C

Detail A

0.20

0.15

2.50

0.20

0.0079

0.0059

0.098

0.0079

3.125

0.125

0.123

0.005

1.27

0.050

1.00

0.05

0.039

0.002

2.00

0.10

0.079

0.004

3.175

0.125

Unit: mm

inch

HB56SW3272ESK-5/6

Cautions

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copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

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received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

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Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109

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16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533

Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HB56SW3272ESK-5