HD155101BF
RF Single-chip Linear IC for GSM and EGSM Systems
ADE-207-256A (Z)
2nd Edition
September 1998
Description
The HD155101BF was developed for GSM and EGSM cellular systems, and integrates most of the
functions of a transceiver. The HD155101BF incorporates the bias circuit for a RF LNA, a 1st mixer, 1st-
IF amplifier, 2nd mixer, AGC amplifier and an IQ quadrature demodulator for the receiver, and an IQ
quadrature modulator and offset PLL for the transmitter. Also, on chip are the dividers for the 1st & 2nd
local oscillator signals and 90 phase splitter. Moreover the HD155101BF includes control circuits to
implement power saving modes. These functions can operate down to 2.7 V and are housed in a 48-pin
LQFP SMD package.
Hence the HD155101BF can form a small size transceiver handset for GSM and EGSM by adding a PLL
frequency synthesizer IC, a power amplifier and some external components. See page 7 "Configuration".
The HD155101BF is fabricated using a 0.6
m double-polysilicon Bi-CMOS process.
Functions
Receiver (RX)
Low Noise Amplifier (LNA) bias circuit
1st mixer
IF amplifier
2nd mixer
Automatic gain control amplifier (AGC)
IQ demodulator with 90
phase splitter
Transmitter (TX)
IQ modulator with 90
phase splitter
Offset PLL
Down converter
Phase comparator
TX VCO driver
HD155101BF
2
Others
IF dividers
Power saving circuit
IFVCO
Features
Highly integrated RF processing for hand-portables
Wide operating frequency
RX:
RF: 925 to 960 MHz
1st IF: 130 to 300 MHz
2nd IF: 26 to 60 MHz
TX:
RF: 880 to 915 MHz
IF: 156 to 360 MHz
Offset PLL architecture reduces TX spurious
Low current consumption (Vcc = 3 V)
RX mode: 42.5 mA Typ (including IFVCO current (2.5 mA Typ)) + LNA transistor current (5.6 mA
Typ)
TX mode: 38.0 mA Typ (including IFVCO current (2.5 mA Typ))
Idle mode: 1
A Typ
Operating supply voltage:
Phase comparator and TX VCO driver circuits: 2.7 to 5.25 V
Other blocks: 2.7 to 3.6 V
Operating temperature range: 20 to +85
C
48 pin SMD Low Profile Quad Flat Package (LQFP): FP-48
HD155101BF
3
Pin Arrangement
The HD155101BF is housed in a 48-pin LQFP SMD package to which is suitable for applications where
space is limited. "Pin Functions" shows the arrangement and roles assigned for each pin of the
HD155101BF.
1
2
3
4
5
6
7
8
9
10
11
12
POONRX1
POONRX2
RFOUT
VCCLNA
GNDLNA
RFIN
POONTX
VCCPLL
GNDPLL
VCOIN
VCCCOMP
PLLOUT
36
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
(Top View)
18
17
16
15
14
13
35
34
33
32
31
30
29
28
27
26
25
MIX2OB
GNDAGC
VCCAGC
AGCOUT
AGCOUTB
VCCDIV
GNDDIV
VCONT
IOUT
IOUTB
QOUT
QOUTB
ICURAD
QINB
QIN
IINB
IIN
MODB
MOD
VCCIQ
IFLO
GNDIQ
IFVCOO
IFVCOI
MIX1IN
MIX1INB
GNDMIX1
VCCMIX1
RFLOIN
MIX1OUTB
MIX1OUT
VCCIF
GNDIF
IFIN
IFINB
MIX2O
HD155101BF
4
Pin Functions
Pin
No.
Symbol
Input/
Output
Meaning of symbol
Function
1
POONRX1
Input
PO
wer
ON
for
RX1
If `H', LNA and MIX1 are active.
Other receiver blocks don't care.
2
POONRX2
Input
PO
wer
ON
for
RX2
LNA and MIX1 don't care.
If `H', Other receiver blocks are active.
3
RFOUT
Output
RF
signal
OUT
put
Open collector type output of LNA.
The collector of LNA transistor.
4
VCCLNA
Vcc
VCC
of
LNA
block
Power supply of LNA
5
GNDLNA
Gnd
GND
of
LNA
block
Ground of LNA
6
RFIN
Input
RF
signal
IN
put
Input of LNA.
The base of LNA transistor
7
POONTX
Input
PO
wer
ON
for
TX
If `H', the blocks for transmitter are active.
The reciver blocks don't care.
8
VCCPLL
Vcc
VCC
of O
PLL
block
Power supply for offset PLL except phase
comparator
9
GNDPLL
Gnd
GND
of O
PLL
block
Ground of offset PLL
10
VCOIN
Input
VCO
signal
IN
put
Input of Tx. VCO signal
11
VCCCOMP
Vcc
VCC
of phase
COMP
arator
Power supply for just phase comparator of offset
PLL
12
PLLOUT
Output
O
PLL
OUT
put
Current output to control and modulate Tx. VCO
This pin should be connected external loop filter.
13
ICURAD
Input
I
CUR
rent
AD
just
This pin should be connected an external R to
determine charge pump current of phase
comparator
14
QINB
Input
Q
signal
IN
put
B
ar
Q negative signal input of IQ quadrature modulator
15
QIN
Input
Q
signal
IN
put
Q positive signal input of IQ quadrature modulator
16
IINB
Input
I
signal
IN
put
B
ar
I negative signal input of IQ quadrature modulator
17
IIN
Input
I
signal
IN
put
I positive signal input of IQ quadrature modulator
18
MODB
Output
MOD
ulator output
B
ar
Negative output of IQ quadrature modulator
19
MOD
Output
MOD
ulator output
Positive output of IQ quadrature modulator
20
VCCIQ
Vcc
VCC
of
IQ
block
Power supply of IQ block
21
IFLO
Input/
Output
IF
LO
cal signal
input/output
IF local signal input to be fed to divider
22
GNDIQ
Gnd
GND
of
IQ
block
Ground of IQ block
23
IFVCOO
Output
IFVCO
O
utput
Emitter of IFVCO transistor
24
IFVCOI
Input
IFVCO
I
nput
Base of IFVCO transistor
HD155101BF
5
Pin Function (cont)
Pin
No.
Symbol
Input/
Output
Meaning of symbol
Function
25
QOUTB
Output
Q
signal
OUT
put
B
ar
Q negative signal output of IQ quadrature
demodulator
26
QOUT
Output
Q
signal
OUT
put
Q positive signal output of IQ quadrature
demodulator
27
IOUTB
Output
I
signal
OUT
put
B
ar
I negative signal output of IQ quadrature
demodulator
28
IOUT
Output
I
signal
OUT
put
I positive signal output of IQ quadrature
demodulator
29
VCONT
Input
V
oltage of AGC
CONT
rol
The DC voltage input to control the power gain of
AGC
30
GNDDIV
Gnd
GND
of
DIV
ider block
Ground of divider to make IF local signals
31
VCCDIV
Vcc
VCC
of
DIV
ider block
Power supply of divider to make IF local signals
32
AGCOUTB
Output
AGC
OUT
put
B
ar
AGC negative signal output to be fed to IQ
quadrature demodulator
33
AGCOUT
Output
AGC
OUT
put
AGC positive signal output to be fed to IQ
quadrature demodulator
34
VCCAGC
Vcc
VCC
of
AGC
block
Power supply of AGC
35
GNDAGC
Gnd
GND
of
AGC
block
Ground of AGC
36
MIX2OB
Output
MIX2
O
utput
B
ar
2nd mixer (MIX2) negative signal output to be fed
to AGC
37
MIX2O
Output
MIX2
O
utput
2nd mixer (MIX2) positive signal output to be fed to
AGC
38
IFINB
Input
1st
IF
signal
IN
put
B
ar
IFAMP negative signal input for 1st IF signal
39
IFIN
Input
1st
IF
signal
IN
put
IFAMP positive signal input for 1st IF signal
40
GNDIF
Gnd
GND
of
IF
MIX2 block
Ground of IFAMP and 2nd mixer (MIX2)
41
VCCIF
Vcc
VCC
of
IF
MIX2 block
Power supply of IFAMP and 2nd mixer (MIX2)
42
MIX1OUT
Output
MIX1
O
utput
1st mixer (MIX1) positive signal output
43
MIX1OUTB
Output
MIX1
O
utput
B
ar
1st mixer (MIX1) negative signal output
44
RFLOIN
Input
RF
LO
cal signal
IN
put
RF 1st local signal input to be fed to 1st mixer
(MIX1) and the down converter of offset PLL
45
VCCMIX1
Vcc
VCC
of
MIX1
block
Power supply of 1st mixer (MIX1)
46
GNDMIX1
Gnd
GND
of
MIX1
block
Ground of 1st mixer (MIX1)
47
MIX1INB
Input
MIX1
I
nput
B
ar
1st mixer (MIX1) negative signal input
48
MIX1IN
Input
MIX1
I
nput
1st mixer (MIX1) positive signal input
PDF 
ZIP