HD404339 Series

Rev. 7.0

Sept. 1999

Description

The HD404339 Series is 4-bit HMCS400-Series microcomputer with large-capacity memory designed to
increase program productivity. Each microcomputer has an A/D converter, input capture timer, and a 32-
kHz oscillator circuit for clock use all built in. They also come with high-voltage I/O pins that can directly
drive a fluorescent display.

The HD404339 Series includes six chips: the HD404339 with 16-kword ROM; the HD4043312 with 12-
kword ROM; the HD404338 with 8-kword ROM; the HD404336 with 6-kword ROM; the HD404334 with
4-kword ROM; the HD4074339 with 16-kword PROM.

The HD4074339 is a PROM version ZTAT

microcomputer. Programs can be written to the PROM by a

PROM writer, which can dramatically shorten system development periods and smooth the process from
debugging to mass production. (The PROM program specifications are the same as for the 27256.)

ZTAT

: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

54 I/O pins

One input-only pin

53 input/output pins: 30 pins are high-voltage pins (40 V, max.)

On-chip A/D converter (8-bit

12-channel)

Three timers

One event counter input

One timer output

One input capture timer

8-bit clock-synchronous serial interface (1 channel)

Alarm output

Built-in oscillators

Ceramic or crystal oscillator

External clock drive is also possible

Subclock: 32.768-kHz crystal oscillator

HD404339 Series

Seven interrupt sources

Two by external sources

Three by timers

One each by the A/D converter and serial interface

Four low-power dissipation modes

Standby mode

Stop mode

Watch mode

Subactive mode

Instruction cycle time: 1

s (f

OSC

= 4 MHz, 1/4 division ratio)

1/4, 1/8, 1/16, 1/32 system clock division ratio can be selected

Ordering Information

Type

Product Name

Model Name

ROM (words)

RAM (digit)

Package

Mask ROM

HD404334

HD404334S

4,096

512

DP-64S

HD404334FS

FP-64B

HD404336

HD404336S

6,144

DP-64S

HD404336FS

FP-64B

HD404338

HD404338S

8,912

DP-64S

HD404338FS

FP-64B

HD4043312

HD4043312S

12,288

DP-64S

HD4043312FS

FP-64B

HD404339

HD404339S

16,384

DP-64S

HD404339FS

FP-64B

ZTAT

HD4074339

HD4074339S

16,384

DP64S

HD4074339FS

FP-64B

Recommended PROM Programmers and Socket Adapters

PROM Programmer

Socket Adapter

Manufacture

Model Name

Package

Manufacture

Model Name

DATA I/O corp

121 B

DP-64S

Hitachi

HS4339ESS01H

FP-64B

HS4339ESF01H

AVAL corp

PKW-1000

DP-64S

Hitachi

HS4339ESS01H

FP-64B

HS4339ESF01H

HD404339 Series

Pin Arrangement

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

FP-64B

SCK

/SI

/SO

/TOC

TEST

RESET

OSC

GND

X1
X2

/AN

disp

/AN

INT

/EVNB

/BUZZ

STOPC

SCK

/SI

/SO

/TOC

TEST

RESET

OSC

GND

X1
X2

/AN

STOPC

/BUZZ

/EVNB

INT

disp

DP-64S

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

20
21
22
23
24
25
26
27
28
29
30
31
32

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

64
63
62
61
60
59
58
57
56
55
54
53
52

HD404339 Series

Pin Description

Pin Number

Item

Symbol

DP-64S

FP-64B

I/O

Function

Power supply

Applies power voltage

GND

Connected to ground

disp

(shared
with RA

)

Used as a high-voltage output power supply pin
when selected by the mask option

Test

TEST

Cannot be used in user applications. Connect
this pin to GND.

Reset

RESET

Resets the MCU

Oscillator

OSC

Input/output pin for the internal oscillator.
Connect these pins to the ceramic or crystal
oscillator, or OSC

to an external oscillator

circuit.

OSC

Used with a 32.768-kHz crystal oscillator for
clock purposes

Port

3447

2841

I/O

Input/output pins addressed individually by bits;
D

are all high-voltage I/O pins. Each pin

can be individually configured as selected by
the mask option.

One-bit high-voltage input port pin

111,
2031

15,

1425,

5964

I/O

Four-bit input/output pins consisting of standard
voltage pins

4863

4257

I/O

Four-bit input/output pins consisting of high
voltage pins

Interrupt

INT

34, 35

28, 29

Input pins for external interrupts

Stop clear

STOPC

Input pin for transition from stop mode to active
mode

Serial interface

SCK

I/O

Serial interface clock input/output pin

Serial interface receive data input pin

Serial interface transmit data output pin

Timer

TOC

Timer output pin

EVNB

Event count input pin

Alarm

BUZZ

Square waveform output pin

HD404339 Series

Pin Description in PROM Mode

The HD4074339 is a PROM version of a ZTAT

microcomputer. In PROM mode, the MCU stops

operating, thus allowing the user to program the on-chip PROM.

Pin Number

MCU Mode

PROM Mode

DP-64S

FP-64B

Pin

I/O

Pin

I/O

I/O

SCK

I/O

/SI

I/O

/SO

I/O

/TOC

I/O

TEST

RESET

OSC

GND

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

HD404339 Series

Pin Number

MCU Mode

PROM Mode

DP-64S

FP-64B

Pin

I/O

Pin

I/O

/AN

I/O

INT

I/O

INT

I/O

/EVNB

I/O

/BUZZ

I/O

STOPC

I/O

disp

Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin

2. O

to O

consist of two pins each. Tie each pair together before using them.

HD404339 Series

Block Diagram

D port

R0 port

R1 port

R2 port

R3 port

R4 port

R5 port

R6 port

R7 port

R8 port

R9 port

RA port

ROM

(16,384

10 bits)

(12,288

10 bits)

(8,192

10 bits)

(14 bits)

Instruction

decoder

(10 bits)

(4 bits)

(1 bit)

ALU

SPY

(4 bits)

SPX

(4 bits)

RAM

(512

4 bits)

System control

Interrupt

control

Timer A

Timer B

Timer C

Serial

interface

A/D

converter

Buzzer

Internal data bus

Internal address bus

BUZZ

·
·
·

SCK

TOC

EVNB

INT

Data bus

High voltage

Directional

signal line

GND

OSC

STOPC

TEST

RESET

(6,144

10 bits)

(4,096

10 bits)

HD404339 Series

Memory Map

ROM Memory Map

Vector Address Area ($0000$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines.

Zero-Page Subroutine Area ($0000$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000-$0FFF (HD404334), $0000-$17FF (HD404336), $0000$1FFF (HD404338),
$0000$2FFF (HD4043312), $0000$3FFF (HD404339, HD4074339)): The entire ROM area can be
used for program coding.

$000F

$0FFF

$1000

$2FFF

$0010

$003F

$0040

Vector address

(16 words)

Zero-page subroutine

(64 words)

Pattern (4,096 words)

HD404334

Program (4,096 words)

HD404338

Program

(8,192 words)

$0000

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007

$0008
$0009

$000A
$000B

$000C
$000D

$000E

$000F

JMPL instruction

(jump to

RESET

STOPC

routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to timer B routine)

JMPL instruction

(jump to timer C routine)

JMPL instruction

(jump to A/D converter routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to serial routine)

HD4043312

Program

(12,288 words)

HD404339, HD4074339

Program

(16,384 words)

$1FFF

$2000

$3000

$3FFF

HD404336

Program

(6,144 words)

$17FF

$1800

Note:

Since the ROM address areas between $0000$0FFF overlap, the user can determine how these
areas are to be used.

Figure 1 ROM Memory Map

HD404339 Series

RAM Memory Map

A/D channel register (ACR)

$000

$040

$050

$003

$004

$005

$006

$007

$008
$009

$00A
$00B

$00C

$00D

$00E

$00F

$020
$023

$033

$034
$035
$036
$037

$00A

$00B

$00E

$00F

R/W

W
W

R/W

R/W
R/W

$3C0

RAM-mapped registers

Memory registers (MR)

Stack (64 digits)

Interrupt control bits area

Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B1 (TMB1)

Timer B (TRBL/TWBL)
(TRBU/TWBU)

Miscellaneous register (MIS)

Timer mode register C (TMC)
Timer C (TRCL/TWCL)
(TRCU/TWCU)

Port R0 DCR (DCR0)

Port R3 DCR (DCR3)

Not used

1. Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).

2. Undefined.

Timer read register B lower (TRBL)

Timer read register B upper (TRBU)

Timer read register C lower (TRCL)

Timer read register C upper (TRCU)

Timer write register B lower (TWBL)

Timer write register B upper (TWBU)

Timer write register C lower (TWCL)

Timer write register C upper (TWCU)

R: Read only
W: Write only
R/W: Read/write

$200

Notes:

$016

A/D data register lower (ADRL)

$017

$024
$025
$026
$027
$028

$018

$019

$01A

$3FF

A/D data register upper (ADRU)
A/D mode register 1 (AMR1)
A/D mode register 2 (AMR2)

W
W

Port mode register B (PMRB)
Port mode register C (PMRC)

Timer mode register B2 (TMB2)

System clock selection register 1 (SSR1)

Not used

Port R4 DCR (DCR4)
Port R5 DCR (DCR5)
Port R6 DCR (DCR6)
Port R7 DCR (DCR7)

W
W
W
W

W
W

W
W
W

$030

Data (432 digits)

Not used

System clock selection register 2 (SSR2)

Not used

0000

0000
0000

Undefined

0000
0000

/0000

0000

0000
1000
0000

-000

0000

00-0
-000
000-

0000
0000
0000

-000

--00

Undefined

/0000

Undefined

Initial values

after reset

$03F

Figure 2 RAM Memory Map and Initial Values

HD404339 Series

Table 1

Initial Values of Flags after MCU Reset

Item

Initial Value

Interrupt flags/mask

Interrupt enable flag (IE)

Interrupt request flag (IF)

Interrupt mask (IM)

Bit registers

Watchdog timer on flag (WDON)

A/D start flag (ADSF)

Input capture status flag (ICSF)

Input capture error flag (ICEF)

off flag (IAOF)

RAM enable flag (RAME)

Low speed on flag (LSON)

Direct transfer on flag (DTON)

Bit 3

Bit 2

Bit 1

Bit 0

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT

)

IF1

(IF of

INT

)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

IMS

(IM of serial)

IFS

(IF of serial)

IMAD

(IM of A/D)

IFAD

(IF of A/D)

$0000

$0001

$0002

$0003

IM0

(IM of

INT

)

IF0

(IF of

INT

)

RSP

(Reset SP bit)

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

$020

$021

$022

$023

DTON

(Direct transfer

on flag)

ADSF

(A/D start flag)

WDON

(Watchdog

on flag)

LSON

(Low speed

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag)

IF: Interrupt

request flag

IM: Interrupt

mask

IE: Interrupt

enable flag

SP: Stack pointer

Bit 3

Bit 2

Bit 1

Bit 0

RAM Address

IAOF

off flag)

Not used

Interrupt control bits area

Register flag area

Figure 3 Interrupt Control Bits and Register Flag Areas Configuration

HD404339 Series

LSON

IAOF

ICSF

ICEF

RAME

RSP

WDON

ADSF

DTON

Not used

SEM/SEMD

Not executed

Allowed

REM/REMD

TM/TMD

Allowed

Not executed

Allowed

Not executed in active mode

Used in subactive mode

Not executed

Allowed

Not executed

Inhibited

Allowed

Not executed

Inhibited

Allowed

Inhibited

Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.

The REM or REMD instruction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode. If the TM or TMD instruction is executed for
the inhibited bits or non-existing bits, the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

Memory registers

$040

$041
$042
$043
$044
$045
$046
$047
$048
$049

$04A
$04B

$04C
$04D

$04E
$04F

$3C0

$3FF

MR(0)
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)

Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1

MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)

Bit 3

Bit 2

Bit 1

Bit 0

PC PC :
ST: Status flag
CA: Carry flag

Program counter

Stack area

$3FC

$3FD

$3FE

$3FF

Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position

HD404339 Series

Addressing Modes

RAM Addressing Modes

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as
a RAM address.

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located
in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.

Opcode

Register Indirect Addressing

2nd instruction

word

RAM address

Direct Addressing

Instruction

RAM address

1st instruction

word

Memory Register Addressing

RAM address 0 0 0 1 0 0

Opcode

Instruction

0 3

Figure 7 RAM Addressing Modes

HD404339 Series

ROM Addressing Modes

Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the
JMPL, BRL, or CALL instruction.

Current Page Addressing Mode: A program can branch to any address in the current page (256 words
per page) by executing the BR instruction.

Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page
subroutine area ($0000$003F) by executing the CAL instruction.

Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.

Direct Addressing

2nd

instruction word

Program counter

Current Page Addressing

Program counter

1st

instruction word

Zero-Page Addressing

0 0

Operand

Table Data Addressing

Operand

Opcode

Operand

* * * * * *

Opcode

Program counter

Operand

Opcode

0 0 0 0 0 0 0 0

Program counter

Figure 8 ROM Addressing Modes

HD404339 Series

Instruction Set

Table 2

Instruction Set Classification

Instruction Type

Function

Number of
Instructions

Immediate

Transferring constants to the accumulator, B register, and RAM.

Transferring contents of the B, Y, SPX, SPY, or memory registers to
the accumulator.

RAM addressing

Available when accessing RAM in register indirect addressing
mode.

RAM register

Transferring data between the accumulator and memory.

Arithmetic

Performing arithmetic operations with the contents of the
accumulator, B register, or memory.

Compare

Comparing contents of the accumulator or memory with a constant.

RAM bit manipulation

Bit set, bit reset, and bit test.

ROM addressing

Branching and jump instructions based on the status condition.

Input/output

Controlling the input/output of the R and D ports; ROM data
reference with the P instruction.

Control

Controlling the serial communication interface and low-power
dissipation modes.

Total: 101
instructions

HD404339 Series

Operating Modes

The MCU has five operating modes as shown in table 3. Transitions between operating modes are shown
in figure 11.

Table 3

Operations in Each Operating Mode

Function

Active Mode

Subactive
Mode

Standby Mode

Watch Mode

Stop Mode

System oscillator

Stopped

Subsystem oscillator OP

CPU

Retained

Reset

RAM

Retained

Timer A

Reset

Timers B, C

Stopped

Reset

Serial

Stopped

Reset

A/D

Stopped

Reset

I/O

Retained

Reset

Notes: OP

implies in operation.

Oscillation can be switched on or off with bit 3 of system clock selection register 1 (SSR1: $027).

HD404339 Series

Reset by

RESET

input or

by watchdog timer

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Stop
Oscillate
f

SUB

OSC

CPU

CLK

PER

Stop
Stop
Stop
Stop
Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

Standby mode

Stop mode

(TMA3 = 0, SSR13 = 1)

Watch mode

Subactive
mode

(TMA3 = 1)

(TMA3 = 1, LSON = 0)

(TMA3 = 1, LSON = 1)

SBY

instruction

Interrupt

SBY

instruction

Interrupt

STOP

instruction

INT

timer A

OSC

cyc

SUB

LSON:
DTON:

Main oscillation frequency
Subsystem oscillation
frequency for time base
f

OSC

/4, f

OSC

/8, f

OSC

/16,

or f

OSC

/32

(software selectable)
f

/8 or f

(software selectable)
f

System clock
Clock for timer A
Clock for other peripheral
functions (except timer A)
Low speed on flag
Direct transfer on flag

Active
mode

CPU

CLK

PER

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
Stop
Stop

(TMA3 = 0, SSR13 = 0)

RESET 1

RESET 2

RAME = 0

RAME = 1

INT

timer A

(TMA3 = 0)

STOP
instruction

STOPC

STOP

instruction

1. STOP/SBY (DTON = 1, LSON = 0)
2. STOP/SBY (DTON = 0, LSON = 0)
3. STOP/SBY (DTON = Don't care, LSON = 1)

Notes:

STOP

instruction

Figure 11 MCU Status Transitions

HD404339 Series

In stop mode, the system oscillator is stopped. To ensure a proper oscillation stabilization period of at least
t

when clearing stop mode, execute the cancellation according to the timing chart in figure 12.

In watch and subactive modes, a timer A or

INT

interrupt can be accepted during the interrupt frame

period T (see figure 13).

Note:

In watch and subactive modes, an interrupt will not be properly detected if the

INT

high or low

level period is shorter than the interrupt frame period T. Thus, when operating in watch and
subactive modes, maintain the

INT

high or low level period longer than period T to ensure

interrupt detection.

Stop mode

Oscillator

Internal

clock

STOP instruction execution

res

(stabilization period)

res

RESET

STOPC

Figure 12 Timing of Stop Mode Cancellation

Active mode

Interrupt strobe

Watch mode

Oscillation

stabilization

period

Active mode

T:
t :

Interrupt frame length
Oscillation stabilization period

INT

Interrupt request
generation

(During the transition
from watch mode to
active mode only)

T + t

2T + t

Figure 13 Interrupt Frame

HD404339 Series

The MCU automatically provides an oscillation stabilization period t

when operation switches from

watch mode to active mode. The interrupt frame period T and one of three values for t

can be selected

with the miscellaneous register (MIS: $00C), as listed in figure 14.

Operation can switch directly from subactive mode to active mode, as illustrated in figure 15. In this case,
the transition time T

obeys the following relationship.

< T

< T + t

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

Miscellaneous register (MIS: $00C)

MIS1

MIS0

0.24414 ms

0.12207 ms

0.24414 ms

7.8125 ms

62.5 ms

Oscillation Circuit Conditions

External clock input

Ceramic oscillator

15.625 ms

125 ms

Not used

Notes: 1.

The values of T and t

are applied when a 32.768-kHz crystal oscillator is used.

The value is applied only when direct transfer operation is used.

Buffer control.

Refer to figure 24.

MIS3

MIS2

Crystal oscillator

Figure 14 Miscellaneous Register

HD404339 Series

Subactive mode

Interrupt strobe

Direct transfer
completion timing

MCU internal

processing period

Oscillation

stabilization

time

Active mode

T:
t :

STOP/SBY instruction execution

(Set LSON = 0, DTON = 1)

Interrupt frame period
Oscillation stabilization time

Figure 15 Direct Transition Timing

MCU Operation Sequence: The MCU operation flow is shown in figures 16 and 17.

RESET input is

asynchronous, and causes an immediate transition to the reset state from any MPU operation state.

The low-power mode operation sequence is shown in figure 17. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.

HD404339 Series

Oscillator Circuit

Figure 18 shows a block diagram of the clock generation circuit. The system clock frequency of the
oscillator connected to OSC

and OSC

can be selected by system clock selection registers 1 and 2 (SSR1,

2: $027, $028) as shown in figures 20 and 21.

The system clock division ratio can be set by software to be 1/4, 1/8, 1/16, or 1/32. The subsystem clock
division ratio can be set by software to be 1/4 or 1/8.

OSC

System

oscillator

Sub-

system

oscillator

1/4, 1/8,

1/16, or

1/32

division

circuit

Timing

generator

circuit

System

clock

selection

CPU with ROM,

RAM, registers,

flags, and I/O

Peripheral

function

interrupt

Time-base

interrupt

Time-base

clock

selection

1/8 or 1/4

division

circuit

Timing

generator

circuit

Timing

generator

circuit

1/8

division

circuit

SUB

subcyc

LSON

TMA3

cyc

OSC

Wcyc

CPU

PER

CLK

Notes: 1.

The system clock division ratio can be selected by setting bit 1 or 0 of the system
clock select register 2 (SSR2: $028).

The system clock division ratio can be selected by setting bit 2 of the system
clock select register 1 (SSR1: $027).

Figure 18 Clock Generation Circuit

HD404339 Series

Table 4

Oscillator Circuit Examples

Circuit Configuration

Circuit Constants

External clock
operation

External
oscillator

OSC

Open

OSC

Ceramic oscillator
(OSC

, OSC

)

OSC

Ceramic

GND

Ceramic oscillator: CSA4.00MG

(Murata)

= 1 M

20%

= C

= 30 pF

20%

Crystal oscillator
(OSC

, OSC

)

OSC

Crystal

GND

OSC

= 1 M

20%

= C

= 10 to 22 pF

20%

Crystal: Equivalent to circuit shown below
C

= 7 pF max.

= 100

max.

Crystal oscillator
(X1, X2)

Crystal

GND

Crystal: 32.768 kHz: MX38T (Nippon
Denpa)

= C

= 20 pF

20%

= 14 k

= 1.5 pF

Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray

capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.

2. Wiring among OSC

, OSC

, X1, X2 and elements should be as short as possible, and must not

cross other wiring (see figure 19).

3. When a 32.768-kHz crystal oscillator is not used, fix pin X1 to GND and leave pin X2 open.

HD404339 Series

Bit

Initial value

Read/Write

Bit name

SSR13

SSR12

Not used

SSR11

System clock selection register 1 (SSR1: $027)

System Clock Selection

0.4 to 1.0 MHz

1.6 to 4.5 MHz

SSR11

SSR12

Ratio Selection

SUB

= f

SUB

= f

32-kHz Oscillation Division

SSR13

32-kHz Oscillation Stop

Oscillation operates in stop mode

Oscillation stops in stop mode

Notes:

SSR13 will only be cleared to 0 by a

RESET

input. A

STOPC

input during stop mode will not

clear SSR13. Also note that SSR13 will not be cleared upon transition to stop mode.

When the subsystem oscillator (32.768 kHz crystal oscillator) is used, set 0.4 MHz

OSC

1.0MHz

or 1.6 MHz

OSC

4.5 MHz.

Figure 20 System Clock Selection Register 1 (SSR1)

Bit

Initial value

Read/Write

Bit name

Not used

SSR20

SSR21

System clock selection register 2 (SSR2: $028)

SSR21

SSR20

System Clock Division Ratio

1/4 division

1/8 division

1/16 division

1/32 division

Figure 21 System Clock Selection Register 2 (SSR2)

HD404339 Series

I/O Ports

The MCU has 53 input/output pins (D

, R0

) and one input-only pin (RA

The 30 pins consisting of ports D

, R1, R2, R8, and R9 are all high-voltage I/O pins. RA

is a high-

voltage input-only pin. The high-voltage pins can be equipped with or without pull-down resistance, as
selected by the mask option.

All standard voltage output pins are CMOS output pins. However, the R0

/SO pin can be programmed

for NMOS open-drain output.

In stop mode, input/output pins go to the high-impedance state.

All standard voltage input/output pins have pull-up MOS built in, which can be individually turned on
or off by software (Table 5).

Pull-up MOS on/off settings can be made independently of settings as on-chip supporting module pins.

Table 5

Control of Standard I/O Pins by Program

MIS3 (bit 3 of MIS)

DCR

PDR

CMOS buffer

PMOS

NMOS

Pull-up MOS

Note:

-- indicates off.

HD404339 Series

Table 6

Circuit Configurations of Standard I/O Pins

I/O Pin Type

Circuit

Pins

Input/output pins

Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

PDR

Input control signal

DCR

, R0

Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

DCR

PDR

Input control signal

MIS2

Peripheral function
pins

Input/
output
pins

Pull-up control signal

Output data

Input data

HLT

MIS3

SCK

Output
pins

Pull-up control signal

PMOS control

signal

Output data

HLT

MIS3

MIS2

Pull-up control signal

Output data

HLT

MIS3

TOC

HD404339 Series

I/O Pin Type

Circuit

Pins

Peripheral function
pins

Input/
pins

Input data

HLT

MIS3

PDR

Input control

HLT

MIS3

PDR

A/D input

Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The

HLT

signal goes low, and input/output pins enter the high-impedance state.

2. The

HLT

signal is 1 in active, standby, watch, and subactive modes.

Table 7

Circuit Configurations for High-Voltage Input/Output Pins

I/O Pin Type

With Pull-Down Resistance

Without Pull-Down Resistance

Pins

Input/output
pins

Input data

Input control
signal

HLT

Output
data

disp

Pull-down
resistance

Input data

Input control

signal

Output
data

HLT

Input pins

Input data

Input control

signal

Peripheral
function
pins

Output pins

Output
data

disp

Pull-down
resistance

HLT

Output
data

HLT

BUZZ

Input pins

Input data

Pull-down
resistance

disp

Input data

INT

EVNB,

STOPC

Note:

HLT

goes high in active, standby, watch, and subactive modes.

HD404339 Series

Bit

Initial value

Read/Write

Bit name

PMRA3

PMRA2

PMRA0

PMRA1

PMRA0

/SO Mode Selection

Port mode register A (PMRA: $004)

PMRA1

/SI Mode Selection

PMRA2

/TOC Mode Selection

TOC

PMRA3

/BUZZ Mode Selection

BUZZ

Figure 23 Port Mode Register A (PMRA)

Bit

Initial value

Read/Write

Bit name

PMRB3

PMRB2

PMRB0

PMRB1

PMRB0

INT

Mode Selection

INT

Port mode register B (PMRB: $024)

PMRB1

INT

Mode Selection

INT

PMRB2

/EVNB Mode Selection

EVNB

PMRB3

STOPC

Mode Selection

STOPC

Note:

PMRB3 is reset to 0 only by

RESET

input. When

STOPC

is input in stop mode, PMRB3 is not

reset but retains its value.

Figure 24 Port Mode Register B (PMRB)

HD404339 Series

Timers

The MCU has three built-in timers A, B, and C. The functions of each timer are listed in table 7.

Timer A

Timer A is an 8-bit free-running timer that can also be used as a clock time-base with a 32.768-kHz
subsystem oscillator. Timer A has the following features:

One of eight internal clocks can be selected from prescaler S according to the setting of timer mode
register A (TMA: $008)

In time-base mode, one of five internal clocks can be selected from prescaler W according to the setting
of timer mode register A

An interrupt request can be generated when timer counter A (TCA) overflows

Input clock frequency must not be modified during timer A operation

Table 7

Timer Functions

Functions

Timer A

Timer B

Timer C

Clock source

Prescaler S

Available

Prescaler W

Available

External event

Available

Timer functions

Free-running

Available

Time base

Available

Event counter

Available

Reload

Available

Watchdog

Available

Input capture

Available

Timer output

PWM

Available

HD404339 Series

Bit

Initial value

Read/Write

Bit name

TMA3

TMA2

TMA0

TMA1

Timer mode register A (TMA: $008)

PSS

PSW

Operating Mode

Timer A mode

TMA3

TMA1

TMA2

TMA0

Source
Prescaler

2048 t

cyc

1024 t

cyc

512 t

cyc

128 t

cyc

32 t

cyc

8 t

cyc

4 t

cyc

2 t

cyc

Input Clock
Frequency

32t

16t

1/2t

Time-base
mode

Not used

PSW and TCA reset

Notes:

Wcyc

X = Don't care.

1.
2.
3.

t = 244.14

s (when a 32.768-kHz crystal oscillator is used)

Timer counter overflow output period (seconds) = input clock period (seconds) 256.
The division ratio must not be modified during time-base mode operation,
otherwise an overflow cycle error will occur.

Wcyc

Figure 28 Timer Mode Register A (TMA)

HD404339 Series

Timer B

Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features.
These are described as follows.

By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler
S can be selected, or timer B can be used as an external event counter

By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected.

By setting timer write register BL, U (TWBL, U: $00A, $00B), timer counter B (TCB) can be written
to during reload timer operation

By setting timer read register BL, U (TRBL, U: $00A, $00B), the contents of timer counter B can be
read out

Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as
an external event

An interrupt can be requested when timer counter B overflows or when a trigger input edge is received
during input capture operation

HD404339 Series

Bit

Initial value

Read/Write

Bit name

TMB13

TMB12

TMB10

TMB11

Timer mode register B1 (TMB1: $009)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMB12

TMB10

TMB11

Input Clock Period and Input
Clock Source

/EVNB (External event input)

TMB13

Free-Running/Reload
Timer Selection

Free-running timer

Reload timer

Figure 31 Timer Mode Register B1 (TMB1)

Bit

Initial value

Read/Write

Bit name

Not used

TMB22

TMB20

TMB21

Timer mode register B2 (TMB2: $026)

TMB21

TMB20

EVNB Edge Detection Selection

No detection

Falling edge detection

Rising edge detection

Rising and falling edge detection

TMB22

Free-Running/Reload and Input Capture Selection

Free-Running/Reload

Input Capture

Figure 32 Timer Mode Register B2 (TMB2)

HD404339 Series

Timer C

Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features,
which are described as follows.

By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S
can be selected

By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output
(PWM output) is enabled

By setting timer write register CL, U (TWCL, U: $00E, $00F), timer counter C (TCC) can be written to

By setting timer read register CL, U (TRCL, U: $00E, $00F), the contents of timer counter C can be
read out

An interrupt can be requested when timer counter C overflows

Timer counter C can be used as a watchdog timer for detecting runaway programs

HD404339 Series

Notes on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 8. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

Table 8

PWM Output Following Update of Timer Write Register

PWM Output

Mode

Timer Write Register is Updated during
High PWM Output

Timer Write Register is Updated during
Low PWM Output

Free running

Timer write
register
updated to
value N

Interrupt
request

(255 N) T

(N + 1)

Timer write
register
updated to
value N

Interrupt
request

(N' + 1)

(255 N)

(N + 1)

Reload

Timer write
register
updated to
value N

Interrupt
request

(255 N)

Timer write
register
updated to
value N

Interrupt
request

(255 N)

HD404339 Series

Serial Interface

The MCU has a one-channel serial interface built in with the following features.

One of 13 different internal clocks or an external clock can be selected as the transmit clock. The
internal clocks include the six prescaler outputs divided by two and by four, and the system clock.

During idle status, the serial output pin can be controlled to be high or low output

Transmit clock errors can be detected

An interrupt request can be generated after transfer has completed when an error occurs

Internal data bus

Port mode

(PMRC)

SCK

Selector

System

clock

PER

Prescaler S (PSS)

Idle

controller

Serial mode

(SMR)

Clock

Serial data

Serial interrupt

request flag

(IFS)

Selector

1/2

Octal

counter (OC)

I/O

controller

Transfer
control
signal

128

512

2048

Figure 38 Serial Interface Block Diagram

HD404339 Series

Table 10

Serial Interface Operating Modes

SMR

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Continuous clock output mode

Transmit mode

Receive mode

Transmit/receive mode

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

MCU reset

SMR write

STS instruction

Transmit clock

8 transmit clocks or STS instruction (IFS 1)

SMR write (IFS 1)

External clock mode

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

SMR write

STS instruction

Transmit clock

STS instruction (IFS 1)

8 transmit clocks or

Internal clock mode

Continuous clock output state

(PMRA 0, 1 = 00)

SMR write

Transmit clock

MCU reset

SMR write (IFS 1)

Figure 39 Serial Interface State Transitions

HD404339 Series

State

MCU reset

PMRA write

SMR write

PMRC write

SCK

STS wait state

Transmit clock
wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

External clock selection

Output level control in

idle states

Dummy write for
state transition

Output level control in

idle states

Data write for transmission

Undefined

LSB

MSB

Flag reset at transfer completion

External clock mode

State

MCU reset

PMRA write

SMR write

PMRC write

STS wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

Internal clock selection

Output level control in

idle states

Data write for transmission

Output level control in

idle states

Undefined

LSB

MSB

Flag reset at transfer completion

Internal clock mode

(input)

instruction

write

SRL, SRU

STS

SO pin

IFS

SCK

(output)

instruction

write

SRL, SRU

STS

SO pin

IFS

Figure 41 Example of Serial Interface Operation Sequence

HD404339 Series

Table 11

Transmit Clock Selection

PMRC

SMR

Bit 0

Bit 2

Bit 1

Bit 0

System Clock Divisor

Transmit Clock Frequency

2048

4096t

cyc

512

1024t

cyc

128

256t

cyc

64t

cyc

16t

cyc

4096

8192t

cyc

1024

2048t

cyc

256

512t

cyc

128t

cyc

32t

cyc

Bit

Initial value

Read/Write

Bit name

SMR3

SMR2

SMR0

SMR1

Serial mode register (SMR: $005)

SMR2

SMR0

SMR1

SMR3

SCK

Mode Selection

SCK

Output

Input

Clock Source

External clock

Prescaler
Division Ratio

Refer to
table 11

Prescaler

System clock

Figure 43 Serial Mode Register (SMR)

HD404339 Series

A/D Converter

The MCU also contains a built-in A/D converter that uses a sequential comparison method with a
resistance ladder. It can perform digital conversion of twelve analog inputs with 8-bit resolution. The
following describes the A/D converter.

A/D mode register 1 (AMR1: $019) is used to select digital or analog ports

A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or
analog ports

The A/D channel register (ACR: $016) is used to select an analog input channel

A/D conversion is started by setting the A/D start flag (ADSF: $020, 2) to 1. After the conversion is
completed, converted data is stored in the A/D data register, and at the same time the A/D start flag is
cleared to 0.

By setting the I

off flag (IAOF: $021, 2) to 1, the current flowing through the resistance ladder can be

cut off even while operating in standby or active mode

The A/D data register is a read-only register consisting of a lower 4 bits and upper 4 bits (ADRL: $017,
ADRU: $018). This register is not cleared by a reset. Data reads during A/D conversion are not
guaranteed. After A/D conversion ends, the resultant 8-bit data is set in this register and held until the
start of the next conversion (figures 51 to 53).

HD404339 Series

Notes on Usage

Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)

Do not write to the A/D start flag during A/D conversion

Data in the A/D data register during A/D conversion is undefined

Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop, watch, or subactive mode. In addition, to save power while in these
modes, all current flowing through the converter's resistance ladder is cut off.

If the power supply for the A/D converter is to be different from V

, connect a 0.1-

F bypass capacitor

between the AV

and AV

pins. (However, this is not necessary when the AV

pin is directly

connected to the V

pin.)

The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to V

. When using a

shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode registr as an analog pin will remain
pulled up.

Bit

Initial value

Read/Write

Bit name

AMR13

AMR12

AMR10

AMR11

AMR10

A/D mode register 1 (AMR1: $019)

AMR11

AMR12

/AN

Mode Selection

AMR13

/AN

Mode Selection

/AN

Mode Selection

/AN

Mode Selection

Figure 46 A/D Mode Register 1 (AMR1)

HD404339 Series

Bit

Initial value

Read/Write

Bit name

R/W

DTON

R/W

ADSF

R/W

LSON

WDON

A/D start flag (ADSF: $020, bit 2)

Refer to the description of operating
modes

DTON

Refer to the description of timers

WDON

Refer to the description of operating
modes

LSON

A/D conversion completed

A/D conversion started

A/D Start Flag (ADSF)

Figure 49 A/D Start Flag (ADSF)

Bit

Initial value

Read/Write

Bit name

R/W

RAME

R/W

IAOF

R/W

ICSF

R/W

ICEF

off flag (IAOF: $021, bit 2)

Refer to the description of operating
modes

RAME

Refer to the description of timers

ICEF

Refer to the description of timers

ICSF

current flows

current is cut off

Off Flag (IAOF)

Figure 50 I

Off Flag (IAOF)

HD404339 Series

AN to

1. When not using an A/D converter.

GND

2. When using pins AN and AN but not using AN to AN .

3. When using all analog pins.

0.1

F 3

0.1

F 13

0.1

Figure 54 Example of Connections (AV

to AV

)

Between the V

and GND lines, connect capacitors designed for use in ordinary power supply circuits.

An example connection is described in figure 54.

No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in
parallel. The capacitors are a large capacitance C

and a small capacitance C

HD404339 Series

Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to V

+ 0.3

45 to V

+ 0.3

Total permissible input current

Total permissible output current

150

Maximum input current

6, 7

6, 8

Maximum output current

9, 10

10, 11

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.

1. Applies to pin TEST (V

) of HD4074339.

2. Applies to all standard voltage pins.

3. Applies to high-voltage pins.

4. The total permissible input current is the total of input currents simultaneously flowing in from all

the I/O pins to GND.

5. The total permissible output current is the total of output currents simultaneously flowing out from

to all I/O pins.

6. The maximum input current is the maximum current flowing from each I/O pin to GND.

7. Applies to ports R3, R4, and R5.

8. Applies to ports R0, R6, and R7.

9. Applies to ports R0 and R3 to R7.

10. The maximum output current is the maximum current flowing from V

to each I/O pin.

11. Applies to ports D

, R1, R2, R8, and R9.

HD404339 Series

Electrical Characteristics

DC Characteristics (V

= 4.0 to 5.5 V, GND = 0 V, V

disp

= V

 40 V to V

C C

, T

= 20 to +75

unless otherwise specified)

Item

Symbol Pins

Min

Typ

Max

Unit

Test Condition

Notes

Input high voltage

RESET

SCK

SI,

INT

STOPC

, EVNB

0.8V

+ 0.3

OSC

0.5 --

+ 0.3

Input low voltage

RESET

SCK

0.3

0.2V

INT

STOPC

, EVNB

40 --

0.2V

OSC

0.3

0.5

Output high
voltage

SCK

, SO, TOC V

0.5 --

= 0.5 mA

Output low voltage V

SCK

, SO, TOC --

0.4

= 0.4 mA

I/O leakage
current

RESET

SCK

SI, SO,TOC,
OSC

= 0 V to V

INT

STOPC

, EVNB

= V

40 to

Current dissipation
in active mode

5.0

= 5 V,

OSC

= 4 MHz

2, 5

8.0

2, 6

Current dissipation
in standby mode

SBY

2.0

= 5 V,

OSC

= 4 MHz

Current dissipation
in subactive mode

SUB

100

= 5 V,

32 kHz oscillator

4, 5

320

4, 6

Current dissipation
in watch mode

WTC

= 5 V,

32 kHz oscillator

Current dissipation
in stop mode

STOP

X1 = GND,

X2 = Open

4, 5

4, 6

Stop mode
retaining voltage

STOP

HD404339 Series

Notes: 1. Excludes current flowing through pull-up MOS and output buffers.

2. I

is the source current when no I/O current is flowing while the MCU is in reset state.

Test conditions:

MCU:

Reset

Pins:

RESET

, TEST at GND

R0, R3

to R7

at V

, R1, R2, R8, R9, RA

at V

disp

3. I

SBY

is the source current when no I/O current is flowing while the MCU timer is operating.

Test conditions:

MCU:

I/O reset

Standby mode

Pins:

RESET

at V

TEST at GND

R0, R3

to R7

at V

, R1, R2, R8, R9, RA

at V

disp

4. This is the source current when no I/O current is flowing.

Test conditions: Pins: R0, R3

to R7

at V

, R1, R2, R8, R9, RA

at GND

5. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339.

6. Applies to the HD4074339.

HD404339 Series

I/O Characteristics for High-Voltage Pins (V

= 4.0 to 5.5 V, GND = 0 V, V

disp

= V

 40 V to V

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pins

Min

Typ Max

Unit Test Condition

Note

Input high voltage

, R1,

R2, R8, R9,

0.7V

+ 0.3 V

Input low voltage

, R1,

R2, R8, R9,

0.3V

Output high
voltage

, R1,

R2, R8, R9,

BUZZ

3.0 --

= 15 mA

2.0 --

= 10 mA

1.0 --

= 4 mA

Output low voltage V

, R1,

R2, R8, R9,

BUZZ

disp

= V

40 V

150 k

at V

40 V

I/O leakage
current

, R1,

R2, R8, R9,

, BUZZ

= V

40 V to V

Pull-down MOS
current

, R1,

R2, R8, R9

200

600 1000

disp

= V

35 V,

= V

Notes: 1. Applies to pins with pull-down MOS as selected by the mask option .

2. Applies to pins without pull-down MOS as selected by the mask option.

3. Excludes output buffer current.

HD404339 Series

A/D Converter Characteristics (V

= 4.0 to 5.5 V, GND = 0 V, V

disp

= V

 40 V to V

, T

= 20 to

+75

C, unless otherwise specified)

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Note

Analog supply
voltage

0.3 V

+ 0.3

Analog input
voltage

Current flowing
between AV

and

200

= AV

= 5.0 V

Analog input
capacitance

Resolution

Bit

Number of input
channels

Channel

Absolute accuracy

2.0

LSB

Conversion time

cyc

Input impedance

Note: 1. Connect this to V

if the A/D converter is not used.

HD404339 Series

AC Characteristics (V

= 4.0 to 5.5 V, GND = 0 V, V

disp

= V

 40 V to V

, T

= 20 to +75

Item

Symbol Pins

Min

Typ

Max

Unit

Test Condition

Note

Clock oscillation frequency

OSC

0.4

4.5

MHz

System clock

divided by 4

X1, X2

32.768

kHz

Instruction cycle time

cyc

0.89

subcyc

244.14

32-kHz oscillator,

1/8 system clock
division ratio

122.07

32-kHz oscillator,

1/4 system clock
division ratio

Oscillation stabilization time
(ceramic oscillator)

OSC

7.5

Oscillation stabilization time
(crystal oscillator)

OSC

X1, X2

External clock high width

CPH

OSC

External clock low width

CPL

OSC

External clock rise time

CPr

OSC

External clock fall time

CPf

OSC

INT

, EVNB high

widths

INT

EVNB

cyc

subcyc

INT

, EVNB low widths t

INT

EVNB

cyc

subcyc

RESET

low width

RSTL

RESET

cyc

STOPC

low width

STPL

STOPC

RESET

rise time

RSTr

RESET

STOPC

rise time

STPr

STOPC

Input capacitance

All input
pins except
TEST

f = 1 MHz,

= 0 V

TEST

f = 1 MHz,

= 0 V

180

Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for f

OSC

must be applied.

0.4 MHz

OSC

1.0 MHz or 1.6 MHz

OSC

4.5 MHz

The operating range for f

OSC

can be set with bit 1 of system selection register 1 (SSR1: $027).

2. The oscillation stabilization time is the period required for the oscillator to stabilize in the

following situations:

HD404339 Series

a. After V

reaches 4.0 V at power-on.

b. After

RESET

input goes low when stop mode is cancelled.

c. After

STOPC

input goes low when stop mode is cancelled.

To ensure the oscillation stabilization time at power-on or when stop mode is cancelled,

RESET

STOPC

must be input for at least a duration of t

When using a crystal or ceramic oscillator, consult with the manufacturer to determine what

stabilization time is required, since it will depend on the circuit constants and stray capacitance.

3. Refer to figure 56.

4. Refer to figure 57.

5. Refer to figure 58.

6. Refer to figure 59.

7. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339.

8. Applies to the HD4074339.

Serial Interface Timing Characteristics (V

= 4.0 to 5.5 V, GND = 0 V, V

disp

= V

 40 V to V

, T

20 to +75

C, unless otherwise specified)

During Transmit Clock Output

Item

Symbol Pins

Min

Typ Max Unit Test Condition

Note

Transmit clock cycle time

Scyc

SCK

cyc

Load shown in figure 61

Transmit clock high width

SCKH

SCK

0.4

Scyc

Load shown in figure 61

Transmit clock low width

SCKL

SCK

0.4

Scyc

Load shown in figure 61

Transmit clock rise time

SCKr

SCK

Load shown in figure 61

Transmit clock fall time

SCKf

SCK

Load shown in figure 61

Serial output data delay time

DSO

300

Load shown in figure 61

Serial input data setup time

SSI

100

Serial input data hold time

HSI

200

During Transmit Clock Input

Item

Symbol

Pins

Min

Typ Max Unit Test Condition

Note

Transmit clock cycle time

Scyc

SCK

cyc

Transmit clock high width

SCKH

SCK

0.4

Scyc

Transmit clock low width

SCKL

SCK

0.4

Scyc

Transmit clock rise time

SCKr

SCK

Transmit clock fall time

SCKf

SCK

Serial output data delay time t

DSO

300

Load shown in figure 61

Serial input data setup time

SSI

100

Serial input data hold time

HSI

200

Note:

1. Refer to figure 60.

HD404339 Series

Notes on ROM Out

Please pay attention to the following items regarding ROM out.

On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404334 and
HD404336 as an 8-kword version (HD404338), and to create the same data size for t he HD4043312 as a
16-kword version (HD404339).

The 8-kword and 16-kword data sizes are required to change ROM data to mask manufacturing data since
the program used is for an 8-k or 16-kword version.

This limitation applies when using an EPROM or a data base.

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(4,096 words)

Not used

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(6,144 words)

Not used

ROM 4-kword version:
HD404334
Address $1000$1FFF

ROM 6-kword version:
HD404336
Address $1800$1FFF

$0000

$000F
$0010

$003F
$0040

$0FFF
$1000

$1FFF

$0000

$000F
$0010

$003F
$0040

$17FF
$1800

$1FFF

Fill this area with 1s

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(12,288 words)

Not used

ROM 12-kword version:
HD4043312
Address $3000$3FFF

$0000

$000F
$0010

$003F
$0040

$2FFF
$3000

$3FFF

HD404339 Series

HD404334/HD404336/HD404338/HD4043312/HD404339 Option List

5. ROM Code Media

EPROM:

Ceramic oscillator

Crystal oscillator

External clock

f = MHz

6. System Oscillator (OSC1, OSC2)

RA1 without pull-down resistance

Vdisp

4. RA1/Vdisp

Note: If even only one pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp.

With 32-kHz CPU operation, with time base for clock

Without 32-kHz CPU operation, with time base for clock

Without 32-kHz CPU operation, without time base

2. Optional Functions

3. I/O Options

Note:

Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).

The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).

EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are

programmed to different EPROMS.

FP-64B

DP-64S

8. Package

Please specify the first type below (the upper bits and lower bits are mixed together), when using the
EPROM on-package microcomputer type (including ZTATTM version).

Used

Not used

7. Stop Mode

Date of order

Customer

Department

Name

ROM code name

LSI number

HD404334

HD404336

HD404338

HD4043312

HD404339

1. ROM Size

4-kword

6-kword

8-kword

12-kword

16-kword

D0/

INT

D1/

INT

D2/EVNB
D3/BUZZ
D4/

STOPC

D5
D6
D7
D8
D9
D10
D11
D12
D13

Pin name

I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O option

D: Without pull-down resistance

R10
R11
R12
R13
R20
R21
R22
R23
R80
R81
R82
R83
R90
R91
R92
R93

Pin name

I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O option

E: With pull-down resistance

Please check off the appropriate applications and enter
the necessary information.

HD404339 Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533

URL

NorthAmerica

: http:semiconductor.hitachi.com/

Europe

: http://www.hitachi-eu.com/hel/ecg

Asia (Singapore)

: http://www.has.hitachi.com.sg/grp3/sicd/index.htm

Asia (Taiwan)

: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm

Asia (HongKong)

: http://www.hitachi.com.hk/eng/bo/grp3/index.htm

Japan

: http://www.hitachi.co.jp/Sicd/indx.htm

Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180

Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX

Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322

Hitachi Europe GmbH
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00

Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223

For further information write to:

Document Outline

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Document Outline

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