HD49323AF-01
CDS/AGC & 10-bit A/D Converter
ADE-207-262A (Z)
2nd Edition
Apr. 1999
Description
The HD49323AF-01 is a CMOS IC that provides CCD-AGC analog processing (CDS/AGC) suitable for
CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip.
Functions
Correlated Double Sampling
AGC
Sample hold
Offset compensation
Serial interface control
10-bit ADC
3 V single operation (2.7 V to 3.6 V)
Power dissipation: 198 mW (Typ)
Maximum frequency: 20 MHz (Min)
Features
Good suppression of CCD output low-frequency noise is achieved through the use of S/H type
correlated double sampling.
A high S/N ratio is achieved through the use of a AGC type amplifier, and high sensitivity is provided
by a wide cover range.
An auto offset circuit provides compensation of output DC offset voltage fluctuations due to variations
in AGC amplifier gain.
AGC, standby mode, offset control, etc., is possible via a serial interface.
High precision is provided by a 10-bit-resolution A/D converter.
Version of Hitachi's previous-generation HD49322BF with improved functions and performance,
including in particular an approximately 3.0 dB improvement in S/N.
HD49323AF-01
2
Pin Arrangement
NC
BIAS
VRT
VRM
VRB
AV
DD
AV
SS
TESTC
TESTY
CDSIN
AV
DD
AV
SS
PBLK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
NC
36 35
27
34 33 32 31 30 29 28
26 25
1 2
10
3 4 5 6 7 8 9
11 12
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
(Top view)
VRM2
CLP
NC
AV
DD
AV
SS
SPSIG
SPBLK
OBP
ADCLK
DV
DD
DV
SS
OE
AV
SS
AV
DD
NC
NC
AV
DD
AV
SS
CS
SCK
SDATA
DV
DD
DV
SS
DV
SS
HD49323AF-01
3
Pin Description
Pin No.
Symbol
Description
I/O
Analog(A) or
Digital(D)
1
PBLK
Pre-blanking pin
I
D
2
D0
Digital output (LSB)
O
D
3 to 10
D1 to D8
Digital output
O
D
11
D9
Digital output (MSB)
O
D
12
NC
No connection pin
--
--
13
OE
Digital output enable control pin
I
D
14
DV
SS
Digital ground (0 V)
--
D
15
DV
DD
Digital power supply (3 V)
Connect off-chip in common with AV
DD
.
--
D
16
ADCLK
ADC conversion clock input pin
I
D
17
OBP
Optical black pulse input pin
I
D
18
SPBLK
Black level sampling clock input pin
I
D
19
SPSIG
Signal level sampling clock input pin
I
D
20
AV
SS
Analog ground (0 V)
--
A
21
AV
DD
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
--
A
22
NC
No connection pin
--
--
23
CLP
Clamp voltage pin
Connect a 0.22
F or more capacitor between CLP and AV
SS
.
--
A
24
VRM2
Reference voltage pin (for CCD offset cancel)
--
A
25
AV
SS
Analog ground (0 V)
--
A
26
AV
DD
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
--
A
27
CDSIN
CDS input pin
I
A
28
TESTY
Test input pin-Y
I
A
29
TESTC
Test input pin-C
I
A
30
AV
SS
Analog ground (0 V)
--
A
31
AV
DD
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
--
A
32
VRB
Reference voltage pin 3
Connect a 0.1
F ceramic capacitor between VRB and AV
SS
.
--
A
33
VRM
Reference voltage pin 2
Connect a 0.1
F ceramic capacitor between VRM and AV
SS
.
--
A
34
VRT
Reference voltage pin 1
Connect a 0.1
F ceramic capacitor between VRT and AV
SS
.
--
A
HD49323AF-01
4
Pin Description (cont)
Pin No.
Symbol
Description
I/O
Analog(A) or
Digital(D)
35
BIAS
Internal bias pin
Connect a 24 k
resistor between BIAS and AV
SS
.
--
A
36
NC
No connection pin
--
--
37
AV
SS
Analog ground (0 V)
--
A
38
AV
DD
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
--
A
39, 40
NC
No connection pin
--
--
41
AV
DD
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
--
A
42
AV
SS
Analog ground (0 V)
--
A
43
CS
Serial interface control input pin
I
D
44
SCK
Serial clock input pin
I
D
45
SDATA
Serial data input pin
I
D
46
DV
DD
Digital power supply (3 V)
Connect off-chip in common with AV
DD
.
--
D
47, 48
DV
SS
Digital ground (0 V)
--
D
HD49323AF-01
5
Input/Output Equivalent Circuit
Pin Name
Equivalent Circuit
Digital output
D0 to D9
DIN
DV
DD
STBY
or
OE
Digital
output
Digital input
ADCLK
OBP
SPBLK
SPSIG
CS
SCK
SDATA
PBLK
OE
Digital
input
70k
(Typ)
*1
Analog input
CDSIN
CDSIN
Connected to
VRM internally
Reference voltage input
VRT
VRM
VRB
VRM2
VRT
VRM VRM2
-
+
-
+
VRB
Clamp
CLP
CLP
Connected to
VRM internally
AV
DD
Internal bias
BIAS
BIAS
AV
DD
Note:
1. Applies to
OE
and PBLK.
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