Hitachi Single-Chip Microcomputer
H8/3048 Series
H8/3048
HD64F3048, HD6473048, HD6433048
H8/3047
HD6433047
H8/3045
HD6433045
H8/3044
HD6433044
Hardware Manual
ADE-602-073B
Preface
The H8/3048 Series is a series of high-performance microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller
(DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been
expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to
reduce power consumption in battery-powered applications: individual modules can be placed in
standby, and the frequency of the system clock supplied to the chip can be divided down under
software control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and
address space size.
With these features, the H8/3048 Series can be used to implement compact, high-performance
systems easily.
In addition to its masked-ROM versions, the H8/3048 Series has a ZTATTM*
1
version with user-
programmable on-chip PROM and an F-ZTATTM*
2
version with on-chip flash memory that can be
programmed on-board. These versions enable users to respond quickly and flexibly to changing
application specifications.
This manual describes the H8/3048 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Notes: 1. ZTATTM (Zero Turn-Around-time) is a trademark of Hitachi, Ltd.
2. F-ZTATTM (Flexible ZTAT) is a trademark of Hitachi, Ltd.
Contents
Section 1
Overview
......................................................................................................
1
1.1
Overview.........................................................................................................................
1
1.2
Block Diagram................................................................................................................
5
1.3
Pin Description ...............................................................................................................
6
1.3.1
Pin Arrangement .............................................................................................
6
1.3.2
Pin Assignments in Each Mode ......................................................................
7
1.3.3
Pin Functions .................................................................................................. 10
Section 2
CPU
............................................................................................................... 15
2.1
Overview......................................................................................................................... 15
2.1.1
Features........................................................................................................... 15
2.1.2
Differences from H8/300 CPU ....................................................................... 16
2.2
CPU Operating Modes.................................................................................................... 17
2.3
Address Space................................................................................................................. 18
2.4
Register Configuration.................................................................................................... 19
2.4.1
Overview......................................................................................................... 19
2.4.2
General Registers............................................................................................ 20
2.4.3
Control Registers ............................................................................................ 21
2.4.4
Initial CPU Register Values ............................................................................ 22
2.5
Data Formats................................................................................................................... 23
2.5.1
General Register Data Formats....................................................................... 23
2.5.2
Memory Data Formats .................................................................................... 25
2.6
Instruction Set ................................................................................................................. 26
2.6.1
Instruction Set Overview ................................................................................ 26
2.6.2
Instructions and Addressing Modes................................................................ 27
2.6.3
Tables of Instructions Classified by Function................................................. 28
2.6.4
Basic Instruction Formats ............................................................................... 38
2.6.5
Notes on Use of Bit Manipulation Instructions .............................................. 39
2.7
Addressing Modes and Effective Address Calculation .................................................. 39
2.7.1
Addressing Modes .......................................................................................... 39
2.7.2
Effective Address Calculation ........................................................................ 42
2.8
Processing States ............................................................................................................ 46
2.8.1
Overview......................................................................................................... 46
2.8.2
Program Execution State ................................................................................ 47
2.8.3
Exception-Handling State ............................................................................... 47
2.8.4
Exception-Handling Sequences ...................................................................... 49
2.8.5
Bus-Released State ......................................................................................... 50
2.8.6
Reset State ...................................................................................................... 50
2.8.7
Power-Down State .......................................................................................... 50
2.9
Basic Operational Timing ............................................................................................... 51
2.9.1
Overview......................................................................................................... 51
2.9.2
On-Chip Memory Access Timing................................................................... 51
2.9.3
On-Chip Supporting Module Access Timing ................................................. 53
2.9.4
Access to External Address Space.................................................................. 54
Section 3
MCU Operating Modes
........................................................................... 55
3.1
Overview......................................................................................................................... 55
3.1.1
Operating Mode Selection .............................................................................. 55
3.1.2
Register Configuration.................................................................................... 56
3.2
Mode Control Register (MDCR) .................................................................................... 57
3.3
System Control Register (SYSCR)................................................................................. 58
3.4
Operating Mode Descriptions......................................................................................... 60
3.4.1
Mode 1 ............................................................................................................ 60
3.4.2
Mode 2 ............................................................................................................ 60
3.4.3
Mode 3 ............................................................................................................ 60
3.4.4
Mode 4 ............................................................................................................ 60
3.4.5
Mode 5 ............................................................................................................ 60
3.4.6
Mode 6 ........................................................................................................... 60
3.4.7
Mode 7 ........................................................................................................... 61
3.5
Pin Functions in Each Operating Mode.......................................................................... 61
3.6
Memory Map in Each Operating Mode.......................................................................... 61
Section 4
Exception Handling
.................................................................................. 71
4.1
Overview......................................................................................................................... 71
4.1.1
Exception Handling Types and Priority.......................................................... 71
4.1.2
Exception Handling Operation ....................................................................... 71
4.1.3
Exception Vector Table................................................................................... 72
4.2
Reset ............................................................................................................................... 73
4.2.1
Overview......................................................................................................... 73
4.2.2
Reset Sequence ............................................................................................... 73
4.2.3
Interrupts after Reset....................................................................................... 76
4.3
Interrupts......................................................................................................................... 77
4.4
Trap Instruction............................................................................................................... 78
4.5
Stack Status after Exception Handling ........................................................................... 79
4.6
Notes on Stack Usage ..................................................................................................... 80
Section 5
Interrupt Controller
................................................................................... 81
5.1
Overview......................................................................................................................... 81
5.1.1
Features........................................................................................................... 81
5.1.2
Block Diagram................................................................................................ 82
5.1.3
Pin Configuration............................................................................................ 83
5.1.4
Register Configuration.................................................................................... 83
5.2
Register Descriptions...................................................................................................... 84
5.2.1
System Control Register (SYSCR)................................................................. 84
5.2.2
Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 85
5.2.3
IRQ Status Register (ISR) .............................................................................. 92
5.2.4
IRQ Enable Register (IER) ............................................................................. 93
5.2.5
IRQ Sense Control Register (ISCR) ............................................................... 94
5.3
Interrupt Sources............................................................................................................. 95
5.3.1
External Interrupts .......................................................................................... 95
5.3.2
Internal Interrupts ........................................................................................... 96
5.3.3
Interrupt Vector Table ..................................................................................... 96
5.4
Interrupt Operation ......................................................................................................... 100
5.4.1
Interrupt Handling Process ............................................................................. 100
5.4.2
Interrupt Sequence .......................................................................................... 105
5.4.3
Interrupt Response Time................................................................................. 106
5.5
Usage Notes .................................................................................................................... 107
5.5.1
Contention between Interrupt and Interrupt-Disabling Instruction ................ 107
5.5.2
Instructions that Inhibit Interrupts .................................................................. 108
5.5.3
Interrupts during EEPMOV Instruction Execution......................................... 108
5.5.4
Notes on External Interrup to during Use....................................................... 108
Section 6
Bus Controller
............................................................................................ 111
6.1
Overview......................................................................................................................... 111
6.1.1
Features........................................................................................................... 111
6.1.2
Block Diagram................................................................................................ 112
6.1.3
Input/Output Pins............................................................................................ 113
6.1.4
Register Configuration.................................................................................... 113
6.2
Register Descriptions...................................................................................................... 114
6.2.1
Bus Width Control Register (ABWCR) ......................................................... 114
6.2.2
Access State Control Register (ASTCR) ........................................................ 115
6.2.3
Wait Control Register (WCR)......................................................................... 116
6.2.4
Wait State Controller Enable Register (WCER)............................................. 117
6.2.5
Bus Release Control Register (BRCR)........................................................... 118
6.2.6
Chip Select Control Register (CSCR) ............................................................ 119
6.3
Operation ........................................................................................................................ 121
6.3.1
Area Division.................................................................................................. 121
6.3.2
Chip Select Signals ......................................................................................... 123
6.3.3
Data Bus.......................................................................................................... 124
6.3.4
Bus Control Signal Timing ............................................................................. 125
6.3.5
Wait Modes ..................................................................................................... 133
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