Document Outline

• Introduction
• Contents
• Section 1 Overview
  • 1.1 SuperH Microcomputer Features
  • 1.2 Block Diagram
  • 1.3 Pin Descriptions
    • 1.3.1 Pin Arrangement
    • 1.3.2 Pin Functions
    • 1.3.3 Pin Layout by Mode
    • Section 2 CPU
• Section 2 CPU
  • 2.1 Register Configuration
    • 2.1.1 General Registers (Rn)
    • 2.1.2 Control Registers
    • 2.1.3 System Registers
    • 2.1.4 Initial Values of Registers
  • 2.2 Data Formats
    • 2.2.1 Data Format in Registers
    • 2.2.2 Data Format in Memory
    • 2.2.3 Immediate Data Format
  • 2.3 Instruction Features
    • 2.3.1 RISC-Type Instruction Set
    • 2.3.2 Addressing Modes
    • 2.3.3 Instruction Formats
  • 2.4 Instruction Set
    • 2.4.1 Instruction Set by Classification
    • 2.4.2 Operation Code Map
  • 2.5 CPU State
    • 2.5.1 State Transitions
    • 2.5.2 Power-Down State
• Section 3 Operating Modes
  • 3.1 Types of Operating Modes and Their Selection
  • 3.2 Operating Mode Descriptions
    • 3.2.1 Mode 0 (MCU Mode 0)
    • 3.2.2 Mode 1 (MCU Mode 1)
    • 3.2.3 Mode 2 (MCU Mode 2)
    • 3.2.4 Mode 7 (PROM Mode)
• Section 4 Exception Processing
  • 4.1 Overview
    • 4.1.1 Exception Processing Types and Priorities
    • 4.1.2 Exception Processing Operation
    • 4.1.3 Exception Process Vector Table
  • 4.2 Reset
    • 4.2.1 Reset Types
    • 4.2.2 Power-On Reset
    • 4.2.3 Manual Reset
  • 4.3 Address Errors
    • 4.3.1 Address Error Sources
    • 4.3.2 Address Error Exception Processing
  • 4.4 Interrupts
    • 4.4.1 Interrupt Sources
    • 4.4.2 Interrupt Priority Rankings
    • 4.4.3 Interrupt Exception Processing
  • 4.5 Instruction Exceptions
    • 4.5.1 Types of Instruction Exceptions
    • 4.5.2 Trap Instruction
    • 4.5.3 Illegal Slot Instruction
    • 4.5.4 General Illegal Instructions
  • 4.6 Cases in Which Exceptions Are Not Accepted
    • 4.6.1 Immediately after Delayed Branch Instructions
    • 4.6.2 Immediately after Interrupt-Disabling Instructions
  • 4.7 Stack Status after Exception Processing
  • 4.8 Notes
    • 4.8.1 Value of the Stack Pointer (SP)
    • 4.8.2 Value of the Vector Base Register (VBR)
    • 4.8.3 Address Errors that Are Caused by Stacking During Address Error Exception Processing
• Section 5 Interrupt Controller (INTC)
  • 5.1 Overview
    • 5.1.1 Features
    • 5.1.2 Block Diagram
    • 5.1.3 Pin Configuration
    • 5.1.4 Registers
  • 5.2 Interrupt Sources
    • 5.2.1 NMI Interrupts
    • 5.2.2 User Break Interrupt
    • 5.2.3 IRQ Interrupts
    • 5.2.4 On-Chip Interrupts
    • 5.2.5 Interrupt Exception Vectors and Priority Rankings
  • 5.3 Register Descriptions
    • 5.3.1 Interrupt Priority Registers A�E (IPRA�IPRE)
    • 5.3.2 Interrupt Control Register (ICR)
  • 5.4 Interrupt Operation
    • 5.4.1 Interrupt Sequence
    • 5.4.2 Stack after Interrupt Exception Processing
  • 5.5 Interrupt Response Time
  • 5.6 Usage Notes
• Section 6 User Break Controller (UBC)
  • 6.1 Overview
    • 6.1.1 Features
    • 6.1.2 Block Diagram
    • 6.1.3 Register Configuration
  • 6.2 Register Descriptions
    • 6.2.1 Break Address Registers (BAR)
    • 6.2.2 Break Address Mask Register (BAMR)
    • 6.2.3 Break Bus Cycle Register (BBR)
  • 6.3 Operation
    • 6.3.1 Flow of the User Break Operation
    • 6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory
    • 6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception Processing
  • 6.4 Setting User Break Conditions
  • 6.5 Notes
    • 6.5.1 On-Chip Memory Instruction Fetch
    • 6.5.2 Instruction Fetch at Branches
    • 6.5.3 Instruction Fetch Break
• Section 7 Clock Pulse Generator (CPG)
  • 7.1 Overview
  • 7.2 Clock Source
    • 7.2.1 Connecting a Crystal Resonator
    • 7.2.2 External Clock Input
  • 7.3 Usage Notes
• Section 8 Bus State Controller (BSC)
  • 8.1 Overview
    • 8.1.1 Features
    • 8.1.2 Block Diagram