Document Outline
- Description
- Features
- Ordering Information
- Pin Arrangement
- Pin Description
- Pin Functions
- Function Overview
- Differences between HD64645 and HD64646
- Internal Block Diagram
- System Block Configuration Examples
- Interface to MPU
- Registers
- Functional Description
- System Configuration and Mode Setting
- Internal Registers
- Absolute Maximum Ratings
- Electrical Characteristics
- Load Circuit
1
HD64645/HD64646
LCTC (LCD Timing Controller)
ADE-207-276(Z)
'99.9
Rev. 0.0
Description
The HD64645/HD64646 LCTC is a control LSI for large size dot matrix liquid crystal displays. The LCTC
is software compatible with the HD6845 CRTC, since its programming method of internal registers and
memory addresses is based on the CRTC. A display system can be easily converted from a CRT to an
LCD.
The HD64646 LCTC is a modified version of the HD64645 LCTC with different LCD interface timing.
The LCTC offers a variety of functions and performance features such as vertical and horizontal scrolling,
and various types of character attribute functions such as reverse video, blinking, nondisplay (white or
black), and an OR function for simple superimposition of character and graphic displays. The LCTC also
provides DRAM refresh address output.
A compact LCD system with a large screen can be configured by connecting the LCTC with the
HD66110ST (column driver) and the HD66113T (common driver) by utilizing 4-bit
2 data outputs.
Power dissipation has been lowered by adopting the CMOS process.
Features
Software compatible with the HD6845 CRTC
Programmable screen size
Up to 1024 dots (height)
Up to 4096 dots (width)
High-speed data transfer
Up to 20 Mbits/s in character mode
Up to 40 Mbits/s in graphic mode
Selectable single or dual screen configuration
Programmable multiplexing duty ratio: static to 1/512 duty cycle
Programmable character font
1-32 dots (height)
8 dots (width)
HD64645/64646
2
Versatile character attributes: reverse video, blinking, nondisplay (white), nondisplay (black)
OR function: superimposing characters and graphics display
Cursor with programmable height, blink rate, display position, and on/off switch
Vertical Smooth Scrolling and horizontal scrolling by the character
Versatile display modes programmable by mode register or external pins: display on/off, graphic or
character, normal or wide, attributes, and blink enable
Refresh address output for dynamic RAM
4- or 8-bit parallel data transfer between LCTC and LCD driver
Recommended LCD driver
HD66110ST and HD66120 (segment)
HD66113T and HD66115T (common)
CPU interface
80 family
CMOS process
Single +5 V
10%
Ordering Information
Type No.
Package
HD64645F
80-pin plastic QFP (FP-80)
HD64646FS
80-pin plastic QFP (FP-80B)
HD64645/64646
3
Pin Arrangement
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RA0
RA1
RA2
RA3
RA4
GND1
G/C
AT
LS
D/S
WIDE
ON/OFF
MODE
BLE
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RD
WR
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA15
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
V
CC
1
LD3
LD2
LD1
LD0
LU3
LU2
LU1
LU0
M
FLM
CL1
CL2
SK0
SK1
V
CC
2
DCLK
MCLK
DISPTMG
CUDISP
GND2
RES
CS
RS
(Top view)
HD64645/64646
4
Pin Description
Symbol
Pin Number
I/O
Name
V
CC
1, V
CC
2
17, 32
--
V
CC
GND1, GND2
37, 59
--
Ground
LU0LU3
2225
O
LCD up panel data 03
LD0LD3
1821
O
LCD down panel data 03
CL1
28
O
Clock one
CL2
29
O
Clock two
FLM
27
O
First line marker
M
26
O
M
MA0MA15
6580
O
Memory address 015
RA0RA4
6064
O
Raster address 04
MD0MD7
18
I
Memory Data 07
MD8MD15
916
I
Memory Data 815
DB0DB7
4350
I/O
Data bus 07
CS
39
I
Chip select
WR
41
I
Write
RD
42
I
Read
RS
40
I
Register select
RES
38
I
Reset
DCLK
33
I
D clock
MCLK
34
O
M clock
DISPTMG
35
O
Display timing
CUDISP
36
O
Cursor display
SK0
30
I
Skew 0
SK1
31
I
Skew 1
ON/
OFF
53
I
On/off
BLE
51
I
Blink enable
AT
57
I
Attribute
G/
C
58
I
Graphic/character
WIDE
54
I
Wide
LS
56
I
Large screen
D/
S
55
I
Dual/single
MODE
52
I
Mode
HD64645/64646
5
Pin Functions
Power Supply (V
CC
1, V
CC
2, GND)
Power Supply Pin (+5 V): Connect V
CC
1 and V
CC
2 with +5V power supply circuit.
Ground Pin (0 V): Connect GND1 and GND2 with 0V.
LCD Interface
LCD Up Panel Data (LU0LU3), LCD Down Panel Data (LD0LD3): LU0LU3 and LD0LD3 output
LCD data as shown in Table 1.
Clock One (CL1): CL1 supplies timing clocks for display data latch.
Clock Two (CL2): CL2 supplies timing clock for display data shift.
First Line Marker (FLM): FLM supplies first line marker.
M (M): M converts liquid crystal drive output to AC.
Memory Interface
Memory Address (MA0MA15): MA0MA15 supply the display memory address.
Raster Address (RA0RA4): RA0RA4 supply the raster address.
Memory Data (MD0MD7): MD0MD7 receive the character dot data or bit-mapped data.
Memory Data (MD8MD15): MD8MD15 receive attribute code data or bit-mapped data.
MPU Interface
Data Bus (DB0DB7): DB0DB7 send/receive data as a three-state I/O common bus.
Chip Select (
CS): CS selects a chip. Low level enables MPU read/write of the LCTC internal registers.
Write (
WR): WR receives MPU write strobe.
Read (
RD): RD receives MPU read strobe.
Register Select (RS): RS selects registers. (Refer to Table 4.)
Reset (
RES): RES performs external reset of the LCTC. Low level of RES stops and zero-clears the LCTC
internal counter. No register contents are affected.
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