Document Outline
- Description
- Features
- Pin Arrangement
- Internal Block Diagram
- HIFAS Family timing Comparision
- Pin Functions
- Pin Functions (cont)
- Rearranging Output Data (SHL)
- Operation Timing
- (1) 4-bit capture mode (1 line, 640 dots)
- BS = GND (4-bit capture mode)
- (2) 8-bit capture mode (1 line, 640 dots)
- BS = Vcc (8-bit capture mode)
- Application Example
- Absolute Maximum Ratings
- Electrical Characteristics
- DC Characteristics 1 (Vcc = 2.5 to 4.5V, V0GND = 2.6 to 5.5V, Ta = 30 to +75C)
- DC Characteristics 2 (Vcc = 4.5 to 5.5V, V0GND = 2.6 to 5.5V, Ta = 30 to +75C)
- AC Characteristics 1 (Vcc = 2.5 to 4.5V, V0GND = 2.6 to 5.5V, Ta = 30 to +75C)
- AC Characteristics 2 (Vcc = 4.5V to 5.5V, V0GND = 2.6 to 5.5V, Ta = 30 to +75C)
1
HD66130T
320-channel Low-voltage Segment Driver for Dot-Matrix STN
Liquid Crystal Display
Description
The HD66130T is a 320-channel segment driver for driving a dot-matrix STN liquid-crystal panel at a low
voltage. The driver can also correspond to 240-channel output by switching mode. It operates at a low
voltage: a liquid-crystal drive voltage of 5 V and a logic drive voltage of 3 V, and is used together with
common driver HD66131T or HD66135T. The package, which adopts a flexible TCP, can be applied to
various liquid crystal panels.
Features
Display duty: Up to 1/240
Liquid crystal drive voltage: 2.6 to 5.5 V
Number of liquid crystal drive circuits: 320 circuits
Operating voltage: 2.5 to 5.5 V
Number of data bits: 4 or 8 bits
Shift clock speed: 8 MHz max/5V
6.5 MHz max/3V
Together with the common drivers
HD66131T , HD66135T
Low power consumption
Switching output mode: 320 output mode
240 output mode
Display-off function
Flexible TCP
Automatic generation of chip-enable signals
Standby function
HD66130T
2
Pin Arrangement
320
Y320
2Y
2
1 Y1
319
Y319
318
Y318
317
Y317
316
Y316
3Y
3
4Y
4
5Y
5
346
345
344
343
342
341
340
339
338
337
336
335
334
333
332
331
330
329
328
327
326
325
324
323
322
321
VML
V0L
V1L
V
CC
MODE
BS
GND2
SHL
EIO1
DISP
D0
D1
D2
D3
D4
D5
D6
D7
CL2
CL1
M
EIO2
GND1
V1R
V0R
VMR
Note: TCP dimensions are not defined.
Top View
Internal Block Diagram
Note: Pins V0L, VML, and V1L are internally connected to pins V0R, VMR, and V1R, respectively.
D0D7
CL2
SHL
EIO1
EIO2
CL1
Vcc
GND2
Y
1
Y
320
M
DISP
V0L
VML
V1L
BS
MODE
Level shifter
Latch circuit 2
Data
rearrangement
circuit
GND1
*
V0L
VML
V1L
Shift register
Latch circuit 1
Latch circuit 1
Timing
generator
circuit
Level
shifter
Liquid crystal drive circuit
HD66130T
3
1. Liquid crystal drive circuit
Selects and outputs the liquid crystal drive level V0, VM, or V1 by
DISP and a combination of data for
latch circuit 2 and signal M.
2. Level shifter
Converts logic signals to liquid crystal drive signals.
3. Latch circuit 2
320-bit latch circuit, which latches the data of latch circuits 1 at the fall of CL1 and outputs the data to
the level shifter.
4. Latch circuit 1
4/8-bit parallel data latch circuit, which latches display data D0 to D7 according to signals transmitted
from the shift register.
5. Shift register
80-bit shift register, which generates data-capture signals for latch circuits 1 at the fall of CL2.
6. Data rearrangement circuit
Inverts the order of data output crosswise.
7. Timing generator circuit
The timing generator circuit generates data latch pulses for latch circuit2 and changes pulse the LCD
drive outputs to AC.
HIFAS Family timing Comparision
HD66130/131/134/135
HD66132/133
Input
signal
Output
signal
Segment
Common
CL1
M
HD66130T
4
Pin Functions
Class
Symbol
Pin
Number
Pin
Name
I/O
Functions
Power
supply
V
CC
GND1
GND2
343
324
340
V
CC
GND
--
V
CC
GND: Power supply for logic.
V0L, R
VML, R
V1L, R
345, 322
346, 321
344, 323
V0L, R
VML, R
V1L, R
Input Liquid crystal drive level power supply
V0
VM
V1
Control
signal
CL1
327
Clock 1
Input Latch signal of display data: A liquid crystal drive signal
corresponding to display data is output at the fall of CL1.
CL2
328
Clock 2
Input Capture signal of display data: Display data is captured
at the fall of CL2.
M
326
M
Input A.C. signal of liquid crystal drive output
D0 to D7 336 to
329
DATA 0
to
DATA 7
Input
Display data Liquid crystal drive output Liquid crystal display
1 (Vcc level)
Selected level
ON
OFF
Not-selected level
0 (GND level)
SHL
339
Shift Left Input Control signal for inverting the order of data output
(see the following page)
EIO1
338
Enable
IO1
I/O
SHL
GND
Vcc
Enable input
Enable output
Enable input
Enable output
EI/O1
EI/O2
EIO2
325
Enable
IO2
I/O
Enable input: The enable input of the first IC is
connected to the GND and another is connected to the
enable output of the second IC.
Enable output: Connected to the enable input of the
second IC at cascade output.
DISP
337
Disp off
Input Grounding
DISP
sets liquid crystal drive output Y1Y320
to the VM level.
BS
341
Bus
Select
Input Switches the number of input bits for the display data.
Vcc
GND
8-bit input mode
4-bit input mode (Captures data from D0D3. At this
time, connect D4D7 to the GND.)
MODE
342
MODE
Input Switches the number of input bits for the display data.
Vcc
GND
320 output mode
240 output mode (Y41Y280 are valid output. The
other 80 pins output the not-selected-level signals
synchronized every time; release these pins.)
HD66130T
5
Pin Functions (cont)
Class
Symbol
Pin
Number
Pin
Name
I/O
Function
Liquid crystal
drive output
Y1 to
Y320
1 to 320 Y1 to
Y320
Output Liquid crystal drive output: Selects and outputs level
V0 or V1 according to the combination of the M signal
and display data when
DISP
is connected to Vcc.
1
0
1
1
0
0
V0
V1
V1
V0
M
D
Output level
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