Document Outline
- Description
- Features
- Ordering Information
- Pin Arrangement
- Pin Description
- Resister List
- RMW
- DISP
- STBY
- PWR
- AMP
- REV
- HOLT
- ADC
- BIS1, 0
- WLS
- GRAY
- DTY1, 0
- INC
- BLK
- Block Diagram
- System Description
- MPU Interface
- LCD Driver Configuration
- Multi-LSI Operation
- Display RAM Configuration and Display
- Word Length
- Configuration of Display Data Bit
- Packed Pixel Method
- Gray scale/Colour palette
- Access to Internal Registers and Display RAM
- Display RAM Reading by LCD Controller:
- Vertical Scroll Function
- Partial Display Function
- Blink Function
- Power Down Modes
- Power On/Off Procedure
- Oscillator
- Changing Oscillator
- Clock and Frame Frequency
- Power Supply Circuits
- Reset
- Initial Setting of Pins:
- Bus interface pins
- LCD driver output pins
- Internal Registers
- Absolute Maximum Ratings
- Electrical Characteristics
- DC Characteristics (Vcc = 2.2 to 5.5V, GND = 0V, VLCD = 6 to 13V, Ta = 40 to +85C)*10
- AC Characteristics (Vcc = 2.2V to 5.5V, GND = 0V, Ta = 40 to +85C)*
- Clock Characteristics
- Reset Timing
- MPU Interface
1
HD66420
(RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot
Matrix Graphics LCD)
Description
The HD66420 drives and controls a dot matrix graphic LCD(Liquid Crystal Display) using a bit-mapped
method. It provides a highly flexible display through its on-chip display RAM, in which each two bits of
data can be used to turn on or off one dot on LCD panel with four-level grey scale.
A single HD66420 can display a maximum of 160x80 dots using its powerful display control functions. It
can display only eight lines out of eighty lines. This function realize low power consumption because high
voltage for driving LCD is not needed.
An MPU can access HD66420 at any time, because the MPU operations are asynchronous with the
HD66420's system clock and display operation.
Its low-voltage operation at 2.2 to 5.5V and standby function provides low power dissipation, making the
HD66420 suitable for small portable device applications.
Features
Built-in bit-mapped display RAM: 25.6kbits (160
80
2 bits)
Grey scale display: PWM four-level grey scale can be selected from 32 levels
Grey scale memory management: Packed pixel
Partial display: Eight-lines data can be displayed in any place
An 80-system MPU interface
Power supply voltage for operation : 2.2V to 5.5V
Power supply voltage for LCD : 13 V max.
Selectable multiplex duty ratio: 1/8, 1/32, 1/64, 1/80
Built-in oscillator: external resister
Low power consumption:
55
A typ. 80
A max. during display
0.1
A typ. 5
A max. during standby
Circuits for generating LCD driving voltage : Contrast control, Operational amplifier, and Resistive
dividers
Internal resistive divider: programmable bias rate
32-level programmable contrast control
HD66420
2
Wide range of instructions reversible display, display on/off, vertical display scroll, blink, reversible
address, read-modify-write mode
Package: TCP
Ordering Information
Type No.
Package
HD66420TA0
TCP
HD66420
3
Pin Arrangement
Note: This figure is not drawn to a scale
COM80
COM79
COM78
COM41
SEG160
SEG159
SEG158
COM40
SEG3
SEG2
SEG1
COM39
COM3
COM2
COM1
I/O,Power supply pins
LCD drive signal output pins
GND1
VLCD1
VCC1
V5O
V4O
V3O
V2O
V1O
GREF
IREFM
IREFP
VLCD2
VLCD3
VCC2
GND2
GND3
VCC3
OSC1
OSC2
OSC
CO
DCON
CL1
FLM
M
M/S
RES
CS
RS
WR
RD
VCC4
GND4
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VCC5
GND5
VCC6
VLCD4
GND6
HD66420
4
Pin Description
Pin Name
Number of
Pins
I/O
Connected to
Description
V
CC
16,
GND16
12
--
Power supply
V
CC
: +2.2V to +5.5V, GND: 0V
VLCD14
4
--
Power supply
Power supply to LCD driving circuit
V1O, V2O,
V3O, V4O,
V5O
5
--
V1 to V5 of
HD66420
Several levels of power to the LCD driving outputs.
Master HD66420 outputs these levels to the slave
HD66420.
OSC
1
I
Oscillator
resister or
Must be connected to external resister when using R-C
oscillation. When using an external clock, it must be
OSC1,
OSC2
2
I/O
external clock
input to the OSC terminal.
CO
1
O
OSC of Slave
HD66420
Clock output
DCON
1
O
External DC/DC
convertor
Controls on/off switch of external DC/DC convertor
CL1
1
I/O
CL1 of
HD66420
Line clock
FLM
1
I/O
FLM of
HD66420
Frame signal
M
1
I/O
M of HD66420
Converts LCD driving outputs to AC
M/S
1
I
V
CC
or GND
Specifies master/slave mode.
RES
1
I
--
Reset the LSI internally when drive low.
CS
1
I
MPU
Select the LSI, specifically internal registers (index and
data registers) when driven low.
RS
1
I
MPU
Select one of the internal registers; select the index
register when driven low and data registers when driven
low.
WR
1
I
MPU
Inputs write strobe; allows a write access when driven
low.
RD
1
I
MPU
Inputs read strobe; allows a read access when driven
low.
DB7 to DB0 8
I/O
MPU
8-bits three-state bidirectional data bus; transfer data
between the HD66420 and MPU through this bus.
SEG1 to
SEG160
160
O
LCD
Output column drive signals
COM1 to
COM80
80
O
LCD
Output row drive signals
IREFP
1
--
V
CC
Power supply for internal operation amplifier
IREFM
1
--
External resistor Bias current for internal operational amplifier
GREF
1
--
GND
Power supply for internal operation amplifier
HD66420
5
Resister List
Index
Reg.Bits
Data bits
CS RS 4 3 2 1 0
Register Name
R/W
7
6
5
4
3
2
1
0
1
0
0
IR
Index register
W
IR4
IR3
IR2
IR1
IR0
0
1
0 0 0 0 0 R0
Control register 1
W
RMW DISP STBY PWR AMP REV
HOLT ADC
0
1
0 0 0 0 1 R1
Control register 2
W
BIS1
BIS0 WLS
GRAY DTY1 DTY0 INC
BLK
0
1
0 0 0 1 0 R2
X address register
W
XA5
XA4
XA3
XA2
XA1
XA0
0
1
0 0 0 1 1 R3
Y address register
W
YA6
YA5
YA4
YA3
YA2
YA1
YA0
0
1
0 0 1 0 0 R4
Display RAM access register
R/W
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0 0 1 0 1 R5
Display start line register
W
ST6
ST5
ST4
ST3
ST2
ST1
ST0
0
1
0 0 1 1 0 R6
Blink start line register
W
BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0
0
1
0 0 1 1 1 R7
Blink end line register
W
BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0
0
1
0 1 0 0 0 R8
Blink register 1
W
BK0
BK1
BK2
BK3
BK4
BK5
BK6
BK7
0
1
0 1 0 0 1 R9
Blink register 2
W
BK8
BK9
BK10 BK11 BK12 BK13 BK14 BK15
0
1
0 1 0 1 0 R10 Blink register 3
W
BK16 BK17 BK8
BK9
0
1
0 1 0 1 1 R11 Partial display block register
W
PB3
PB2
PB1
PB0
0
1
0 1 1 0 0 R12 Gray scale palette 1 (0, 0)
W
GP14 GP13 GP12 GP11 GP10
0
1
0 1 1 0 1 R13 Gray scale palette 2 (0, 1)
W
GP24 GP23 GP22 GP21 GP20
0
1
0 1 1 1 0 R14 Gray scale palette 3 (1, 0)
W
GP34 GP33 GP32 GP31 GP30
0
1
0 1 1 1 1 R15 Gray scale palette 4 (1, 1)
W
GP44 GP43 GP42 GP41 GP40
0
1
1 0 0 0 0 R16 Contrast control register
W
CM1 CM0
CC4
CC3
CC2
CC1
CC0
0
1
1 0 0 0 1 R17 Reserved
0
1
1 0 0 1 0 R18 Reserved
0
1
1 0 0 1 1 R19 Reserved
0
1
1 0 1 0 0 R20 Reserved
0
1
1 0 1 0 1 R21 Reserved
0
1
1 0 1 1 0 R22 Reserved
0
1
1 0 1 1 1 R23 Reserved
0
1
1 1 0 0 0 R24 Reserved
0
1
1 1 0 0 1 R25 Reserved
0
1
1 1 0 1 0 R26 Reserved
0
1
1 1 0 1 1 R27 Reserved
0
1
1 1 1 0 0 R28 Reserved
0
1
1 1 1 0 1 R29 Reserved
0
1
1 1 1 1 0 R30 Reserved
0
1
1 1 1 1 1 R31 Reserved
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