HD74AC195
4-bit Parallel-Access Shift Register
Description
This shift register features parallel inputs, parallel outputs, J-
K serial inputs, Shift/Load control input, and a
direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q
0
towards
Q
3
.
Parallel loading is accomplished by applying the four bits of data, and taking the
PE Input low. The data is
loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input.
During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the
PE
input is high. Serial data for this mode is entered at the J-
K inputs. These inputs allow the first stage to
perform as a J-
K or toggle flip-flop as shown in the function table.
Features
Shift Right and Parallel Load Capability
J-
K (D-Type) Inputs to First Stage
Complement Output from Last Stage
Asynchronous Master Reset
Outputs Source/Sink 24 mA
HD74AC195
2
Pin Arrangement
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MR
J
K
D
0
D
1
D
3
D
2
GND
V
CC
Q
0
Q
1
Q
2
Q
3
Q
3
CP
PE
(Top view)
Logic Symbol
J
Q
3
CP
K
PE
D
0
D
1
D
2
D
3
MR
Q
0
Q
1
Q
2
Q
3
Pin Names
CP
Clock Pulse Input (Active Rising Edge)
D
0
to D
3
Parallel Data Inputs
PE
Parallel Enable Input
MR
Asynchronous Master Reset
J,
K
J-
K or D Type Serial Inputs
Q
0
to Q
3
,
Q
3
Outputs
HD74AC195
3
Timing Diagram
CP
J
D
0
D
1
D
2
D
3
Q
0
Q
1
Q
2
Q
3
K
PE
MR
Serial Shift
Serial Shift
Load
Clear
L
H
L
H
Mode Select-Function Table
Inputs
Outputs
Operating Modes
MR
CP
PE
J
K
D
n
Q
0
Q
1
Q
2
Q
3
Q
3
Asynchronous Reset
L
X
X
X
X
X
L
L
L
L
H
Shift, Set First Stage
H
H
H
H
X
H
q
0
q
1
q
2
q
2
Shift, Reset First Stage
H
H
L
L
X
L
q
0
q
1
q
2
q
2
Shift, Toggle First Stage
H
H
H
L
X
q
0
q
0
q
1
q
2
q
2
Shift, Retain First Stage
H
H
L
H
X
q
0
q
0
q
1
q
2
q
2
Parallel Load
H
L
X
X
d
n
d
0
d
1
d
2
d
3
d
3
H :
HIGH Voltage Level
L
:
LOW Voltage Level
X :
Immaterial
Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-
HIGH transition.
:
LOW-to-HIGH clock transition.
HD74AC195
4
Logic Diagram
PE
MR
CP
D
3
D
2
D
1
D
0
Q
0
Q
1
Q
2
Q
3
Q
3
V
CC
J
V
CC
K
DC Characteristics (unless otherwise specified)
Item
Symbol
Max
Unit
Condition
Maximum quiescent supply current
I
CC
80
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
Maximum quiescent supply current
I
CC
8.0
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25
C
HD74AC195
5
AC Characteristics: HD74AC195
Ta = +25
C
C
L
= 50 pF
Ta = 40
C to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Min
Typ
Max
Min
Max
Unit
Maximum clock
f
max
3.3
75
--
--
65
--
MHz
frequency
5.0
100
--
--
85
--
Propagation delay
t
PLH
3.3
1.0
9.0
13.0
1.0
15.0
ns
CP to Q
n
or
Q
3
5.0
1.0
5.5
10.0
1.0
11.5
Propagation delay
t
PHL
3.3
1.0
9.0
13.0
1.0
15.0
ns
CP to Q
n
or
Q
2
5.0
1.0
6.5
10.0
1.0
11.5
Propagation delay
t
PLH
3.3
1.0
7.5
10.5
1.0
12.0
ns
MR
to
Q
2
5.0
1.0
5.5
8.0
1.0
9.5
Propagaion delay
t
PHL
3.3
1.0
6.0
9.0
1.0
10.5
ns
MR
to
Q
n
5.0
1.0
5.0
7.0
1.0
8.0
Note:
1. Voltage Range 3.3 is 3.3 V
0.3 V
Voltage Range 5.0 is 5.0 V
0.5 V
AC Operating Requirements: HD74AC195
Ta = +25
C
C
L
= 50 pF
Ta = 40
C
to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Typ
Guaranteed Minimum
Unit
Setup time, HIGH or LOW
t
su
3.3
3.0
5.5
7.0
ns
J,
K
or
D
n
to CP
5.0
2.0
4.0
5.0
Hold time, HIGH or LOW
t
h
3.3
0.5
2.0
3.6
ns
J,
K
or
D
n
to CP
5.0
0.5
1.5
2.0
Setup time, HIGH or LOW
t
su
3.3
3.5
5.0
7.0
ns
PE
to CP
5.0
2.5
4.0
5.0
Hold time, HIGH or LOW
t
h
3.3
2.0
0.0
0.0
ns
PE
to CP
5.0
1.5
0.0
0.0
Recovery time
t
rec
3.3
1.5
0.5
0.5
ns
MR
to CP
5.0
1.0
0.5
0.5
Pulse width
t
w
3.3
3.0
5.5
7.0
ns
5.0
3.0
4.5
5.0
Note:
1. Voltage Range 3.3 is 3.3 V
0.3 V
Voltage Range 5.0 is 5.0 V
0.5 V
PDF 
ZIP