HD74AC393
Dual Modulo-16-Counter
Description
The HD74AC393 contains a pair of high speed 4-stage ripple counters. Each half of the HD74AC393
operates as a modulo-16 binary divider, with the last three stages triggered in a ripple fashion. The flip-
flops are triggered by a High-to-Low transition of their
CP inputs. Each half of each circuit type has a
Master Reset input which responds to a High signal by forcing all four outputs to the Low state.
Feature
Outputs Source/Sink 24 mA
Pin Arrangement
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CP
MR
Q
0
Q
1
Q
2
Q
3
GND
V
CC
CP
MR
Q
0
Q
1
Q
2
Q
3
(Top view)
HD74AC393
2
Logic Symbol (each half)
MR
Q
0
Q
1
Q
2
Q
3
CP
2, 12
1, 13
3, 11
5, 9
4, 10
6, 8
Vcc=Pin14
GND=Pin7
Pin Names
CP
Clock Pulse Input (Active Falling Edge)
MR
Asynchronous Master Reset Input (Active High)
Q
0
Q
3
Flip-flop Outputs
Functional Description
Each half of the HD74AC393 operates in the modulo-16 binary sequence, as indicated in the + 16 Truth
Table. The first flip-flop is triggered by High-to-Low transitions of the
CP input signal. Each of the other
flip-flops is triggered by a High-to-Low transition of the Q output of the preceding flip-flop. Thus state
changes of the Q outputs do not occur simultaneously. This means that logic signals derived from
combinations of these outputs will be subject to decoding spikes and, therefore, should not be used as
clocks for other counters, registers or flip-flops. A High signal on MR forces all outputs to the Low state
and prevents counting.
HD74AC393
3
Truth Table
Outputs
Count
Q
3
Q
2
Q
1
Q
0
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
H :
High Voltage Level
L
:
Low Voltage Level
Logic Diagram (one, half shown)
K
C
D
CP
J
Q
K
C
D
CP
J
Q
K
C
D
CP
J
Q
K
C
D
CP
J
Q
CP
MR
Q
0
Q
1
Q
2
Q
3
HD74AC393
4
DC Characteristics (unless otherwise specified)
Item
Symbol
Max
Unit
Condition
Maximum quiescent supply current
I
CC
80
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
Maximum quiescent supply current
I
CC
8.0
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25
C
AC Characteristics: HD74AC393
Ta = +25
C
C
L
= 50 pF
Ta = 40
C to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Min
Typ
Max
Min
Max
Unit
Maximum clock
f
max
3.3
125
--
--
100
--
MHz
frequency
5.0
150
--
--
125
--
Propagation delay
t
PLH
3.3
1.0
8.5
12.0
1.0
13.0
ns
CP
to Q
0
5.0
1.0
6.5
9.0
1.0
10.0
Propagation delay
t
PHL
3.3
1.0
8.0
11.5
1.0
12.5
ns
CP
to Q
0
5.0
1.0
6.0
8.5
1.0
9.5
Propagation delay
t
PLH
3.3
1.0
12.0
15.0
1.0
16.0
ns
CP
to Q
1
5.0
1.0
9.5
12.0
1.0
13.0
Propagation delay
t
PHL
3.3
1.0
11.5
14.5
1.0
15.5
ns
CP
to Q
1
5.0
1.0
9.0
11.5
1.0
12.5
Propagation delay
t
PLH
3.3
1.0
15.0
18.0
1.0
19.5
ns
CP
to Q
2
5.0
1.0
12.0
14.5
1.0
16.0
Propagation delay
t
PHL
3.3
1.0
14.5
17.5
1.0
19.0
ns
CP
to Q
2
5.0
1.0
11.5
14.0
1.0
15.5
Propagation delay
t
PLH
3.3
1.0
18.0
20.5
1.0
22.0
ns
CP
to Q
3
5.0
1.0
14.5
17.0
1.0
18.5
Propagation delay
t
PHL
3.3
1.0
17.5
20.0
1.0
21.5
ns
CP
to Q
3
5.0
1.0
14.0
16.5
1.0
17.5
Propagation delay
t
PHL
3.3
1.0
10.5
14.0
1.0
15.0
ns
MR to Q
0
, Q
1
, Q
2
or Q
3
5.0
1.0
8.5
11.0
1.0
12.0
Note:
1. Voltage Range 3.3 is 3.3 V
0.3 V
Voltage Range 5.0 is 5.0 V
0.5 V
HD74AC393
5
AC Operating Requirements: HD74AC393
Ta = +25
C
C
L
= 50 pF
Ta = 40
C
to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Typ
Guaranteed Minimum
Unit
Pulse width
CP
t
w
3.3
3.5
5.5
7.0
ns
5.0
2.5
4.5
5.0
Recovery time MR to
CP
t
rec
3.3
2.5
0.0
0.0
ns
5.0
2.5
0.0
0.0
Note:
1. Voltage Range 3.3 is 3.3 V
0.3 V
Voltage Range 5.0 is 5.0 V
0.5 V
Capacitance
Item
Symbol
Typ
Unit
Condition
Input capacitance
C
IN
4.5
pF
V
CC
= 5.5 V
Power dissipation capacitance
C
PD
50
pF
V
CC
= 5.0 V
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