HD74AC74
Dual D-Type Positive Edge-Triggered Flip-Flop
Description
The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q,
Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse.
Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input
is locked out and information present will not be transferred to the outputs until the next rising edge of the
Clock Pulse input.
Features
Asynchronous Inputs:
Low input to
S
D
(Set) sets Q to High level
Low input to
C
D
(Clear) sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on
C
D
and
S
D
makes both Q and
Q High
Outputs Source/Sink 24 mA
HD74AC74
2
Pin Arrangement
1
2
3
4
5
6
7
C
D1
D
1
CP
1
S
D1
Q
1
Q
1
GND
V
CC
C
D2
D
2
CP
2
S
D2
Q
2
Q
2
14
13
12
11
10
9
8
CP
1
CP
2
S
D1
C
D2
S
D2
C
D1
D
1
D
2
Q
1
Q
2
(Top view)
Q
2
Q
1
Logic Symbol
D
1
Q
1
Q
1
CP
1
C
D1
S
D1
S
D2
D
2
Q
2
Q
2
CP
2
C
D2
Pin Names
D
1
, D
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
,
C
D2
Direct Clear Inputs
S
D1
,
S
D2
Direct Set Inputs
Q
1
,
Q
1
, Q
2
,
Q
2
Outputs
HD74AC74
3
Truth Table (Each Half)
Inputs
Outputs
S
D
C
D
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q
0
Q
0
H
:
High Voltage Level
L
:
Low Voltage Level
X
:
Immaterial
: Low-to-High Clock Transition
Q
0
(
Q
0
) :
Previous Q (
Q
) before Low-to-High Transition of Clock
Logic Diagram
S
D
C
D
D
Q
Q
CP
Please note that this diagram is provised only for the understanding of logic operations and should not be
used to estimate propagation delays.
DC Characteristics (unless otherwise specified)
Item
Symbol
Max
Unit
Condition
Maximum quiescent supply current
I
CC
40
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
Maximum quiescent supply current
I
CC
4.0
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25
C
HD74AC74
4
AC Characteristics
Ta = +25
C
C
L
= 50 pF
Ta = 40
C to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Min
Typ
Max
Min
Max
Unit
Maximum clock
f
max
3.3
100
125
--
95
--
MHz
frequency
5.0
140
160
--
125
--
Propagation delay
t
PLH
3.3
1.0
8.0
12.0
1.0
13.0
ns
C
Dn
or
S
Dn
to Q
n
or
Q
n
5.0
1.0
6.0
9.0
1.0
10.0
Propagation delay
t
PHL
3.3
1.0
10.5
12.0
1.0
13.5
ns
C
Dn
or
S
Dn
to Q
n
or
Q
n
5.0
1.0
8.0
9.5
1.0
10.5
Propagation delay
t
PLH
3.3
1.0
8.0
13.5
1.0
16.0
ns
CP
n
to Q
n
or
Q
n
5.0
1.0
6.0
10.0
1.0
10.5
Propagation delay
t
PHL
3.3
1.0
8.0
14.0
1.0
14.5
ns
CP
n
to Q
n
or
Q
n
5.0
1.0
6.0
10.0
1.0
10.5
Note:
1. Voltage Range 3.3 is 3.3 V
0.3 V
Voltage Range 5.0 is 5.0 V
0.5 V
AC Operating Requirements: HD74AC74
Ta = +25
C
C
L
= 50 pF
Ta = 40
C
to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Typ
Guaranteed Minimum
Unit
Set-up time, HIGH or LOW
t
su
3.3
1.5
4.0
4.5
ns
D
n
to CP
n
5.0
1.0
3.0
3.0
Hold time, HIGH or LOW
t
h
3.3
2.0
0
0
ns
D
n
to CP
n
5.0
1.5
0
0
CP
n
or
C
Dn
or
S
Dn
t
w
3.3
3.0
5.5
7.0
ns
Pulse width
5.0
2.5
4.5
5.0
Recovery time
t
rec
3.3
2.5
0
0
ns
C
Dn
or
S
Dn
to CP
5.0
2.0
0
0
Note:
1. Voltage Range 3.3 is 3.3 V
0.3 V
Voltage Range 5.0 is 5.0 V
0.5 V
HD74AC74
5
Capacitance
Item
Symbol
Typ
Unit
Condition
Input capacitance
C
IN
4.5
pF
V
CC
= 5.5 V
Power dissipation capacitance
C
PD
35.0
pF
V
CC
= 5.0 V
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