HD74AC107/HD74ACT107
Dual JK Flip-Flop (with Separate Clear and Clock)
Description
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop.
Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the
coupling transistors which connect the master and slave sections. The sequence of operation is as follows:
1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs;
4) transfer information from master to slave.
Features
Outputs Source/Sink 24 mA
HD74ACT107 has TTL-Compatible Inputs
Pin Arrangement
1
2
3
4
5
6
7
J
1
Q
1
Q
1
K
1
Q
2
Q
2
GND
V
CC
C
D1
CP
1
K
2
C
D2
CP
2
J
2
14
13
12
11
10
9
8
(Top view)
HD74AC107/HD74ACT107
2
Logic Symbol
1
J
1
Q
1
Q
1
K
1
CP
1
C
D1
J
2
Q
2
Q
2
K
2
CP
2
C
D2
3
8
9
11
2
6
5
12
4
13
10
V
CC
= Pin14
GND = Pin7
Pin Names
J
1
, J
2
, K
1
, K
2
Data Inputs
CP
1
,
CP
2
Clock Pulse Inputs (Active Falling Edge)
C
D1
,
C
D2
Direct Clear Inputs (Active Low)
Q
1
, Q
2
,
Q
1
,
Q
2
Outputs
Truth Table
Inputs
Outputs
@ t
n
@ t
n + 1
J
K
Q
L
L
Qn
L
H
L
H
L
H
H
H
Q
n
H
:
High Voltage Level
L
:
Low Voltage Level
t
n
:
Bit time before clock pulse.
t
n + 1
:
Bit time after clock pulse.
HD74AC107/HD74ACT107
3
Logic Diagram
C
D
CP
CP
CP
CP
Q
Q
#CP
#CP
#
CP
#
CP
CP
CP
CP
J
K
DC Characteristics (unless otherwise specified)
Item
Symbol
Max
Unit
Condition
Maximum quiescent supply current
I
CC
80
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
Maximum quiescent supply current
I
CC
8.0
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25
C
Maximum additional I
CC
/input
(HD74ACT107)
I
CCT
1.5
mA
V
IN
= V
CC
2.1 V, V
CC
= 5.5 V
Ta = Worst case
HD74AC107/HD74ACT107
4
AC Characteristics: HD74AC107
Ta = +25
C
C
L
= 50 pF
Ta = 40
C to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Min
Typ
Max
Min
Max
Unit
Maximum clock
f
max
3.3
125
--
--
100
--
MHz
frequency
5.0
150
--
--
125
--
Propagation delay
t
PLH
3.3
1.0
9.5
13.0
1.0
14.0
ns
C
P
to Q or
Q
5.0
1.0
7.5
10.0
1.0
11.0
Propagation delay
t
PHL
3.3
1.0
10.0
13.5
1.0
14.5
ns
C
P
to Q or
Q
5.0
1.0
8.0
10.5
1.0
11.5
Propagation delay
t
PLH
3.3
1.0
9.5
13.0
1.0
14.0
ns
C
D
to
Q
5.0
1.0
7.5
10.0
1.0
11.0
Propagation delay
t
PHL
3.3
1.0
9.5
13.0
1.0
14.0
ns
C
D
to
Q
5.0
1.0
7.5
10.0
1.0
11.0
Note:
1. Voltage Range 3.3 is 3.3 V
0.3 V
Voltage Range 5.0 is 5.0 V
0.5 V
Operating Requirements: HD74AC107
Ta = +25
C
C
L
= 50 pF
Ta = 40
C
to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Typ
Guaranteed Minimum
Unit
Setup time
t
su
3.3
3.0
5.5
6.0
ns
J or k to
C
P
5.0
2.0
4.0
4.5
Hold time
t
h
3.3
1.5
0.0
0.0
C
P
to J or k
5.0
0.5
0.0
0.0
Pulse width
t
w
3.3
2.0
5.5
7.5
C
P
or
C
D
5.0
2.0
4.5
5.0
Recovery time
t
rec
3.3
2.5
0.0
0.0
C
D
to
C
P
5.0
1.5
0.0
0.0
Note:
1. Voltage Range 3.3 is 3.3 V
0.3 V
Voltage Range 5.0 is 5.0 V
0.5 V
HD74AC107/HD74ACT107
5
AC Characteristics: HD74ACT107
Ta = +25
C
C
L
= 50 pF
Ta = 40
C to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Min
Typ
Max
Min
Max
Unit
Maximum clock
frequency
f
max
5.0
100
--
--
80
--
MHz
Propagation delay
C
P
to Q or
Q
t
PLH
5.0
1.0
9.5
12.5
1.0
13.5
ns
Propagation delay
C
P
to Q or
Q
t
PHL
5.0
1.0
10.5
13.0
1.0
14.0
Propagation delay
C
D
to
Q
t
PLH
5.0
1.0
8.5
11.0
1.0
12.0
Propagation delay
C
D
to Q
t
PHL
5.0
1.0
8.5
11.0
1.0
12.0
Note:
1. Voltage Range 5.0 is 5.0 V
0.5 V
Operating Requirements: HD74ACT107
Ta = +25
C
C
L
= 50 pF
Ta = 40
C
to +85
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Typ
Guaranteed Minimum
Unit
Setup time
J or k to
C
P
t
su
5.0
2.5
7.0
8.0
ns
Hold time
C
P
to J or k
t
h
5.0
0.0
1.5
1.5
Pulse width
C
P
or
C
D
t
w
5.0
4.5
7.0
8.0
Recovery time
C
D
to
C
P
t
rec
5.0
--
3.0
3.0
Note:
1. Voltage Range 5.0 is 5.0 V
0.5 V
Capacitance
Item
Symbol
Typ
Unit
Condition
Input capacitance
C
IN
4.5
pF
V
CC
= 5.5 V
Power dissipation capacitance
C
PD
35.0
pF
V
CC
= 5.0 V
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