ChipFind - документация

Электронный компонент: HD74ALVC162835

Скачать:  PDF   ZIP
HD74ALVC162835
18-bit Universal Bus Driver with 3-state Outputs
ADE-205-201E (Z)
Preliminary
6th. Edition
January 1999
Description
The HD74ALVC162835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V
CC
operation.
Data flow from A to Y is controlled by the output enable (
OE). The device operates in the transparent mode
when the latch enable (LE) is high. When LE is low, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If the LE is low, the A data is stored in the latch/flip flop on the low to high
transition of CLK. When
OE is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE should be tied to V
CC
through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver.
All outputs, which are designed to sink up to 12 mA, include 26
resistors to reduce overshoot and
undershoot.
Features
Meets "PC SDRAM registered DIMM design support document, Rev. 1.2"
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25
C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25
C)
High output current
12 mA (@V
CC
= 3.0 V)
All outputs have equivalent 26
series resistors, so no external resistors are required
HD74ALVC162835
2
Function Table
Inputs
OE
LE
CLK
A
Output Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
L
L
L
H
H
L
L
L or H
X
Y
0
*1
H :
High level
L :
Low level
X :
Immaterial
Z :
High impedance
:
Low to high transition
Note:
1. Output level before the indicated steady-state input conditions were established.
HD74ALVC162835
3
Pin Arrangement
(Top view)
1
2
3
4
5
6
7
8
9
10
V
CC
NC
NC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y17
Y16
Y18
OE
LE
11
12
13
14
15
16
17
18
19
20
21
22
23
24
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
GND
GND
GND
GND 25
26
27
28
A17
32 GND
31 A18
30 CLK
29 GND
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
GND
A6
A5
A4
A3
A2
A1
GND
NC
V
CC
GND
V
CC
V
CC
GND
HD74ALVC162835
4
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage range
V
CC
0.5 to 4.6
V
Input voltage range
*1
V
I
0.5 to 4.6
V
Output voltage range
*1,
2
V
O
0.5 to V
CC
+0.5
V
Input clamp current
I
IK
50
mA
V
I
< 0
Output clamp current
I
OK
50
mA
V
O
< 0 or V
O
> V
CC
Continuous output current
I
O
50
mA
V
O
= 0 to V
CC
V
CC
, GND current / pin
I
CC
or I
GND
100
mA
Maximum power dissipation
at Ta = 55
C (in still air)
*3
P
T
1
W
TSSOP
Storage temperature range
Tstg
65 to 150
C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those indicated under "recommended operating condition" is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. The input and output positive-voltage ratings may be exceeded up to 4.6 V if the input and output
clamp-current ratings are observed.
3. The maximum power dissipation is calculated using a junction temperature of 150
C and board
trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Conditions
Supply voltage
V
CC
2.3
3.6
V
Input voltage
V
I
0
V
CC
V
Output voltage
V
O
0
V
CC
V
High-level output current
I
OH
--
6
mA
V
CC
= 2.3 V
--
8
V
CC
= 2.7 V
--
12
V
CC
= 3.0 V
Low-level output current
I
OL
--
6
mA
V
CC
= 2.3 V
--
8
V
CC
= 2.7 V
--
12
V
CC
= 3.0 V
Input transition rise or fall rate
t/
v
0
10
ns/V
Operating free-air temperature
Ta
40
85
C
Note: Unused or floating control pins must be held high or low.
HD74ALVC162835
5
Logic Diagram
OE
LE
A1
27
30
28
54
3
Y1
CLK
C1
1D
CLK
To seventeen other channels