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Электронный компонент: HD74ALVCH16269

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HD74ALVCH16269
12-bit to 24-bit Registered Bus Transceivers
with 3-state Outputs
ADE-205-136 (Z)
Preliminary 1st. Edition
May 1996
Description
The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or
demultiplexed from, a single port. The device is particularly suitable as an interface between
synchronous DRAMs and high speed microprocessors. Data is stored in the internal B port registers on
the low to high transition of the clock (CLK) input when the appropriate clock enable (
CLKENA)
inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a
24-bit word on the B port. For data transfer in the B to A direction, a single storage register is
provided. The select (
SEL) line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, thus extending the period that the data is valid on the bus.
The control terminals are registered so that all transactions are synchronous with CLK. Data flow is
controlled by the active low output enables (
OEA, OEB1, OEB2). Active bus hold circuitry is
provided to hold unused or floating data inputs at a valid logic level.
Features
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25C)
High output current 24 mA (@V
CC
= 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16269
Function Table
Inputs
Outputs
CLK
OEA
OEB
A
1B, 2B
H
H
Z
Z
H
L
Z
Active
L
H
Active
Z
L
L
Active
Active
Output enable
Inputs
Outputs
CLKENA1
CLKENA2
CLK
A
1B
2B
H
H
X
X
1B
0
*1
2B
0
*1
L
X
L
L
X
L
X
H
H
X
X
L
L
X
L
X
L
H
X
H
A-to-B storage (
OEB = L)
Inputs
Output A
CLK
SEL
1B
2B
X
H
X
X
A
0
*1
X
L
X
X
A
0
*1
H
L
X
L
H
H
X
H
L
X
L
L
L
X
H
H
B-to-A storage (
OEA = L)
H : High level
L : Low level
X : Immaterial
Z : High impedance
: Low to high transition
Note:
1. Output level before the indicated steady state input conditions were established.
HD74ALVCH16269
Pin Arrangement
(Top view)
1
2
3
4
5
6
7
8
9
10
V
CC
V
CC
OEB1
2B3
GND
2B2
2B1
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
1B1
1B2
OEA
11
12
13
14
15
16
17
18
19
20
21
22
23
24
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1B5
GND 25
32 GND
1B3 26
31 1B4
NC 27
30
CLKENA1
SEL
28
29 CLK
1B6
1B7
1B8
1B9
1B10
GND
1B11
1B12
2B12
2B11
2B10
GND
2B9
2B8
2B7
2B6
2B5
2B4
OEB2
GND
CLKENA2
V
CC
V
CC
HD74ALVCH16269
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage
V
CC
0.5 to 4.6
V
Input voltage
*1, 2
V
I
0.5 to 4.6
V
Except I/O ports
0.5 to V
CC
+0.5
I/O ports
Output voltage
*1, 2
V
O
0.5 to V
CC
+0.5
V
Input clamp current
I
IK
50
mA
V
I
< 0
Output clamp current
I
OK
50
mA
V
O
< 0 or V
O
> V
CC
Continuous output current
I
O
50
mA
V
O
= 0 to V
CC
100
Maximum power dissipation
at Ta = 55
C (in still air)
*3
P
T
1
W
TSSOP
Storage temperature
Tstg
65 to 150
C
Notes:
Stresses beyond those listed under "absolute maximum ratings" may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute maximum rated conditions for extended
periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output
clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of
150
C and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Conditions
Supply voltage
V
CC
2.3
3.6
V
Input voltage
V
I
0
V
CC
V
Output voltage
V
O
0
V
CC
V
High level output current
I
OH
--
12
mA
V
CC
= 2.3 V
--
12
V
CC
= 2.7 V
--
24
V
CC
= 3.0 V
Low level output current
I
OL
--
12
mA
V
CC
= 2.3 V
--
12
V
CC
= 2.7 V
--
24
V
CC
= 3.0 V
Input transition rise or fall rate
t /
v
0
10
ns / V
Operating temperature
Ta
40
85
C
Note:
Unused control inputs must be held high or low to prevent them from floating.
HD74ALVCH16269
Logic Diagram
1 of 12 Channels
1D
C1
1D
C1
1D
C1
1D
CE
C1
1D
CE
C1
1D
C1
1D
C1
CLK
OEB1
OEB2
CLKENA1
SEL
OEA
A1
1B1
2B1
CLKENA2
G1
1
1
29
2
56
23
6
30
55
28
1
8