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Электронный компонент: HD74ALVCH16821

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HD74ALVCH162820
3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs
ADE-205-185B (Z)
3rd. Edition
December 1999
Description
The HD74ALVCH162820 flip flops are edge triggered D-type flip flops. On the positive transition of the
clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (
OE) input can
be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high
impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly.
The high impedance state and increased drive provide the capability to drive bus line without need for
interface or pullup components.
OE does not affect the internal operations of the flip flops. Old data can
be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold
circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are
designed to sink up to 12 mA, include 26
resistors to reduce overshoot and undershoot.
Features
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25
C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25
C)
High output current
12 mA (@V
CC
= 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
All outputs have equivalent 26
series resistors, so no external resistors are required.
HD74ALVCH162820
2
Function Table
Inputs
Output Q
OE
n
*2
CLK
D
L
H
H
L
L
L
L
L
X
Q
0
*1
H
X
X
Z
H : High level
L : Low level
X : Immaterial
Z : High impedance
: Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established.
2. n = 1, 2
HD74ALVCH162820
3
Pin Arrangement
(Top view)
1
2
3
4
5
6
7
8
9
10
V
CC
V
CC
1Q1
1Q2
GND
2Q1
2Q2
3Q1
3Q2
4Q1
GND
4Q2
5Q1
5Q2
6Q1
6Q2
7Q1
GND
7Q2
8Q1
8Q2
9Q1
9Q2
1
OE
11
12
13
14
15
16
17
18
19
20
21
22
23
24
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
GND 25
32 GND
10Q1 26
31 D10
10Q2 27
30 NC
2
OE
28
29 NC
D9
NC
D8
NC
D7
GND
NC
D6
NC
D5
NC
GND
D4
NC
D3
NC
D2
NC
CLK
GND
D1
V
CC
V
CC
HD74ALVCH162820
4
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage
V
CC
0.5 to 4.6
V
Input voltage
*1
V
I
0.5 to 4.6
V
Output voltage
*1, 2
V
O
0.5 to V
CC
+0.5
V
Input clamp current
I
IK
50
mA
V
I
< 0
Output clamp current
I
OK
50
mA
V
O
< 0 or V
O
> V
CC
Continuous output current
I
O
50
mA
V
O
= 0 to V
CC
V
CC
, GND current / pin
I
CC
or I
GND
100
mA
Maximum power dissipation
at Ta = 55
C (in still air)
*3
P
T
1
W
TSSOP
Storage temperature
Tstg
65 to 150
C
Notes:
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150
C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Conditions
Supply voltage
V
CC
2.3
3.6
V
Input voltage
V
I
0
V
CC
V
Output voltage
V
O
0
V
CC
V
High level output current
I
OH
--
6
mA
V
CC
= 2.3 V
--
8
V
CC
= 2.7 V
--
12
V
CC
= 3.0 V
Low level output current
I
OL
--
6
mA
V
CC
= 2.3 V
--
8
V
CC
= 2.7 V
--
12
V
CC
= 3.0 V
Input transition rise or fall rate
t /
v
0
10
ns / V
Operating temperature
Ta
40
85
C
Note:
Unused control inputs must be held high or low to prevent them from floating.
HD74ALVCH162820
5
Logic Diagram
1
OE
2
OE
1
55
CLK
D1
56
28
1Q2
3
1Q1
2
1D
C1
To nine other channels