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Электронный компонент: HD74HC107

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HD74HC107
Dual J-K Flip-Flops (with Clear)
Description
This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the
clock pulse. Each one has independent J, K, clock, and clear inputs and Q and
Q outputs. Clear is
independent of the clock and accomplished by a low level on the input.
Features
High Speed Operation: t
pd
(Clock to Q) = 19 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 A max
Low Quiescent Supply Current: I
CC
(static) = 2 A max (Ta = 25C)
Function Table
Inputs
Output
Clear
Clock
J
K
Q
Q
L
X
X
X
L
H
H
L
L
No change
H
L
H
L
H
H
H
L
H
L
H
H
H
Toggle
H
L
X
X
No change
H
H
X
X
No change
H
X
X
No change
HD74HC107
2
Pin Arrangement
1
Q
Q
CK
J
K
CLR
(Top View)
2
3
4
5
6
7
1J
1Q
1Q
1K
2Q
2Q
GND
VCC
1CLR
1CK
2K
2CLR
2CK
2J
14
13
12
11
10
9
8
Q
Q
CK
K
J
CLR
Block Diagram (1/2)
CK
Q
Q
CK
CK
CLR
J
K
CK
CK
CK
CK
CK
CK
CK
CK
HD74HC107
3
DC Characteristics
Ta = 25
C
Ta = 40 to
+85
C
Item
Symbol
V
CC
(V) Min Typ Max Min
Max
Unit
Test Conditions
Input voltage
V
IH
2.0
1.5
--
--
1.5
--
V
4.5
3.15 --
--
3.15
--
6.0
4.2
--
--
4.2
--
V
IL
2.0
--
--
0.5
--
0.5
V
4.5
--
--
1.35 --
1.35
6.0
--
--
1.8
--
1.8
Output voltage
V
OH
2.0
1.9
2.0
--
1.9
--
V
Vin = V
IH
or V
IL
I
OH
= 20
A
4.5
4.4
4.5
--
4.4
--
6.0
5.9
6.0
--
5.9
--
4.5
4.18 --
--
4.13
--
I
OH
= 4 mA
6.0
5.68 --
--
5.63
--
I
OH
= 5.2 mA
V
OL
2.0
--
0.0
0.1
--
0.1
V
Vin = V
IH
or V
IL
I
OL
= 20
A
4.5
--
0.0
0.1
--
0.1
6.0
--
0.0
0.1
--
0.1
4.5
--
--
0.26 --
0.33
I
OL
= 4 mA
6.0
--
--
0.26 --
0.33
I
OL
= 5.2 mA
Input current
Iin
6.0
--
--
0.1 --
1.0
A
Vin = V
CC
or GND
Quiescent supply
current
I
CC
6.0
--
--
2.0
--
20
A
Vin = V
CC
or GND, Iout = 0
A
HD74HC107
4
AC Characteristics (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Ta = 25
C
Ta = 40 to
+85
C
Item
Symbol
V
CC
(V) Min Typ Max Min
Max
Unit
Test Conditions
Maximum clock
f
max
2.0
--
--
6
--
5
MHz
frequency
4.5
--
--
30
--
24
6.0
--
--
35
--
28
Propagation delay t
PLH
2.0
--
--
150 --
190
ns
Clock to Q or
Q
time
t
PHL
4.5
--
19
30
--
38
6.0
--
--
26
--
33
2.0
--
--
140 --
175
ns
Clear to Q or
Q
4.5
--
17
28
--
35
6.0
--
--
24
--
30
Pulse width
t
w
2.0
80
--
--
100
--
ns
Clock, Clear
4.5
16
7
--
20
--
6.0
14
--
--
17
--
Setup time
t
su
2.0
100 --
--
125
--
ns
J or K to Clock
4.5
20
3
--
25
--
6.0
17
--
--
21
--
Hold time
t
h
2.0
5
--
--
5
--
ns
Clock to J or K
4.5
5
2
--
5
--
6.0
5
--
--
5
--
Removal time
t
rem
2.0
100 --
--
125
--
ns
Clear to Clock
4.5
20
0
--
25
--
6.0
17
--
--
21
--
Output rise/fall
t
TLH
2.0
--
--
75
--
95
ns
time
t
THL
4.5
--
5
15
--
19
6.0
--
--
13
--
16
Input capacitance
Cin
--
--
5
10
--
10
pF
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-14
Conforms
Conforms
0.97 g
Unit: mm
7.62
0.25
0
15
19.20
20.32 Max
1
8
14
7
1.30
2.54
0.25
0.48
0.10
6.30
7.40 Max
0.51 Min
2.54 Min
5.06 Max
+ 0.10
0.05
2.39 Max