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Электронный компонент: HD74HC4020

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HD74HC4020
14-stage Binary Counter
Description
The HD74HC4020 is a 14 stage counter. This device is incremented on the falling edge (negative
transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset
input.
Features
High Speed Operation: t
pd
(Clock to Q
1
) = 14 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 A max
Low Quiescent Supply Current: I
CC
(static) = 4 A max (Ta = 25C)
Function Table
Clock
Reset
Outputs State
L
No change
L
Advance to next state
X
H
All output are low
HD74HC4020
2
Pin Arrangement
1
2
3
4
5
6
7
8
Q
12
Q
13
Q
14
Q
6
Q
5
Q
7
Q
4
GND
Q
13
Q
14
Q
6
Q
5
Q
7
Q
4
Q
11
Q
10
Q
8
Q
9
R
C
Q
1
Q
12
V
CC
Q
11
Q
10
Q
8
Q
9
Reset
Clock
Q
1
16
15
14
13
12
11
10
9
(Top view)
Block Diagram
C
Reset
Clock
R
Q
C
Q
C
R
Q
C
Q
C
R
Q
C
Q
C
R
Q
C
Q
C
R
Q
C
Q
C
R
Q
C
Q
Q
1
Q
4
Q
5
Q
12
Q
13
Q
14
HD74HC4020
3
Timing Diagram
Clock
Reset
Q
1
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
Q
10
Q
11
Q
12
Q
13
Q
14
1
2
4
8
16
32
64
128
256
512
1,024
2,048
4,096
8,192 16,384
HD74HC4020
4
DC Characteristics
Ta = 25
C
Ta = 40 to
+85
C
Item
Symbol
V
CC
(V) Min Typ Max Min
Max
Unit
Test Conditions
Input voltage
V
IH
2.0
1.5
--
--
1.5
--
V
4.5
3.15 --
--
3.15
--
6.0
4.2
--
--
4.2
--
V
IL
2.0
--
--
0.5
--
0.5
V
4.5
--
--
1.35 --
1.35
6.0
--
--
1.8
--
1.8
Output voltage
V
OH
2.0
1.9
2.0
--
1.9
--
V
Vin = V
IH
or V
IL
I
OH
= 20
A
4.5
4.4
4.5
--
4.4
--
6.0
5.9
6.0
--
5.9
--
4.5
4.18 --
--
4.13
--
I
OH
= 4 mA
6.0
5.68 --
--
5.63
--
I
OH
= 5.2 mA
V
OL
2.0
--
0.0
0.1
--
0.1
V
Vin = V
IH
or V
IL
I
OL
= 20
A
4.5
--
0.0
0.1
--
0.1
6.0
--
0.0
0.1
--
0.1
4.5
--
--
0.26 --
0.33
I
OL
= 4 mA
6.0
--
--
0.26 --
0.33
I
OL
= 5.2 mA
Input current
Iin
6.0
--
--
0.1 --
1.0
A
Vin = V
CC
or GND
Quiescent supply
current
I
CC
6.0
--
--
4.0
--
40
A
Vin = V
CC
or GND, Iout = 0
A
HD74HC4020
5
AC Characteristics (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Ta = 25
C
Ta = 40 to
+85
C
Item
Symbol
V
CC
(V) Min Typ Max Min
Max
Unit
Test Conditions
Maximum clock
f
max
2.0
--
--
5
--
4
MHz
frequency
4.5
--
--
25
--
20
6.0
--
--
29
--
24
Propagation delay t
PLH
2.0
--
--
175 --
220
ns
Clock to Q
1
time
t
PHL
4.5
--
14
35
--
44
6.0
--
--
30
--
37
t
PLH
2.0
--
--
175 --
220
ns
Clock to Q
1
t
PHL
4.5
--
14
35
--
44
6.0
--
--
30
--
37
t
PLH
2.0
--
--
200 --
250
ns
Reset to output
t
PHL
4.5
--
18
40
--
50
6.0
--
--
34
--
43
t
PLH
2.0
--
--
100 --
125
ns
Q
n
to Q
n 1
t
PHL
4.5
--
--
20
--
25
6.0
--
--
17
--
21
Removal time
t
rem
2.0
100 --
--
125
--
ns
4.5
20
6
--
25
--
6.0
17
--
--
21
--
Pulse width
t
w
2.0
80
--
--
100
--
ns
4.5
16
4
--
20
--
6.0
14
--
--
17
--
Output rise/fall
t
TLH
2.0
--
--
75
--
95
ns
time
t
THL
4.5
--
5
15
--
19
6.0
--
--
13
--
16
Input capacitance
Cin
--
--
5
10
--
10
pF