HD74HCT563/HD74HCT573
Octal Transparent Latches (with 3-state outputs)
Description
When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D
inputs and the Q outputs of HD74HCT573 will follow the D inputs.
When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enabled
returns high again. When a high logic level is applied to the output control input, all outputs go to a high
impedance state, regardless of what signals are present at the other inputs and the state of the storage
elements.
Features
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: t
pd
(D to Q,
Q) = 13 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: V
CC
= 4.5 to 5.5 V
Low Input Current: 1 A max
Low Quiescent Supply Current: I
CC
(static) = 4 A max (Ta = 25C)
Function Table
Outputs
Output Control
Latch Enable
Data
HD74HCT563
HD74HCT573
L
H
H
L
H
L
H
L
H
L
L
L
X
Q
0
Q
0
H
X
X
Z
Z
PDF 
ZIP
