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Электронный компонент: HD74LV166A

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HD74LV166A
Parallel-Load 8-bit Shift Register
ADE-205-268 (Z)
1st Edition
March 1999
Description
The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the
register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded
asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge
of either clock inhibit or Clock. Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating
one of the clock inputs to act as a clock inhibit.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25
C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25
C)
Output current
6 mA (@V
CC
= 3.0 V to 3.6 V),
12 mA (@V
CC
= 4.5 V to 5.5 V)
HD74LV166A
2
Function Table
Inputs
Internal outputs
Output
CLR
SH/
LD
CLK INH
CLK
SER
A ... H
QA
QB
QH
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
Q
A0
Q
B0
Q
H0
H
L
L
X
a ... h
a
b
h
H
H
L
H
X
H
Q
An
Q
Gn
H
H
L
L
X
L
Q
An
Q
Gn
H
X
H
X
X
Q
A0
Q
B0
Q
H0
Note:
H: High level
L: Low level
: Low to high transition
X: Immaterial
a ... h:
Parallel data
Q
A0
... Q
H0
: Outputs remain unchanged.
Q
An
... Q
Gn
: Data shifted from the previous stage on a positive edge at the clock input.
Pin Arrangement
13
14
11
12
15
16
9
10
V
CC
SH/
LD
H
QH
G
F
1
2
3
4
5
6
7
8
SER
A
B
C
D
CLK INH
CLK
GND
E
CLR
(Top view)
HD74LV166A
3
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage range
V
CC
0.5 to 7.0
V
Input voltage range*
1
V
I
0.5 to 7.0
V
Output voltage range*
1, 2
V
O
0.5 to V
CC
+ 0.5
V
Output: H or L
0.5 to 7.0
V
CC
: OFF
Input clamp current
I
IK
20
mA
V
I
< 0
Output clamp current
I
OK
50
mA
V
O
< 0 or V
O
> V
CC
Continuous output current
I
O
25
mA
V
O
= 0 to V
CC
Continuous current through
V
CC
or GND
I
CC
or I
GND
50
mA
Maximum power dissipation
at Ta = 25
C (in still air)*
3
P
T
785
mW
SOP
500
TSSOP
Storage temperature
Tstg
65 to 150
C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150
C.
HD74LV166A
4
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Conditions
Supply voltage range
V
CC
2.0
5.5
V
Input voltage range
V
I
0
5.5
V
Output voltage range
V
O
0
V
CC
V
H or L
Output current
I
OH
--
50
A
V
CC
= 2.0 V
--
2
mA
V
CC
= 2.3 to 2.7 V
--
6
V
CC
= 3.0 to 3.6 V
--
12
V
CC
= 4.5 to 5.5 V
I
OL
--
50
A
V
CC
= 2.0 V
--
2
mA
V
CC
= 2.3 to 2.7 V
--
6
V
CC
= 3.0 to 3.6 V
--
12
V
CC
= 4.5 to 5.5 V
Input transition rise or fall rate
t /
v
0
200
ns/V
V
CC
= 2.3 to 2.7 V
0
100
V
CC
= 3.0 to 3.6 V
0
20
V
CC
= 4.5 to 5.5 V
Operating free-air temperature
Ta
40
85
C
Note:
Unused or floating inputs must be held high or low.
HD74LV166A
5
Logic Diagram
R CP S
C
D
Q
R CP S
C
D
Q
QH
A
C
B
D
E
F
CLR
SH/
LD
G
H
CLK CLK INH
SER