HM538123B Series
1 M VRAM (128-kword
8-bit)
ADE-203-231D (Z)
Rev. 4.0
Nov. 1997
Description
The HM538123B is a 1-Mbit multiport video RAM equipped with a 128-kword
8-bit dynamic RAM and a
256-word
8-bit SAM (serial access memory). Its RAM and SAM operate independently and
asynchronously. It can transfer data between RAM and SAM. In addition, it has two modes to realize fast
writing in RAM. Block write and flash write modes clear the data of 4-word
8-bit and the data of one row
(256-word
8-bit) respectively in one cycle of RAM. And the HM538123B makes split transfer cycle
possible by dividing SAM into two split buffers equipped with 128-word
8-bit each. This cycle can
transfer data to SAM which is not active, and enables a continuous serial access.
Features
Multiport organization
Asynchronous and simultaneous operation of RAM and SAM capability
RAM: 128-kword
8-bit and
SAM: 256-word
8-bit
Access time
RAM: 60 ns/70 ns/80 ns/100 ns max
SAM: 20 ns/22 ns/25 ns/25 ns max
Cycle time
RAM: 125 ns/135 ns/150 ns/180 ns min
SAM: 25 ns/25 ns/30 ns/30 ns min
Low power
Active
RAM: 413 mW max
SAM: 275 mW max
Standby
38.5 mW max
High-speed page mode capability
Mask write mode capability
Bidirectional data transfer cycle between RAM and SAM capability
Split transfer cycle capability
Block write mode capability
Flash write mode capability
HM538123B Series
2
3 variations of refresh (8 ms/512 cycles)
5$6-only refresh
&$6-before-5$6 refresh
Hidden refresh
TTL compatible
Ordering Information
Type No.
Access Time
Package
HM538123BJ-6
HM538123BJ-7
HM538123BJ-8
HM538123BJ-10
60 ns
70 ns
80 ns
100 ns
400-mil 40-pin plastic SOJ (CP-40D)
HM538123B Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SI/O7
SI/O6
SI/O5
SI/O4
SE
I/O7
I/O6
I/O5
I/O4
V
DSF
NC
CAS
QSF
A0
A1
A2
A3
A7
SC
SI/O0
SI/O1
SI/O2
SI/O3
DT/OE
I/O0
I/O1
I/O2
I/O3
V
WE
NC
RAS
NC
A8
A6
A5
A4
V
CC
CC
SS
SS
(Top View)
HM538123BJ Series
Pin Description
Pin Name
Function
A0 A8
Address inputs
I/O0 I/O7
RAM port data inputs/outputs
SI/O0 SI/O7
SAM port data inputs/outputs
5$6
Row address strobe
&$6
Column address strobe
:(
Write enable
'7
/
2(
Data transfer/Output enable
SC
Serial clock
6(
SAM port enable
DSF
Special function input flag
QSF
Special function output flag
V
CC
Power supply
V
SS
Ground
NC
No connection
HM538123B Series
4
Block Diagram
A0 A8
A0 A7
A0 A8
SI/O0 SI/O7
I/O0 I/O7
RAS
CAS
DT/OE
WE
DSF
SC
SE
Timing Generator
Output
Buffer
Input
Buffer
Mask
Register
Input Data
Control
Serial Output
Buffer
Serial Input
Buffer
Column Decoder
Sense Amplifier & I/O Bus
SAM I/O Bus
SAM Column Decoder
Data
Register
Serial Address
Counter
Refresh
Counter
Row Address
Buffer
Column Address
Buffer
Row Decoder
Memory Array
Data
Register
Transfer
Gate
Transfer
Gate
0
255
511
0
Flash Write
Control
Block Write
Control
Color
Resister
Address Mask
Register
QSF
HM538123B Series
5
Pin Functions
5$6
5$6 (input pin): 5$6 is a basic RAM signal. It is active in low level and standby in high level. Row
address and signals as shown in table 1 are input at the falling edge of
5$6. The input level of these signals
determine the operation cycle of the HM538123B.
Table 1
Operation Cycles of the HM538123B
Input Level At The Falling Edge Of
5$6
5$6
&$6
&$6
'7
'7
/
2(
2( :(
:(
6(
6(
DSF
DSF At The Falling Edge Of
&$6
&$6
Operation Mode
L
X
X
X
X
--
CBR refresh
H
L
L
L
L
X
Write transfer
H
L
L
H
L
X
Pseudo transfer
H
L
L
X
H
X
Split write transfer
H
L
H
X
L
X
Read transfer
H
L
H
X
H
X
Split read transfer
H
H
L
X
L
L
Read/mask write
H
H
L
X
L
H
Mask block write
H
H
L
X
H
X
Flash write
H
H
H
X
L
L
Read/write
H
H
H
X
L
H
Block write
H
H
H
X
H
X
Color register read/write
Note: X; Don't care
&$6
&$6 (input pin): Column address and DSF signal are fetched into chip at the falling edge of &$6, which
determines the operation mode of HM538123B.
&$6 controls output impedance of I/O in RAM.
A0 A8 (input pins): Row address (AX0 AX8) is determined by A0 A8 level at the falling edge of
5$6. Column address (AY0 AY7) is determined by A0 A7 level at the falling edge of &$6. In transfer
cycles, row address is the address on the word line which transfers data with SAM data register, and column
address is the SAM start address after transfer.
:(
:( (input pin): :( pin has two functions at the falling edge of 5$6 and after. When :( is low at the
falling edge of
5$6, the HM538123B turns to mask write mode. According to the I/O level at the time,
write on each I/O can be masked. (
:( level at the falling edge of 5$6 is don't care in read cycle.) When
:( is high at the falling edge of 5$6, a normal write cycle is executed. After that, :( switches read/write
cycles as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by
:( level at
the falling edge of
5$6. When :( is low, data is transferred from SAM to RAM (data is written into
RAM), and when
:( is high, data is transferred from RAM to SAM (data is read from RAM).
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