HM628128D Series
1 M SRAM (128-kword
8-bit)
ADE-203-996 (Z)
Preliminary, Rev. 0.0
Jan. 20, 1999
Description
The Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword
8-bit. HM628128D
Series has realized higher density, higher performance and low power consumption by employing Hi-
CMOS process technology. The HM628128D Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP,
standard 32-pin plastic SOP and standard 32-pin plastic TSOPI.
Features
Single 5 V supply: 5 V
10%
Access time: 55 ns/70 ns (max)
Power dissipation
Active: 30 mW/MHz (typ)
Standby: 10
W (typ)
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output
Three state output
Directly TTL compatible all inputs
Battery backup operation
2 chip selection for battery backup
HM628128D Series
2
Ordering Information
Type No.
Access time
Package
HM628128DLP-5
HM628128DLP-7
55 ns
70 ns
600-mil 32-pin plastic DIP (DP-32)
HM628128DLP-5SL
HM628128DLP-7SL
55 ns
70 ns
HM628128DLP-5UL
HM628128DLP-7UL
55 ns
70 ns
HM628128DLFP-5
HM628128DLFP-7
55 ns
70 ns
525-mil 32-pin plastic SOP (FP-32D)
HM628128DLFP-5SL
HM628128DLFP-7SL
55 ns
70 ns
HM628128DLFP-5UL
HM628128DLFP-7UL
55 ns
70 ns
HM628128DLTS-5
HM628128DLTS-7
55 ns
70 ns
8
13.4 mm 32-pin plastic TSOP I (TFP-32DC)
HM628128DLTS-5SL
HM628128DLTS-7SL
55 ns
70 ns
HM628128DLTS-5UL
HM628128DLTS-7UL
55 ns
70 ns
HM628128DLT-5
HM628128DLT-7
55 ns
70 ns
Normal-bend type 8
20 mm 32-pin plastic TSOP I (TFP-32D)
HM628128DLT-5SL
HM628128DLT-7SL
55 ns
70 ns
HM628128DLT-5UL
HM628128DLT-7UL
55 ns
70 ns
HM628128DLR-5
HM628128DLR-7
55 ns
70 ns
Reverse-bend type 8
20 mm 32-pin plastic TSOP I (TFP-32DR)
HM628128DLR-5SL
HM628128DLR-7SL
55 ns
70 ns
HM628128DLR-5UL
HM628128DLR-7UL
55 ns
70 ns
HM628128D Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CS2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
A3
(Top view)
32-pin TSOP (Normal Type TSOP)
32-pin DIP/SOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
WE
CS2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
32-pin TSOP (Reverse Type TSOP)
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
CC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
Pin Description
Pin name
Function
A0 to A16
Address input
I/O0 to I/O7
Data input/output
CS1
Chip select 1
CS2
Chip select 2
WE
Write enable
OE
Output enable
V
CC
Power supply
V
SS
Ground
NC
No connection
HM628128D Series
4
Block Diagram
I/O0
I/O7
WE
OE
A14 A16 A15
A8
A11
V
CC
V
SS
Row
decoder
Memory matrix
512 x 2,048
Column I/O
Column decoder
Input
data
control
Timing pulse generator
Read/Write control
A9
A12
A7
A6
A5
A4
A3
A2
A1
A0
A10
A13
MSB
LSB
MSB
LSB
CS1
CS2
HM628128D Series
5
Operation Table
CS1
CS2
WE
OE
I/O
Operation
H
H
High-Z
Standby
L
L
High-Z
Standby
L
L
High-Z
Standby
L
H
H
L
Dout
Read
L
H
L
H
Din
Write
L
H
L
L
Din
Write
L
H
H
H
High-Z
Output disable
Note:
H: V
IH
, L: V
IL
,
: V
IH
or V
IL
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage relative to V
SS
V
CC
0.5 to +7.0
V
Terminal voltage on any pin relative to V
SS
V
T
0.5*
1
to V
CC
+ 0.3*
2
V
Power dissipation
P
T
1.0
W
Storage temperature range
Tstg
55 to +125
C
Storage temperature range under bias
Tbias
20 to +85
C
Notes: 1. V
T
min: 1.5 V for pulse half-width
30 ns
2. Maximum voltage is +7.0 V
DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
CC
4.5
5.0
5.5
V
V
SS
0
0
0
V
Input high voltage
V
IH
2.2
--
V
CC
+ 0.3
V
Input low voltage
V
IL
0.3
--
0.8
V
1
Ambient temperature range
Ta
20
--
+70
C
Note:
1. V
IL
min: 1.5 V for pulse half-width
30 ns
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