HM62V8512C Series
4 M SRAM (512-kword
8-bit)
ADE-203-1210A (Z)
Rev. 1.0
Jan. 31, 2001
Description
The Hitachi HM62V8512C is a 4-Mbit static RAM organized 512-kword
8-bit. It realizes higher density,
higher performance and low power consumption by employing CMOS process technology (6-transistor
memory cell). The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is
available for high density mounting. The HM62V8512C is suitable for battery backup system.
Features
Single 3.0 V supply: 2.7 V to 3.6 V
Access time: 55/70 ns (max)
Power dissipation
Active: 6.0 mW/MHz (typ)
Standby: 2.4 W (typ)
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly LV-TTL compatible: All inputs
Battery backup operation
HM62V8512C Series
2
Ordering Information
Type No.
Access time
Package
HM62V8512CLFP-5
HM62V8512CLFP-7
55 ns
70 ns
525-mil 32-pin plastic SOP (FP-32D)
HM62V8512CLFP-5SL
HM62V8512CLFP-7SL
55 ns
70 ns
HM62V8512CLTT-5
HM62V8512CLTT-7
55 ns
70 ns
400-mil 32-pin plastic TSOP II (TTP-32D)
HM62V8512CLTT-5SL
HM62V8512CLTT-7SL
55 ns
70 ns
HM62V8512CLRR-5
HM62V8512CLRR-7
55 ns
70 ns
400-mil 32-pin plastic TSOP II reverse (TTP-32DR)
HM62V8512CLRR-5SL
HM62V8512CLRR-7SL
55 ns
70 ns
HM62V8512C Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
32-pin SOP
32-pin TSOP
32-pin TSOP (reverse)
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A18
Address input
I/O0 to I/O7
Data input/output
CS
Chip select
OE
Output enable
WE
Write enable
V
CC
Power supply
V
SS
Ground
HM62V8512C Series
4
Block Diagram
I/O0
I/O7
CS
WE
OE
A3 A2A1A0
A6
A5
V
V
CC
SS
Row
Decoder
Memory Matrix
2,048 2,048
Column I/O
Column Decoder
Input
Data
Control
Timing Pulse Generator
Read/Write Control
A4
A7
A11
A9
A8
A15
A18
A10
A13
A17
A16
A14
A12
LSB
MSB
LSB
MSB
HM62V8512C Series
5
Function Table
WE
CS
OE
Mode
V
CC
current
Dout pin
Ref. cycle
H
Not selected
I
SB
, I
SB1
High-Z
--
H
L
H
Output disable
I
CC
High-Z
--
H
L
L
Read
I
CC
Dout
Read cycle
L
L
H
Write
I
CC
Din
Write cycle (1)
L
L
L
Write
I
CC
Din
Write cycle (2)
Note:
: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage
V
CC
0.5 to +4.6
V
Voltage on any pin relative to V
SS
V
T
0.5*
1
to V
CC
+ 0.5*
2
V
Power dissipation
P
T
1.0
W
Operating temperature
Topr
20 to +70
C
Storage temperature
Tstg
55 to +125
C
Storage temperature under bias
Tbias
20 to +85
C
Notes: 1. V
T
min: 3.0 V for pulse half-width
30 ns.
2. Maximum voltage is 4.6 V.
Recommended DC Operating Conditions (Ta = 20 to +70C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
2.7
3.0
3.6
V
V
SS
0
0
0
V
Input high voltage
V
IH
2.0
--
V
CC
+ 0.3
V
Input low voltage
V
IL
0.3*
1
--
0.8
V
Note:
1. V
IL
min: 3.0 V for pulse half-width
30 ns.
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