Document Outline
- Description
- Features
- Ordering Information
- Pin Arrangement
- Pin Description
- Block Diagram
- Operation Table
- Absolute Maximum Ratings
- Recommended DC Operating Conditions
- DC Characteristics
- Capacitance
- AC Characteristics
- Timing Waveforms
- Read Timing Waveform (1) (WE = VIH )
- Read Timing Waveform (2) (WE = VIH , LB = VIL , UB, = VIL )
- Write Timing Waveform (1) (LB, UB Controlled)
- Write Timing Waveform (2) (WE Controlled)
- Write Timing Waveform (3) (CS Controlled)
- Low V CC Data Retention Characteristics
- Low VCC Data Retention Timing Waveform
- Package Dimensions
- HM62W16255HJP/HLJP Series (CP-44D)
- HM62W16255HTT/HLTT Series (TTP-44DE)
HM62W16255H Series
4M High Speed SRAM (256-kword
16-bit)
ADE-203-751D (Z)
Rev. 1.0
Sep. 15, 1998
Description
The HM62W16255H is a 4-Mbit high speed static RAM organized 256-kword
16-bit. It has realized high
speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed
circuit designing technology. It is most appropriate for the application which requires high speed, high
density memory and wide bit width configuration, such as cache and buffer memory in system. The
HM62W16255H is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density
surface mounting.
Features
Single 3.3 V supply: 3.3 V
0.3V
Access time: 12/15 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current: 180/160 mA (max)
TTL standby current: 60/50 mA (max)
CMOS standby current: 5 mA (max)
: 1mA (max) (L-version)
Data retension current: 0.6 mA (max) (L-version)
Data retension voltage: 2.0 V (min) (L-version)
Center V
CC
and V
SS
type pinout
HM62W16255H Series
2
Ordering Information
Type No.
Access time
Package
HM62W16255HJP-12
HM62W16255HJP-15
12 ns
15 ns
400-mil 44-pin plastic SOJ (CP-44D)
HM62W16255HLJP-12
HM62W16255HLJP-15
12 ns
15 ns
HM62W16255HTT-12
HM62W16255HTT-15
12 ns
15 ns
400-mil 44-pin plastic SOJ (TTP-44DE)
HM62W16255HLTT-12
HM62W16255HLTT-15
12 ns
15 ns
Pin Arrangement
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
HM62W16255HJP/HLJP Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HM62W16255HTT/HLTT Series
(Top View)
HM62W16255H Series
3
Pin Description
Pin name
Function
A0 to A17
Address input
I/O1 to I/O16
Data input/output
CS
Chip select
OE
Output enable
WE
Write enable
UB
Upper byte select
LB
Lower byte select
V
CC
Power supply
V
SS
Ground
NC
No connection
Block Diagram
Memory matrix
256 rows
8 columns
128 blocks
16 bit
(4,194,304 bits)
CS
V
CC
V
SS
A10 A8 A9 A12 A13 A14 A0 A15 A3 A4
Column I/O
Column decoder
I/O1
WE
Input
data
control
Row
decoder
OE
CS
CS
CS
LB
UB
I/O16
I/O9
I/O8
.
.
.
.
.
.
A1
A17
A7
A11
A16
A2
A6
A5
(LSB)
(MSB)
HM62W16255H Series
4
Operation Table
CS
OE
WE LB
UB
Mode
V
CC
current
I/O1I/O8
I/O9I/O16
Ref. cycle
H
Standby
I
SB
, I
SB1
High-Z
High-Z
--
L
H
H
Output disable
I
CC
High-Z
High-Z
--
L
L
H
L
L
Read
I
CC
Output
Output
Read cycle
L
L
H
L
H
Lower byte read I
CC
Output
High-Z
Read cycle
L
L
H
H
L
Upper byte read I
CC
High-Z
Output
Read cycle
L
L
H
H
H
--
I
CC
High-Z
High-Z
--
L
L
L
L
Write
I
CC
Input
Input
Write cycle
L
L
L
H
Lower byte write I
CC
Input
High-Z
Write cycle
L
L
H
L
Upper byte write I
CC
High-Z
Input
Write cycle
L
L
H
H
--
I
CC
High-Z
High-Z
--
Note:
: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply voltage relative to V
SS
V
CC
0.5 to +4.6
V
Voltage on any pin relative to V
SS
V
T
0.5*
1
to V
CC
+ 0.5*
2
V
Power dissipation
P
T
1.0
W
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
55 to +125
C
Storage temperature under bias
Tbias
10 to +85
C
Notes: 1. V
T
(min) = 2.0 V for pulse width (under shoot)
8 ns
2. V
T
(max) = V
CC
+ 2.0 V for pulse width (over shoot)
8 ns
HM62W16255H Series
5
Recommended DC Operating Conditions (Ta = 0 to +70
C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
*
3
3.0
3.3
3.6
V
V
SS
*
4
0
0
0
V
Input voltage
V
IH
2.2
--
V
CC
+ 0.5*
2
V
V
IL
0.5*
1
--
0.8
V
Notes: 1. V
IL
(min) = 2.0 V for pulse width (under shoot)
8 ns
2. V
IH
(max) = V
CC
+ 2.0 V for pulse width (over shoot)
8 ns
3. The supply voltage with all V
CC
pins must be on the same level.
4. The supply voltage with all V
SS
pins must be on the same level.
DC Characteristics (Ta = 0 to +70
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V)
Parameter
Symbol Min
Typ*
1
Max
Unit
Test conditions
Input leakage current
|I
LI
|
--
--
2
A
Vin = V
SS
to V
CC
Output leakage
current*
1
|I
LO
|
--
--
2
A
Vin = V
SS
to V
CC
Operating power
supply current
12 ns cycle I
CC
--
--
180
mA
Min cycle
CS
= V
IL
, Iout = 0 mA
Other inputs = V
IH
/V
IL
15 ns cycle I
CC
--
--
160
Standby power supply
current
12 ns cycle I
SB
--
--
60
mA
Min cycle,
CS
= V
IH
,
Other inputs = V
IH
/V
IL
15 ns cycle I
SB
--
--
50
I
SB1
--
0.05
5
mA
f = 0 MHz
V
CC
CS
V
CC
0.2 V,
(1) 0 V
Vin
0.2 V or
(2) V
CC
Vin
V
CC
0.2 V
--*
2
0.05*
2
1.0*
2
Output voltage
V
OL
--
--
0.4
V
I
OL
= 8 mA
V
OH
2.4
--
--
V
I
OH
= 4 mA
Note:
1. Typical values are at V
CC
= 3.3 V, Ta = +25
C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
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