HN58C65 Series

8192-word

8-bit Electrically Erasable and Programmable CMOS

ROM

ADE-203-374A (Z)

Rev. 1.0

Apr. 12, 1995

Description

The Hitachi HN58C65 is a electrically erasable and programmable ROM organized as 8192-word

8-bit. It

realizes high speed, low power consumption, and a high level of reliability, employing advanced MNOS
memory technology and CMOS process and circuitry technology. It also has a 32-byte page programming
function to make its erase and write operations faster.

Features

Single 5 V Supply

On chip latches: address, data, CE, OE, WE

Automatic byte write: 10 ms max

Automatic page write (32 byte): 10 ms max

Fast access time: 250 ns max

Low power dissipation: 20 mW/MHz typ (Active)

2.0 mW typ (Standby)

Data polling and Ready/Busy

Data protection circuity on power on/power off

Conforms to JEDEC byte-wide standard

Reliable CMOS with MNOS cell technology

erase/write cycles (in page mode)

10 year data retention

Ordering Information

Type No.

Access Time

Package

HN58C65P-25

250 ns

600 mil 28 pin plastic DIP (DP-28)

HN58C65FP-25

250 ns

28 pin plastic SOP

(FP-28D/DA)

Note:

1. T is added to the end of the type no. for a SOP of 3.0 mm (max) thickness.

HN58C65 Series

Pin Arrangement

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

RDY/Busy

A12
A7
A6
A5
A4
A3
A2
A1
A0

I/O0
I/O1
I/O2

(Top View)

HN58C65P/FP Series

Pin Description

Pin Name

Function

A0 A12

Address input

I/O1 I/O7

Data input/output

Output enable

Chip enable

Write enable

Power (+5 V)

Ground

No connection

RDY/

Busy

Ready/

Busy

HN58C65 Series

Block Diagram

A12

I/O0

I/O7

High Voltage Generator

Control Logic and Timing

Y Decoder

X Decoder

Address

Buffer and

Latch

I/O Buffer

and

Input Latch

Y Gating

Memory Array

Data Latch

RDY/Busy

Mode Selection

Pin Mode

RDY/

Busy

I/O

Read

High-Z

Dout

Standby

High-Z

Write

High-Z to V

Din

Deselect

High-Z

Write inhibit

High-Z

Data

polling

Data out (I/O7)

Note:

1. X = Don't care

HN58C65 Series

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

Supply voltage

0.6 to +7.0

Input voltage

Vin

0.5

to +7.0

Operating temperature range

Topr

0 to +70

Storage temperature range

Tstg

55 to +125

Notes: 1. With respect to V

2. 3.0 V for pulse width

50 ns.

3. Including electrical characteristics and data retention.

Recommended DC Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

4.5

5.0

5.5

Input voltage

0.3

0.8

2.2

+ 1

Operating temperature

Topr

HN58C65 Series

DC Characteristics (Ta = 0 to +70

C, V

= 5 V

10%)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Input leakage current

= 5.5 V

Vin = 5.5 V

Output leakage current

= 5.5 V

Vout = 5.5/0.4 V

current (Standby)

CC1

= V

current (Active)

CC2

Iout = 0 mA
Duty = 100%
Cycle = 1

s at

= 5.5 V

Iout = 0 mA
Duty = 100%
Cycle = 250 ns at
V

= 5.5 V

Input low voltage

0.3

0.8

Input high voltage

2.2

+ 1

Output low voltage

0.4

= 2.1 mA

Output high voltage

2.4

= 400

Note:

1. 1.0 V for pulse width

50 ns

Capacitance (Ta = 25

C, f = 1 MHz)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Input capacitance

Cin

Vin = 0 V

Output capacitance

Cout

Vout = 0 V

Note:

1. This parameter is periodically sampled and not 100% tested.

AC Characteristics (Ta = 0 to +70

C, V

= 5 V

10%)

Test Conditions

Input pulse levels: 0.4 V to 2.4 V

Input rise and fall time:

20 ns

Output load: 1TTL gate + 100 pF

Reference levels for measuring timing: 0.8 V and 2 V

HN58C65 Series

Read Cycle

Parameter

Symbol

Min

Max

Unit

Test Conditions

Address to output delay

ACC

250

= V

to output delay

250

= V

to output delay

100

= V

Address to output hold

= V

OE, CE

high to output float

= V

Note:

1. t

is defined at which the outputs archieve the open circuit conditions and are no longer driven.

Read Timing Waveform

Address

Data Out

High

Data Out Valid

ACC

HN58C65 Series

Write Cycle

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Address setup time

Address hold time

150

to write setup time (

controlled)

hold time (

controlled)

to write setup time (

controlled)

hold time (

controlled)

to write setup time

OES

hold time

OEH

Data setup time

100

Data hold time

pulse width (

controlled)

200

pulse width (

controlled)

200

Data latch time

100

Byte lode cycle

BLC

0.30

Byte lode window

100

Write cycle time

Time to devce busy

120

Write start time

150

Notes: 1. Use this device in longer cycle than this value.

2. t

must be longer than this value unless polling technique is used. This device automatically

completes the internal write operation within this value.

HN58C65 Series

Data Polling Timing Waveform

OES

Address

I/O7

Din X

Dout

Dout X

Functional Description

Automatic Page Write

Page-mode write feature allows 1 to 32 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 31 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30

s of the preceding rising edge of the WE. When CE or

WE is high for 100

s after data input, the EEPROM enters write mode automatically and the input data are

written into the EEPROM.

Data Polling

Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a
write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM
is performing a write operation.

RDY/Busy Signal

RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high
impedance, except in write cycle and is lowered to V

after the first write signal. At the end of a write cycle,

the RDY/Busy signal changes state to high impedance.

HN58C65 Series

WE, CE Pin Operation

During a write cycle, addresses are latched by the falling edge of WE or CE and data is latched by the rising
edge of WE or CE.

Write/Erase Endurance and Data Retention Time

The endurance is 10

cycles in case of the page programming and 3

cycles in case of byte programming

(1% cumulative failure rate). The data retention time is more than 10 years when a device is page-
programmed less than 10

cycles.

Data Protection

1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation

During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to progam
mode by mistake. To prevent this phenomenon, this device has a noise cancelation function that cuts
noise if its width is 20 ns or less in program mode. Be careful not to allow noise of a width of more than
20 ns on the control pins.

WE
CE

5 V

0 V

5 V

0 V

20 ns max

HN58C65 Series

2. Data Protection at V

On/Off

When V

is turned on or off, noise on the control pins generated by external circuits (CPU, etc.) may act

as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.

CPU
RESET

Unprogrammable

*The EEPROM should be kept in unprogrammable
state during V

on/off by using CPU RESET signal.

In addition, when V

is turned on or off, the input level of on control pins must be held as shown in the

table below.

X: Don't care.

: Pull-up to V

level

: Pull-down to V

level.

HN58C65 Series

Package Dimensions

HN58C65P series (DP-28)

Unit: mm

0.51 Min

2.54 Min

0.25

+ 0.11
0.05

2.54 ± 0.25

0.48 ± 0.10

0° 15°

15.24

1.20

35.60

36.50 Max

13.40

14.60 Max

5.70 Max

1.90 Max

HN58C65FP Series (FP-28D)

Unit: mm

0 10 °

+ 0.08

0.07

0.17

1.00 ± 0.20

0.20 ± 0.10

2.50 Max

1.27

0.40

+ 0.10
0.05

8.40

18.30

18.75 Max

1.12 Max

11.80 ± 0.30

0.20

0.15

1.70

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