Rev.2.00, May.25.2004, page 1 of 12
R1LV0408C-I Series
Wide Temperature Range Version
4M SRAM (512-kword
8-bit)
REJ03C0098-0200Z
Rev. 2.00
May.25.2004
Description
The R1LV0408C-I is a 4-Mbit static RAM organized 512-kword
8-bit. R1LV0408C-I Series has
realized higher density, higher performance and low power consumption by employing CMOS process
technology (6-transistor memory cell). The R1LV0408C-I Series offers low power standby power
dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin
TSOP II and 32-pin STSOP.
Features
Single 3 V supply: 2.7 V to 3.6 V
Access time: 55/70 ns (max)
Power dissipation:
Active: 6 mW/MHz (typ)
Standby: 1.5 W (typ)
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
Directly TTL compatible.
All inputs and outputs
Battery backup operation.
Operating temperature: -40 to +85C
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 2 of 12
Ordering Information
Type No.
Access time
Package
R1LV0408CSP-5SI
55 ns
525-mil 32-pin plastic SOP (32P2M-A)
R1LV0408CSP-7LI 70
ns
R1LV0408CSB-5SI
55 ns
400-mil 32-pin plastic TSOP II (32P3Y-H)
R1LV0408CSB-7LI 70
ns
R1LV0408CSA-5SI 55
ns
8mm
13.4mm STSOP (32P3K-B)
R1LV0408CSA-7LI 70
ns
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 3 of 12
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CC
A11
A9
A8
A13
WE#
A18
A15
V
A17
A16
A14
A12
A7
A6
A5
A4
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
V
I/O2
I/O1
I/O0
A0
A1
A2
A3
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
CC
(Top view)
32-pin SOP
32-pin TSOP
32-pin STSOP
(Top view)
Pin Description
Pin name
Function
A0 to A18
Address input
I/O0 to I/O7
Data input/output
CS# (
CS
) Chip
select
OE# (
OE
) Output
enable
WE# (
WE
) Write
enable
V
CC
Power
supply
V
SS
Ground
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 4 of 12
Block Diagram
I/O0
I/O7
CS#
WE#
OE#
A3 A2A1A0
A6
A5
V
V
CC
SS
Row
Decoder
Memory Matrix
2,048 2,048
Column I/O
Column Decoder
Input
Data
Control
Timing Pulse Generator
Read/Write Control
A4
A7
A11
A9
A8
A15
A18
A10
A13
A17
A16
A14
A12
LSB
MSB
LSB
MSB
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 5 of 12
Operation Table
WE# CS# OE# Mode
V
CC
current
I/O0 to I/O7
Ref. cycle
H
Not
selected
I
SB
, I
SB1
High-Z
H L H Output
disable I
CC
High-Z
H L L Read
I
CC
Dout
Read
cycle
L L H Write
I
CC
Din
Write cycle (1)
L L L Write
I
CC
Din
Write cycle (2)
Note: H: V
IH
, L: V
IL
,
: V
IH
or V
IL
Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Power supply voltage relative to V
SS
V
CC
-
0.5 to +4.6
V
Terminal voltage on any pin relative to V
SS
V
T
-
0.5
*
1
to V
CC
+ 0.5
*
2
V
Power dissipation
P
T
0.7
W
Operating temperature
Topr
-
40 to +85
C
Storage temperature range
Tstg
-
65 to +150
C
Storage temperature range under bias
Tbias
-
40 to +85
C
Notes: 1. V
T
min:
-
3.0 V for pulse half-width
30 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
(Ta =
-40 to +85C)
Parameter Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
2.7
3.0
3.6
V
V
SS
0 0
0
V
Input high voltage
V
IH
2.2
V
CC
+ 0.3
V
Input low voltage
V
IL
-
0.3
*
1
0.6 V
Note: 1. V
IL
min:
-
3.0 V for pulse half-width
30 ns.
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 6 of 12
DC Characteristics
Parameter Symbol Min
Typ
Max Unit Test
conditions
Input leakage current
|I
LI
|
1
A Vin = V
SS
to V
CC
Output leakage current
|I
LO
|
1
A CS# = V
IH
or OE# = V
IH
or
WE# = V
IL
or V
I/O
= V
SS
to V
CC
Operating current
I
CC
5
*
1
10
mA CS# = V
IL
,
Others = V
IH
/ V
IL
, I
I/O
= 0 mA
Average operating current
I
CC1
8
*
1
25
mA Min. cycle, duty = 100%,
CS# = V
IL
, Others = V
IH
/V
IL
I
I/O
= 0 mA
I
CC2
2
*
1
5
mA Cycle time = 1
s,
duty = 100%,
I
I/O
= 0 mA, CS#
0.2 V,
V
IH
V
CC
-
0.2 V, V
IL
0.2 V
Standby current
I
SB
0.1
*
1
0.3 mA CS# = V
IH
to +85
C I
SB1
10
A Vin
0 V, CS#
V
CC
-
0.2 V
to +70
C I
SB1
8
A
to +40
C I
SB1
0.7
*
2
3
A
-
5SI
to +25
C I
SB1
0.5
*
1
3
A
to +85
C I
SB1
20
A
to +70
C I
SB1
16
A
to +40
C I
SB1
0.7
*
2
10
A
Standby
current
-
7LI
to +25
C I
SB1
0.5
*
1
10
A
Output low voltage
V
OL
0.4
V I
OL
= 2.1 mA
V
OL2
0.2
V I
OL
= 100
A
Output high voltage
V
OH
2.4
V I
OH
=
-
1.0 mA
V
OH2
V
CC
-
0.2
V I
OH
=
-
0.1 mA
Notes: 1. Typical values are at V
CC
= 3.0 V, Ta = +25
C and specified loading, and not guaranteed.
2. Typical values are at V
CC
= 3.0 V, Ta = +40
C and specified loading, and not guaranteed.
Capacitance
(Ta = +25
C, f = 1.0 MHz)
Parameter Symbol
Min
Typ
Max
Unit
Test
conditions
Note
Input capacitance
Cin
8
pF
Vin = 0 V
1
Input/output capacitance
C
I/O
10 pF V
I/O
= 0 V
1
Note: 1. This parameter is sampled and not 100% tested.
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 7 of 12
AC Characteristics
(Ta =
-40 to +85C, V
CC
= 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
Input pulse levels: V
IL
= 0.4 V, V
IH
= 2.4 V
Input rise and fall time: 5 ns
Input and output timing reference levels: 1.5 V
Output load: 1 TTL Gate + C
L
(50 pF) (R1LV0408C-5SI)
1 TTL Gate + C
L
(100 pF) (R1LV0408C-7LI)
(Including scope and jig)
Read Cycle
R1LV0408C-I
-5SI
-7LI
Parameter
Symbol Min Max Min Max Unit Notes
Read cycle time
t
RC
55
70
ns
Address access time
t
AA
55
70 ns
Chip select access time
t
CO
55
70 ns
Output enable to output valid
t
OE
30
35 ns
Chip select to output in low-Z
t
LZ
10
10
ns 2
Output enable to output in low-Z
t
OLZ
5
5
ns 2
Chip deselect to output in high-Z
t
HZ
0 20 0 25 ns 1,
2
Output disable to output in high-Z
t
OHZ
0 20 0 25 ns 1,
2
Output hold from address change
t
OH
10
10
ns
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 8 of 12
Write Cycle
R1LV0408C-I
-5SI
-7LI
Parameter
Symbol
Min Max Min Max Unit Notes
Write cycle time
t
WC
55
70
ns
Chip selection to end of write
t
CW
50
60
ns 4
Address setup time
t
AS
0
0
ns 5
Address valid to end of write
t
AW
50
60
ns
Write pulse width
t
WP
40
50
ns 3,
12
Write recovery time
t
WR
0
0
ns 6
Write to output in high-Z
t
WHZ
0 20 0 25
ns 1,
2,
7
Data to write time overlap
t
DW
25
30
ns
Data hold from write time
t
DH
0
0
ns
Output active from end of write
t
OW
5
5
ns 2
Output disable to output in high-Z
t
OHZ
0 20 0 25
ns 1,
2,
7
Notes: 1. t
HZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
WP
) of a low CS# and a low WE#. A write begins at the later
transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going
high or WE# going high. t
WP
is measured from the beginning of write to the end of write.
4.
t
CW
is measured from CS# going low to the end of write.
5.
t
AS
is measured from the address valid to the beginning of write.
6.
t
WR
is measured from the earlier of WE# or CS# going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE# low fixed, t
WP
must satisfy the following equation to avoid a problem of
data bus contention. t
WP
t
DW
min + t
WHZ
max
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 9 of 12
Timing Waveform
Read Timing Waveform (WE# = V
IH
)
t
AA
t
CO
t
RC
t
LZ
t
OE
t
OLZ
t
HZ
t
OHZ
Valid data
Valid address
High impedance
Address
CS#
OE#
Dout
t
OH
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 10 of 12
Write Timing Waveform (1) (OE# Clock)
t
WC
t
CW
t
WP
t
AS
t
OHZ
t
DW
t
DH
t
AW
t
WR
*8
Address
OE#
CS#
WE#
Dout
Din
Valid data
Valid address
High impedance
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 11 of 12
Write Timing Waveform (2) (OE# Low Fixed)
Address
CS#
WE#
Dout
Din
t
WC
t
CW
t
WR
t
AW
t
WP
t
AS
t
WHZ
t
OW
t
OH
t
DW
t
DH
*11
*9
*10
*8
Valid data
Valid address
High impedance
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 12 of 12
Low V
CC
Data Retention Characteristics
(Ta =
-40 to +85C)
Parameter Symbol
Min Typ
Max Unit Test
conditions
*
3
V
CC
for data retention
V
DR
2.0
V CS#
V
CC
-
0.2 V, Vin
0 V
to +85
C I
CCDR
10
A V
CC
= 3.0 V, Vin
0 V
to +70
C I
CCDR
8
A CS#
V
CC
-
0.2 V
to +40
C
I
CCDR
0.7
*
2
3
A
-
5SI
to +25
C I
CCDR
0.5
*
1
3
A
to +85
C I
CCDR
20
A
to +70
C I
CCDR
16
A
to +40
C
I
CCDR
0.7
*
2
10
A
Data
retention
current
-
7LI
to +25
C I
CCDR
0.5
*
1
10
A
Chip deselect to data retention time
t
CDR
0
ns
See retention waveform
Operation recovery time
t
R
t
RC
*
4
ns
Notes: 1. Typical values are at V
CC
= 3.0 V, Ta = +25
C and specified loading, and not guaranteed.
2. Typical values are at V
CC
= 3.0 V, Ta = +40
C and specified loading, and not guaranteed.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4.
t
RC
= read cycle time.
Low V
CC
Data Retention Timing Waveform (CS# Controlled)
V
CC
2.7 V
2.2 V
0 V
CS#
t
CDR
t
R
CS#
V
CC
0.2 V
V
DR
Data retention mode
Revision History
R1LV0408C-I Series Data Sheet
Contents of Modification
Rev. Date
Page Description
1.00 Jul.24.2003
Initial
issue
2.00 May.25.2004 1
5
6
12
12
Features
Standby: 2.4
W (typ) to 1.5
W (typ)
Absolute Maximum Ratings
Notes 2 : +7.0 V to +4.6 V
DC characteristics
-
5SI and
-
7LI items' description are divided.
Low V
CC
Data Retention Characteristics
-
5SI and
-
7LI items' description are divided.
Low V
CC
Data Retention Timing Waveform
4.5 V to 2.7 V
2.4 V to 2.2 V
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