HT48R50A-1/HT48C50-1
I/O Type 8-Bit MCU
Rev. 2.00
1
March 8, 2006
General Description
The HT48R50A-1/HT48C50-1 are 8-bit high perfor-
mance, RISC architecture microcontroller devices spe-
cifically designed for multiple I/O control product
applications. The mask version HT48C50-1 is fully pin
and functionally compatible with the OTP version
HT48R50A-1 device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Features
Operating voltage:
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
Low voltage reset function
35 bidirectional I/O lines (max.)
1 interrupt input shared with an I/O line
8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler
16-bit programmable timer/event counter and over-
flow interrupts
On-chip RC oscillator, external crystal and RC oscil-
lator
32768Hz crystal oscillator for timing purposes only
Watchdog Timer
4096
15 program memory ROM
160
8 data memory RAM
Buzzer driving pair and PFD supported
HALT function and wake-up feature reduce power
consumption
6-level subroutine nesting
Up to 0.5
ms instruction cycle with 8MHz system clock
at V
DD
=5V
Bit manipulation instruction
15-bit table read instruction
63 powerful instructions
All instructions in one or two machine cycles
28-pin SKDIP/SOP, 48-pin SSOP package
Technical Document
Tools Information
FAQs
Application Note
-
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
-
HA0004E HT48 & HT46 MCU UART Software Implementation Method
-
HA0013E HT48 & HT46 LCM Interface Design
-
HA0021E Using the I/O Ports on the HT48 MCU Series
-
HA0055E 2^12 Decoder (8+4 - Corresponds to HT12E)
Block Diagram
HT48R50A-1/HT48C50-1
Rev. 2.00
2
March 8, 2006
I N T / P G 0
O S C 2 /
P G 2
O S C 1 /
P G 1
R E S
V D D
M U X
T M R 0
T M R 0 C
T M R 0
V S S
P r e s c a l e r
f
S Y S
P G 0
P r o g r a m
R O M
P r o g r a m
C o u n t e r
I n t e r r u p t
C i r c u i t
S T A C K
I N T C
D A T A
M e m o r y
I n s t r u c t i o n
R e g i s t e r
M
U
X
I n s t r u c t i o n
D e c o d e r
S T A T U S
A L U
S h i f t e r
T i m i n g
G e n e r a t o r
A C C
M
U
X
M P
W D T S
W D T
W D T O S C
W D T P r e s c a l e r
M
U
X
R T C O S C
E N / D I S
P G 1
P G 2
I n t e r n a l
R C O S C
P D C
P O R T D
P D 0 ~ P D 7
P G C
P G
P O R T G
P G 0 ~ P G 2
P B C
P O R T B
P B 0 ~ P B 7
B Z / B Z
P B
P A C
P O R T A
P A 0 ~ P A 7
P A
P D
P C
P O R T C
P C 0 ~ P C 7
P C C
M
U
X
f
S Y S
/ 4
T M R 1 C
T M R 1 L
T M R 1 H
M
U
X
M
U
X
T M R 1
f
S Y S
/ 4
Pin Assignment
Pin Description
Pin Name
I/O
Options
Description
PA0~PA7
I/O
Pull-high*
Wake-up
CMOS/Schmitt
trigger Input
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by options. Software instructions determine the CMOS out-
put or Schmitt trigger or CMOS input with pull-high resistor (determined by
pull-high option).
PB0/BZ
PB1/BZ
PB2~PB7
I/O
Pull-high*
I/O or BZ/BZ
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined by
pull-high option).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once
the PB0 and PB1 are selected as buzzer driving outputs, the output signals
come from an internal PFD generator (shared with Timer/Event Counter 0).
PD0~PD7
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output
or Schmitt trigger input with pull-high resistor (determined by pull-high op-
tion).
VSS
Negative power supply, ground
PG0/INT
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output
or Schmitt trigger input with pull-high resistor (determined by pull-high op-
tion). This external interrupt input is pin-shared with PG0. The external in-
terrupt input is activated on a high to low transition.
TMR0
I
Timer/Event Counter 0 Schmitt trigger input (without pull-high resistor)
PC0~PC7
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output
or Schmitt trigger input with pull-high resistor (determined by pull-high op-
tion).
TMR1
I
Timer/Event Counter 1 Schmitt trigger input (without pull-high resistor)
HT48R50A-1/HT48C50-1
Rev. 2.00
3
March 8, 2006
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2 / P G 2
O S C 1 / P G 1
V D D
R E S
P C 5 / T M R 1
P C 4
P C 3
P C 2
P B 5
P B 4
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 / B Z
P B 0 / B Z
V S S
P G 0 / I N T
P C 0 / T M R 0
P C 1
H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1 - A
2 8 S K D I P - A / S O P - A
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1 - A
4 8 S S O P - A
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
N C
N C
N C
N C
O S C 2 / P G 2
O S C 1 / P G 1
V D D
R E S
T M R 1
P D 3
P D 2
P D 1
P D 0
P C 7
P C 6
P C 5
P C 4
P C 3
P B 5
P B 4
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 / B Z
P B 0 / B Z
N C
N C
N C
N C
P D 7
P D 6
P D 5
P D 4
V S S
P G 0 / I N T
T M R 0
P C 0
P C 1
P C 2
Pin Name
I/O
Options
Description
RES
I
Schmitt trigger reset input. Active low
VDD
Positive power supply
OSC1/PG1
OSC2/PG2
I
O
Pull-high*
Crystal
or RC
or Int. RC+I/O
or Int. RC+RTC
OSC1, OSC2 are connected to an RC network or Crystal (determined by
option) for the internal system clock. In the case of RC operation, OSC2 is
the output terminal for 1/4 system clock. These two pins can also be
optioned as an RTC oscillator (32768Hz) or I/O lines. In these two cases,
the system clock comes from an internal RC oscillator whose frequency
has 4 options (3.2MHz, 1.6MHz, 800kHz, 400kHz). If the I/O option is se-
lected, the pull-high option can also be enabled or disabled. Otherwise the
PG1 and PG2 are used as internal registers (pull-high resistors are always
disabled).
Note: * The pull-high resistors of each I/O port (PA, PB, PC, PD, PG) are controlled by options.
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V to V
SS
+6.0V
Storage Temperature ............................
-50C to 125C
Input Voltage..............................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature...........................
-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
f
SYS
=4MHz
2.2
5.5
V
f
SYS
=8MHz
3.3
5.5
V
I
DD1
Operating Current
(Crystal OSC, RC OSC)
3V
No load, f
SYS
=4MHz
1
2
mA
5V
2.5
5
mA
I
DD23
Operating Current
(Crystal OSC, RC OSC)
5V
No load, f
SYS
=8MHz
4
8
mA
I
STB1
Standby Current
(WDT OSC Enabled RTC Off)
3V
No load, system HALT
5
mA
5V
10
mA
I
STB2
Standby Current
(WDT OSC Disabled RTC Off)
3V
No load, system HALT
1
mA
5V
2
mA
I
STB3
Standby Current
(WDT OSC Disabled, RTC On)
3V
No load, system HALT
5
mA
5V
10
mA
V
IL1
Input Low Voltage for I/O Ports
0
0.3V
DD
V
V
IH1
Input High Voltage for I/O Ports
0.7V
DD
V
DD
V
V
IL2
Input Low Voltage (RES)
0
0.4V
DD
V
V
IH2
Input High Voltage (RES)
0.9V
DD
V
DD
V
V
LVR
Low Voltage Reset
LVRenabled
2.7
3.0
3.3
V
I
OL
I/O Port Sink Current
3V
V
OL
=0.1V
DD
4
8
mA
5V
V
OL
=0.1V
DD
10
20
mA
HT48R50A-1/HT48C50-1
Rev. 2.00
4
March 8, 2006
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
I
OH
I/O Port Source Current
3V
V
OH
=0.9V
DD
-2
-4
mA
5V
V
OH
=0.9V
DD
-5
-10
mA
R
PH
Pull-high Resistance
3V
20
60
100
k
W
5V
10
30
50
k
W
A.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
f
SYS1
System Clock (Crystal OSC)
2.2V~5.5V
400
4000
kHz
3.3V~5.5V
400
8000
kHz
f
SYS2
System Clock (RC OSC)
2.2V~5.5V
400
4000
kHz
3.3V~5.5V
400
8000
kHz
f
SYS3
System Clock
(Internal RC OSC)
5V
3.2MHz
1800
5400
kHz
1.6MHz
900
2700
kHz
800kHz
450
1350
kHz
400kHz
225
675
kHz
f
TIMER
Timer I/P Frequency (TMR)
2.2V~5.5V
0
4000
kHz
3.3V~5.5V
0
8000
kHz
t
WDTOSC
Watchdog Oscillator Period
3V
45
90
180
ms
5V
32
65
130
ms
t
WDT1
Watchdog Time-out Period
(WDT OSC)
3V
Without WDT
prescaler
11
23
46
ms
5V
8
17
33
ms
t
WDT2
Watchdog Time-out Period
(System Clock)
Without WDT
prescaler
1024
*t
SYS
t
WDT3
Watchdog Time-out Period
(RTC OSC)
Without WDT
prescaler
7.812
ms
t
RES
External Reset Low Pulse
Width
1
ms
t
SST
System Start-up Timer Period
Wake-up from HALT
1024
t
SYS
t
INT
Interrupt Pulse Width
1
ms
Note: *t
SYS
= 1/f
SYS1
, 1/f
SYS2
or 1/f
SYS3
HT48R50A-1/HT48C50-1
Rev. 2.00
5
March 8, 2006
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