HT48R52/HT48R53
I/O Type 8-Bit MCU
Rev. 1.10
1
June 6, 2005
General Description
These devices are 8-bit high performance, RISC archi-
tecture microcontroller specifically designed for multiple
I/O control product applications. The advantages of low
power consumption, I/O flexibility, timer functions, oscil-
lator options, HALT and wake-up functions, watchdog
timer, buzzer driver, as well as low cost, enhance the
versatility of these devices to suit a wide range of appli-
cation possibilities such as industrial control, consumer
products, subsystem controllers, etc.
Features
Operating voltage:
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
Program memory:
HT48R52: 2k
14
HT48R53: 4k
15
88
8 data memory
40 bidirectional I/O lines
One External interrupt input
One Internal interrupt
8 bit programmable timer/event counter
4-level subroutine nesting
Watchdog Timer (WDT)
Buzzer output
Low voltage reset (LVR)
External RC and 32768Hz crystal oscillator
Dual clock system offers three operating modes
-
Normal mode: Both RC and 32768Hz clock active
-
Slow mode: 32768Hz clock only
-
Idle mode: Periodical wake-up by watchdog timer
overflow
HALT function and wake-up feature reduce power
consumption
14-bit table read instructions for HT48R52
15-bit table read instructions for HT48R53
63 powerful instructions
One instruction cycle: 4 system clock periods
All instructions in 1 or 2 instruction cycles
Bit manipulation instructions
Up to 0.5
ms instruction cycle with 8MHz system clock
52-pin QFP package
Technical Document
Tools Information
FAQs
Application Note
-
HA0002E Reading Larger than Usual MCU Tables
-
HA0007E Using the MCU Look Up Table Instructions
-
HA0011E HT48 & HT46 Keyboard Scan Program
-
HA0019E Using the Watchdog Timer in the HT48 MCU Series
-
HA0020E Using the Timer/Event Counter in the HT48 MCU Series
Block Diagram
HT48R52/HT48R53
Rev. 1.10
2
June 6, 2005
M U X
P r o g r a m
C o u n t e r
I n t e r r u p t
C i r c u i t
I N T C
L o o k u p T a b l e
P o i n t e r
I n s t r u c t i o n
R e g i s t e r
I n s t r u c t i o n
D e c o d e r
A L U
S h i f t e r
T i m i n g
G e n e r a t o r
A C C
W D T
C o u n t e r
W D T
O s c i l l a t o r
P D
P O R T D
P B C
P B
P A C
P O R T A
P A
P O R T C
f
S Y S
/ 4
P r e s c a l e r
M
U
X
T M R
T M R C
S t a c k
S t a c k P o i n t e r
A d d r e s s D e c o d e r
P r o g r a m M e m o r y
R C
O s c i l l a t o r
L o o k u p T a b l e
R e g i s t e r
M e m o r y
P o i n t e r
M U X
A d d r e s s D e c o d e r
P r o g r a m M e m o r y
O S C 1
O S C 2
O S C 3
O S C 4
R E S , V D D
A V D D , V S S
A V S S , P V S S 0
P V S S 1
R e s e t &
L V R
R T C
O s c i l l a t o r
P E
P O R T E
P B 0 / B Z
P B 1 / B Z
P B 2 / I N T
P B 3 / T M R
P B 4 ~ P B 7
M
U
X
f
S Y S
/ 4
M
U
X
R T C O S C
W D T O S C
P C
P A 0 ~ P A 7
P C 0 ~ P C 7
P D 0 ~ P D 7
P E 0 ~ P E 7
Pin Assignment
Pin Description
Pin Name
I/O
Options
Description
PA0~PA7
I/O
Pull-high
Wake-up
CMOS/Schmitt
Trigger Input
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined by
pull-high options).
Each bit can be configured as a wake-up input by options.
PB0/BZ
PB1/BZ
PB2/INT
PB3/TMR
PB4~PB7
I/O
Pull-high
CMOS/Schmitt
PB0 or BZ
PB1 or BZ
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined by
pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively.
Once the PB0 or PB1 is selected as buzzer driving outputs, the output signal
range can be selected from f
S
/2~f
S
/16 by option.
This external interrupt input is pin-shared with PB2.The external interrupt in-
put is activated on a high to low transition. The timer input is pin-shared with
PB3.
PC0~PC7
I/O
Pull-high
PC0~PC7 constitute an 8-bit input/output port. PC0~PC7 are configured as
NMOS input/output pins with or without pull-high resistor by options.
PD0~PD7
I/O
Pull-high
PD0~PD7 constitute an 8-bit input/output port. PD0~PD7 are configured as
NMOS input/output pins with or without pull-high resistor by options.
PE0~PE7
I/O
Pull-high
PE0~PE7 constitute an 8-bit input/output port. PE0~PE7 are configured as
NMOS input/output pins with or without pull-high resistor by options.
RES
I
Schmitt trigger reset input. Active low.
OSC1
OSC2
I
O
RC
OSC1 and OSC2 are connected to an RC oscillator for the internal system
clock. In the case of RC operation, OSC2 will be hold high by the MCU.
OSC3
OSC4
I
O
RTC
Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz
crystal oscillator for timing purposes.
VDD
Positive power supply
AVDD
Positive power supply
VSS
Negative Power supply, ground
AVSS
Negative power supply, ground
PVSS0
Negative power supply for PC, PD7~PD4 port, ground
PVSS1
Negative power supply for PD3~PD0, PE port, ground
Note:
* The pull-high resistors of each I/O port (PA, PB, PC, PD, PE) are all controlled by port option.
HT48R52/HT48R53
Rev. 1.10
3
June 6, 2005
P A 7
P E 0
P E 1
P E 2
P E 3
P E 4
P E 5
P E 6
P E 7
P V S S 1
P D 0
P D 1
P D 2
V S S
P B 7
P B 6
P B 5
P B 4
P B 3 / T M R
P B 2 / I N T
P B 1 / B Z
P B 0 / B Z
A V D D
A V S S
N C
P C 7
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
3 4
3 5
3 6
3 7
3 8
3 9
4 8
4 9
5 0
5 1
5 2
2 3 2 4 2 5 2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
H T 4 8 R 5 2 / H T 4 8 R 5 3
5 2 Q F P - A
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
O
S
C
4
O
S
C
3
V
D
D
O
S
C
2
O
S
C
1
R
E
S
P
A
0
P
A
1
P
A
2
P
A
3
P
A
4
P
A
5
P
A
6
P
C
6
P
C
5
P
C
4
P
C
3
P
C
2
P
C
1
P
C
0
P
V
S
S
0
P
D
7
P
D
6
P
D
5
P
D
4
P
D
3
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V to V
SS
+6.0V
Storage Temperature ............................
-50C to 125C
Input Voltage..............................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature...........................
-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
f
SYS
=4MHz
2.2
5.5
V
f
SYS
=8MHz
3.3
5.5
f
SYS
=32768Hz
I
DD1
Operating Current (RC OSC)
3V
No load, f
SYS
=4MHz
1.2
2
mA
5V
2.5
5
I
DD2
Operating Current (RC OSC)
5V
No load, f
SYS
=8MHz
4
8
mA
I
DD3
Operating Current
(32768Hz OSC, RC off)
3V
No load, f
SYS
=32768Hz
0.3
0.6
mA
5V
0.6
1
I
STB1
Standby Current
(WDT and 32768Hz Enabled)
3V
No load, system HALT
5
mA
5V
10
I
STB2
Standby Current
(WDT Disabled, 32768Hz Enabled)
3V
No load, system HALT
0.8
1.5
mA
5V
1.5
2.5
V
IL1
Input Low Voltage for I/O Ports
0
0.3V
DD
V
V
IH1
Input High Voltage for I/O Ports
0.7V
DD
V
DD
V
V
IL2
Input Low Voltage (RES)
0
0.4V
DD
V
V
IH2
Input High Voltage (RES)
0.9V
DD
V
DD
V
V
LVR
Low Voltage Reset
3.3V option
2.7
3
3.3
V
I
OL
I/O Port Sink Current
3V
V
OL
=0.1V
DD
4
8
mA
5V
10
20
I
OH
I/O Port Source Current
3V
V
OH
=0.9V
DD
-2
-4
mA
5V
-5
-10
R
PH
Pull-high Resistance
3V
20
60
100
k
W
5V
10
30
50
HT48R52/HT48R53
Rev. 1.10
4
June 6, 2005
A.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
f
SYS
System Clock
(RC OSC)
2.2V~5.5V
400
4000
kHz
3.3V~5.5V
400
8000
f
TIMER
Timer I/P Frequency
2.2V~5.5V
0
4000
kHz
3.3V~5.5V
0
8000
t
WDTOSC
Watchdog Oscillator Period
3V
45
90
180
ms
5V
32
65
130
ms
t
FSP1
f
SP
Time-out Period Clock Source
from WDT
3V
With prescaler (f
S
/4096)
184
369
737
ms
5V
131
266
532
t
FSP2
f
SP
Time-out Period Clock Source
from 32.768kHz
3V
With prescaler (f
S
/4096)
125
ms
5V
125
t
RES
External Reset Low Pulse Width
1
ms
t
SST
System Start-up Timer Period
Power-up or wake-up
from HALT
1024
t
SYS
t
INT
Interrupt Pulse Width
1
ms
HT48R52/HT48R53
Rev. 1.10
5
June 6, 2005
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