256K x 1 STATIC RAM--SOI
HX6156
Aerospace Electronics
Advance Information
RADIATION
Fabricated with RICMOS
TM
IV Silicon on Insulator
(SOI) 0.75
m Process (L
eff
= 0.6
m)
Total Dose Hardness through 1x10
6
rad(SiO
2
)
Neutron Hardness through 1x10
14
cm
-2
Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
Dose Rate Survivability through 1x10
11
rad(Si)/s
Soft Error Rate of <1x10
-10
upsets/bit-day
in Geosynchronous Orbit
OTHER
Fast Read/Write Cycle Times
15 ns (Typical)
25 ns (-55 to 125
C)
Asynchronous Operation
CMOS or TTL Compatible I/O
Single 5 V
10% Power Supply
Packaging Options
24-Lead Flat Pack (0.540 in. x 0.600 in.)
28-LeadFlat Pack (0.500 in. x 0.720 in.)
FEATURES
GENERAL DESCRIPTION
The 256K x 1 Radiation Hardened Static RAM is a high
performance 262,144 word x 1-bit static random access
memory with industry-standard functionality. It is fabricated
with Honeywell's radiation hardened technology, and is
designed for use in systems operating in radiation environ-
ments. The RAM operates over the full military temperature
range and requires only a single 5 V
10% power supply.
The RAM is available with either TTL or CMOS compatible
I/O. Power consumption is typically less than 15 mW/MHz
in operation, and less than 5 mW when de-selected. The
RAM read operation is fully asynchronous, with an associ-
ated typical access time of 15 ns at 5 V.
Honeywell's enhanced SOI RICMOSTM IV (Radiation In-
sensitive CMOS) technology is radiation hardened through
the use of advanced and proprietary design, layout, and
process hardening techniques. The RICMOSTM IV process
is a 5-volt, SIMOX CMOS technology with a 150 gate
oxide and a minimum drawn feature size of 0.75
m (0.6
m
effective gate length--L
eff
). Additional features include
tungsten via plugs, Honeywell's proprietary SHARP pla-
narization process, and a lightly doped drain (LDD) struc-
ture for improved short channel reliability. A 7 transistor
(7T) memory cell is used for superior single event upset
hardening, while three layer metal power bussing and the
low collection volume SIMOX substrate provide improved
dose rate hardening.
HX6156
2
A: 0-17
Address input pins which select a particular bit within the memory array.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output driver in a high impedance state and disables
all input buffers except CE. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output driver in a high
impedance state. When at a high level NWE allows normal read operation.
NOE*
Negative output enable, when at a high level holds the data output driver in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE*
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output driver in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
D
Data input pin during a write operation. Remains in the high impedance state during a read operation.
Q
Data output pin during a read operation. Remains in the high impedance state during a write operation.
NCS
CE*
NWE
NOE*
MODE
D
Q
L
H
H
L
Read
X
Data Out
L
H
L
X
Write
Data In
High Z
H
X
XX
XX
Deselected
XX
High Z
X
L
XX
XX
Disabled
XX
High Z
TRUTH TABLE
FUNCTIONAL DIAGRAM
Notes:
X: VI=VIH or VIL
XX: VSS
VI
VDD
NOE=H: High Z output state maintained
for NCS=X, CE=X, NWE=X
SIGNAL DEFINITIONS
*Available in 28-pin package only.
NCS
A:0-2, 5, 13-17
CE*
NWE
NOE*
WE CS CE
NWE CS CE OE
Column Decoder
Data Input/Output
Row
Decoder
262,144 x 1
Memory
Array
A:3-4, 6-12
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
1 = enabled
Signal
9
(0 = high Z)
1
1
9
D
Q
3
HX6156
Total Dose
1x10
6
rad(SiO
2
)
Transient Dose Rate Upset
1x10
9
rad(Si)/s
Transient Dose Rate Survivability
1x10
11
rad(Si)/s
Soft Error Rate (SER)
<1x10
-10
upsets/bit-day
Neutron Fluence
1x10
14
N/cm
2
Parameter
Limits (2)
Test Conditions
RADIATION HARDNESS RATINGS (1)
Units
T
A
=25
C
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electrical
and timing performance parameters will remain within
specifications after rebound at VDD = 5.5 V and T =125
C
extrapolated to ten years of operation. Total dose hardness
is assured by wafer level testing of process monitor transis-
tors and RAM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 keV X-rays applied at a
dose rate of 1x10
5
rad(SiO
2
)/min at T = 25
C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse up to the transient dose rate upset
specification, when applied under recommended operat-
ing conditions.
To ensure validity of all specified performance param-
eters before, during, and after radiation (timing degrada-
tion during transient pulse radiation is
10%), it is sug-
gested that stiffening capacitance be placed on or near
the package VDD and VSS, with a maximum inductance
between the package (chip) and stiffening capacitance of
0.7 nH per part. If there are no operate-through or valid
stored data requirements, typical circuit board mounted
de-coupling capacitors are recommended.
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55
C to 125
C.
1 MeV equivalent energy,
Unbiased, T
A
=25
C
T
A
=125
C, Adams 90%
worst case environment
Pulse width
50 ns, X-ray,
VDD=6.0 V, T
A
=25
C
Pulse width
1
s
RADIATION CHARACTERISTICS
The SRAM will meet any functional or electrical specifica-
tion after exposure to a radiation pulse up to the transient
dose rate survivability specification, when applied under
recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs,
and power supply may significantly exceed the normal
operating levels. The application design must accommo-
date these effects.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This as-
sumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
The SRAM has an extremely low Soft Error Rate (SER) as
specified in the table below. This hardness level is defined
by the Adams 90% worst case cosmic ray environment.
The low SER is achieved by the use of a unique 7-transistor
memory cell and the oxide isolation of the SOI substrate.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under recom-
mended operating conditions. Fabrication with the SIMOX
substrate material provides oxide isolation between adja-
cent PMOS and NMOS transistors and eliminates any
potential SCR latchup structures. Sufficient transistor body
tie connections to the p- and n-channel substrates are
made to ensure no source/drain snapback occurs.
HX6156
4
VDD
Positive Supply Voltage (2)
-0.5
6.5
V
VPIN
Voltage on Any Pin (2)
-0.5
VDD+0.5
V
TSTORE
Storage Temperature (Zero Bias)
-65
150
C
TSOLDER
Soldering Temperature Time
2705
Cs
PD
Total Package Power Dissipation (3)
2.5
W
IOUT
DC or Average Output Current
25
mA
VPROT
ESD Input Protection Voltage (4)
2000
V
24 FP
2
28 FP
2
TJ
Junction Temperature
175
C
Parameter
Symbol
Parameter
Max
Symbol
Test Conditions
Worst Case
Units
CAPACITANCE (1)
Symbol
Test Conditions
Min
Max
Typical
(1)
Units
NCS=VDD=VDR
VI=VDR or VSS
VDR
Data Retention Voltage
2.5
V
IDR
Data Retention Current
500
A
NCS=VDR
VI=VDR or VSS
JC
Thermal Resistance (Jct-to-Case)
(1) This parameter is tested during initial design characterization only.
RECOMMENDED OPERATING CONDITIONS
Symbol
Max
Typ
Description
Parameter
Min
Worst Case
(2)
C/W
Units
VDD
Supply Voltage (referenced to VSS)
4.5
5.0
5.5
V
TA
Ambient Temperature
-55
25
125
C
VPIN
Voltage on Any Pin (referenced to VSS)
-0.3
VDD+0.3
V
Min
Typical
(1)
CI
Input Capacitance
5
7
pF
VI=VDD or VSS, f=1 MHz
CO
Output Capacitance
7
9
pF
VIO=VDD or VSS, f=1 MHz
Units
Rating
Min
Max
(1) Typical operating conditions: TA= 25
C, pre-radiation.
(2) Worst case operating conditions: TA= -55
C to +125
C, post total dose at 25
C.
DATA RETENTION CHARACTERISTICS
Parameter
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
ABSOLUTE MAXIMUM RATINGS (1)
5
HX6156
IDDSB1
Static Supply Current
1.5
mA
IDDSBMF Standby Supply Current - Deselected
1.5
mA
IDDOPW
Dynamic Supply Current, Selected
(Write)
4.0
mA
IDDOPR
Dynamic Supply Current, Selected
(Read)
4.0
mA
II
Input Leakage Current
-5
+5
A
IOZ
Output Leakage Current
-10
+10
A
VIL
Low-Level Input Voltage
1.7
VIH
High-Level Input Voltage
3.2
DC ELECTRICAL CHARACTERISTICS
Units
Test Conditions
Min
Max
Worst Case (2)
Symbol
Parameter
Typical
(1)
NCS=VDD, IO=0,
f=40 MHz
VIH=VDD, IO=0
VIL=VSS, f=0MHz
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
VSS
VI
VDD
VSS
VIO
VDD
Output=high Z
CMOS
0.7xV
DD
V
March Pattern
TTL
2.2
V
VDD = 5.5V
0.3
0.4
V
VDD = 4.5V, IOL = 10 mA
(CMOS)
= 8 mA
(TTL)
0.005
0.05
V
VDD = 4.5V, IOL = 200
A
4.3
4.2
V
VDD = 4.5V, IOH = -5 mA
4.5
V
DD
-0.05
V
VDD = 4.5V, IOH = -200
A
CMOS
0.3xV
DD
V
March Pattern
TTL
0.8
V
VDD = 4.5V
VOL
Low-Level Output Voltage
VOH
High-Level Output Voltage
(1) Typical operating conditions: VDD= 5.0 V,TA=25
C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55
C to +125
C, post total dose at 25
C.
(3) All inputs switching. DC average current.
DUT
output
Valid low
output
Vref1
CL >50 pF*
249
Tester Equivalent Load Circuit
2.9 V
Valid high
output
Vref2
-
+
-
+
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
HX6156
6
TAVAVR
Address Read Cycle Time
25
ns
TAVQV
Address Access Time
25
ns
TAXQX
Address Change to Output Invalid Time
3
ns
TSLQV
Chip Select Access Time
25
ns
TSLQX
Chip Select Output Enable Time
5
ns
TSHQZ
Chip Select Output Disable Time
10
ns
TEHQV
Chip Enable Access Time (4)
25
ns
TEHQX
Chip Enable Output Enable Time (4)
5
ns
TELQZ
Chip Enable Output Disable Time (4)
10
ns
TGLQV
Output Enable Access Time
9
ns
TGLQX
Output Enable Output Enable Time
0
ns
TGHQZ
Output Enable Output Disable Time
9
ns
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical
-55 to 125
C
Units
(2)
Min Max
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading C
L
>50 pF, or equivalent
capacitive output loading C
L
=5 pF for TSHQZ, TELQZ TGHQZ. For C
L
>50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25
C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125
C, post total dose at 25
C.
(4) Chip Enable (CE) pin only available with 28-lead FP.
*Only available in 28-lead package.
HIGH
IMPEDANCE
NCS
NOE
DATA VALID
CE
T
AVAVR
T
AVQV
T
AXQX
T
SLQV
T
SLQX
T
SHQZ
T
EHQX
T
EHQV
T
GLQX
T
GLQV
T
GHQZ
T
ELQZ
ADDRESS
(NWE = high)
DATA OUT
*
*
7
HX6156
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive
load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25
C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125
C, post total dose at 25
C.
(4) TAVAV = TWLWH + TWHWL
(5) Guaranteed but not tested.
(6) Chip Enable (CE) pin only available with 28-lead FP.
*Only available in 28-lead package.
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ADDRESS
HIGH
IMPEDANCE
DATA OUT
NWE
DATA IN
DATA VALID
T
AVAVW
NCS
CE
T
AVWH
T
WLWH
T
AVWL
T
WLQZ
T
DVWH
T
WHQX
T
WHDX
T
SLWH
T
EHWH
T
WHAX
T
WHWL
*
HX6156
8
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (NCS), or chip
enable (CE) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and chip enable and write enable
(NWE) must be high. The output driver can be controlled
independently by the NOE signal. Consecutive read cycles
can be executed with NCS held continuously low, and with
CE held continuously high, and toggling the addresses.
For an address activated read cycle, NCS must be valid prior
to, coincident with or within (TAVQV minus TSLQV) time
following edge transition(s). CE must be valid a minimum of
(TEHQV minimums TAVQV) time prior to the activating
address edge transitions(s). Any amount of toggling or skew
between address edge transitions is permissible; however,
data outputs will become valid TAVQV time following the
latest occurring address edge transition. The minimum ad-
dress activated read cycle time is TAVAV. When the RAM is
operated at the minimum address activated read cycle time,
the data output will remain valid on the RAM I/O until TAXQX
time following the next sequential address transition.
To control a read cycle with NCS, all addresses must be
valid at least (TAVQV minus TSLQV) time prior to the
enabling NCS edge transition. CE must be valid a minimum
of (TEHQV minus TSLQV) time prior to the enabling NCS
edge transition. Address or CE edge transitions can occur
later than the specified setup times to NCS, however, the
valid data access time will be delayed. Any address edge
transition, which occurs during the time when NCS is low,
will initiate a new read access, and the data output will not
become valid until TAVQV time following the address edge
transition. The data output will enter a high impedance
state TSHQZ time following a disabling NCS edge transi-
tion.
To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edge transition. Address or NCS edge transitions can
occur later than the specified setup times to CE; however,
the valid data access time will be delayed. Any address
edge transition which occurs during the time when CE is
high will initiate a new read access, and data output will not
become valid until TAVQV time following the address edge
transition. The data output will enter a high impedance
state TELQZ time following a disabling CE edge transition.
Write Cycle
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To per-
form a write operation, both NWE and NCS must be low,
and CE must be high. The ouput driver can be controlled
independently by the output enable (NOE) signal. Con-
secutive write cycles can be performed with NWE or NCS
held continuously low, or CE held continuously high. At
least one of the control signals must transition to the
opposite state between consecutive write operations.
To write data into the RAM, NWE and NCS must be held low
and CE must be held high for at least TWLWH/TSLSH/
TEHEL time. Any amount of edge skew between the
signals can be tolerated, and any one of the control signals
can initiate or terminate the write operation. For consecu-
tive write operations, write pulses must be separated by the
minimum specified TWHWL/TSHSL/TELEH time. Address
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
must remain valid during the entire write time. A valid data
overlap of write pulse width time of TDVWH/TDVSH/TDVEL,
and an address valid to end of write time of TAVWH/
TAVSH/TAVEL also must be provided for during the write
operation. Hold times for address inputs and data input with
respect to the disabling NWE/NCS/CE edge transition
must be a minimum of TWHAX/TSHAX/TELAX time and
TWHDX/TSHDX/TELDX time, respectively. The minimum
write cycle time is TAVAV.
9
HX6156
TESTER AC TIMING CHARACTERISTICS
QUALITY AND RADIATION HARDNESS
ASSURANCE
Honeywell maintains a high level of product integrity through
process control, utilizing statistical process control, a com-
plete "Total Quality Assurance System," a computer data
base process performance tracking system, and a radia-
tion-hardness assurance strategy.
The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiation hardness is assured on every wafer by irradiating
test structures as well as SRAM product, and then monitor-
ing key parameters which are sensitive to ionizing radiation.
Conventional MIL-STD-883 TM 5005 Group E testing,
which includes total dose exposure with Cobalt 60, may
also be performed as required. This Total Quality approach
ensures our customers of a reliable product by engineering
in reliability, starting with process development and con-
tinuing through product qualification and screening.
SCREENING LEVELS
Honeywell offers several levels of device screening to meet
your system needs. "Engineering Devices" are available
with limited performance and screening for breadboarding
and/or evaluation testing. Hi-Rel Level B and S devices
undergo additional screening per the requirements of MIL-
STD-883. As a QML supplier, Honeywell also offers QML
Class Q and V devices per MIL-PRF-38535 and are avail-
able per the applicable Standard Microcircuit Drawing (SMD).
QML devices offer ease of procurement by eliminating the
need to create detailed specifications and offer benefits of
improved quality and cost savings through standardization.
RELIABILITY
Honeywell understands the stringent reliability require-
ments for space and defense systems and has extensive
experience in reliability testing on programs of this nature.
This experience is derived from comprehensive testing of
VLSI processes. Reliability attributes of the RICMOS
TM
process were characterized by testing specially designed
irradiated and non-irradiated test structures from which
specific failure mechanisms were evaluated. These specific
mechanisms included, but were not limited to, hot carriers,
electromigration and time dependent dielectric breakdown.
This data was then used to make changes to the design
models and process to ensure more reliable products.
In addition, the reliability of the RICMOS
TM
process and
product in a military environment was monitored by testing
irradiated and non-irradiated circuits in accelerated dy-
namic life test conditions. Packages are qualified for prod-
uct use after undergoing Groups B & D testing as outlined
in MIL-STD-883, TM 5005, Class S. The product is qualified
by following a screening and testing flow to meet the
customer's requirements. Quality conformance testing is
performed as an option on all production lots to ensure the
ongoing reliability of the product.
High Z = 2.9V
3 V
0 V
1.5 V
VDD-0.5 V
0.5 V
VDD/2
1.5 V
VDD-0.4V
0.4 V
High Z
3.4 V
2.4 V
High Z
VDD/2
0.4 V
High Z
3.4 V
2.4 V
High Z
TTL I/O Configuration
Input
Levels*
Output
Sense
Levels
CMOS I/O Configuration
High Z = 2.9V
* Input rise and fall times <1 ns/V
VDD-0.4V
HX6156
10
The 256K x 1 SRAM is offered in a custom 24-lead and 28-
lead flat pack. These packages are constructed of multi-
layer ceramic (Al
2
O
3
) and contain internal power and ground
planes. All NC pins must be connected to either VDD, VSS
or an active driver to prevent charge buildup in the radiation
environment.
PACKAGING
DYNAMIC BURN-IN DIAGRAM
STATIC BURN-IN DIAGRAM
VDD = 5.6V,
R
10K
, VIH = VDD, VIL = VSS
Ambient Temperature > 125
C, F0 > 100 KHz Sq Wave
Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
VDD = 5.5V, R < 10 K
Ambient Temperature > 125
C
R
F18
F10
F11
F12
F13
F14
F15
F16
F17
F1
F18
VSS
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
Q
NWE
VSS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
F9
F8
F7
F6
F5
F4
F3
F2
F18
VDD/2
F0
VDD
A17
A16
A15
A14
A13
A12
A11
A10
A9
D
NCS
256K x 1 SRAM
Optional capacitors can be mounted to the package by the
user to maximize supply noise decoupling and increase
board packing density. The capacitors attach electrically to
the internal package power and ground planes. This design
minimizes resistance and inductance of the bond wire and
package, both of which are critical in a transient radiation
environment.
28-LEAD FP PINOUT
VDD
A17
A16
A15
A14
A13
A12
A11
A10
A9
D
NCS
A0
A1
A2
A3
A4
A5
A6
A7
A8
Q
NWE
VSS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
Top
View
256K x 1
24-LEAD FP PINOUT
VDD
A17
A16
A15
A14
A13
CE
NOE
A12
A11
A10
A9
D
NCS
A0
A1
A2
A3
A4
A5
NC
NC
A6
A7
A8
Q
NWE
VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
256K x 1
Top
View
VSS
VDD
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
VDD
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
A0
A1
A2
A3
A4
A5
A6
A7
A8
Q
NWE
VSS
VDD
A17
A16
A15
A14
A13
A12
A11
A10
A9
D
NCS
R
R
VDD/2
256K x 1 SRAM
11
HX6156
24-LEAD FLAT PACK
28-LEAD FLAT PACK
E
1
e
b
D
(width)
(pitch)
L
TOP
VIEW
U
W
X
Y
Capacitor
Pads
F
[1] BSC Basic lead spacing between centers
[2] Where lead is brazed to package
[3] Parts delivered with leads unformed
[4] Lid connected to VSS
A
b
C
D
e
E
E2
E3
F
G
L
Q
S
U
W
X
Y
0.105
0.015
0.017
0.002
0.003 to 0.006
0.720
0.008
0.050
0.005 [1]
0.500
0.007
0.380
0.008
0.060 ref
0.650
0.005 [2]
0.035
0.004
0.295 min [3]
0.026 to 0.045
0.045
0.010
0.130 ref
0.050 ref
0.075 ref
0.010 ref
All dimensions in inches
1
BOTTOM
VIEW
S
Index
A
Lead
(Alloy 42) [3]
C
E2
G
Q
Kovar
Lid [4]
E3
Ceramic
Body
A
b
C
D
e
E
E2
E3
F
0.150 0.015
0.015 0.002
0.003 to 0.006
0.600 0.007
0.050 0.005 [1]
0.540 0.007
0.450 0.007
0.030 min
0.550 0.005 [2]
G
L
Q
S
V
W
X
Y
Z
0.050 0.005
0.376 min [3]
0.026 to 0.045
0.025 0.010
0.300 ref
0.050 ref
0.030 ref
0.100 ref
0.080 ref
[1] Tolerances are non-accumulative
[2] Where lead is brazed to package
[3] Parts delivered with leads unformed
[4] Lid is connected to VSS
All dimensions in inches
E
1
e
b
D
Lid Marking
(width)
(pitch)
Right Reading
on Lid
L
F
L
V
Z
1
X
W
Y
VSS
VDD
VDD
BOTTOM
VIEW
Optional capacitors
in cutout*
S
Q
E2
A
Lead
(Alloy 42)
cutout
Kovar
Lid [4]
Ceramic
Body
C
E3
G
HX6156
12
Helping You Control Your World
900197 Rev. A
6-97
ORDERING INFORMATION (1)
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information.
(2) Engineering Device description: Parameters are tested from -55 to 125
C, 24 hr burn-in, no radiation guaranteed.
Contact Factory with other needs.
To learn more about Honeywell Solid State Electronics Center,
visit our web site at http://www.ssec.honeywell.com
C
INPUT
BUFFER TYPE
C=CMOS Level
T=TTL Level
S
SCREEN LEVEL
V=QML Class V
Q=QML Class Q
S=Class S
B=Class B
E=Engr Device (2)
H
SOURCE
H=HONEYWELL
X
PROCESS
X=SOI
PART NUMBER
6156
H
TOTAL DOSE
HARDNESS
F=3x10
5
rad(SiO
2
)
G=5x10
5
rad(SiO
2
)
H=1x10
6
rad(SiO
2
)
N
PACKAGE DESIGNATION
L=24-Lead FP
N=28-Lead FP
K=Known Good Die
- = Bare Die (No Package)
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