RADIATION
Fabricated with RICMOSTM IV Silicon on Insulator (SOI)
0.7
m Process (L
eff
= 0.55
m)
Total Dose Hardness through 1x10
6
rad(SiO
2
)
Neutron Hardness through 1x10
14
cm
-2
Dynamic and Static Transient Upset Hardness
through 1x10
11
rad (Si)/s
Dose Rate Survivability through <1x10
12
rad(Si)/s
Soft Error Rate of <1x10
-10
upsets/bit-day in
Geosynchronous Orbit
No Latchup
128K x 8 STATIC RAM--SOI
HX6228
OTHER
Read/Write Cycle Times
16 ns (Typical)
25 ns (-55 to 125
C)
Typical Operating Power <25 mW/MHz
Asynchronous Operation
CMOS or TTL Compatible I/O
Single 5 V
10% Power Supply
Packaging Options
- 32-Lead Flat Pack (0.820 in. x 0.600 in.)
- 40-Lead Flat Pack (0.775 in. x 0.710 in.)
Military & Space Products
GENERAL DESCRIPTION
The 128K x 8 Radiation Hardened Static RAM is a high
performance 131,072 word x 8-bit static random access
memory with industry-standard functionality. It is fabricated
with Honeywell's radiation hardened technology, and is
designed for use in systems operating in radiation environ-
ments. The RAM operates over the full military temperature
range and requires only a single 5 V
10% power supply. The
RAM is wire bond programmable for either TTL or CMOS
compatible I/O. Power consumption is typically less than 25
mW/MHz in operation, and less than 5 mW in the low power
disabled mode. The RAM read operation is fully asynchro-
nous, with an associated typical access time of 15 ns at 5V.
Honeywell's enhancedSOI RICMOSTMIV (Radiation Insen-
sitive CMOS) technology is radiation hardened through the
use of advanced and proprietary design, layout and process
hardening techniques. The RICMOSTM IV process is an
advanced 5-volt, SIMOX CMOS technology with a 150
gate oxide and a minimum feature size of 0.7
m (0.55
m
effective gate length--L
eff
). Additional features include
Honeywell's proprietary SHARP planarization process, and
a lightly doped drain (LDD) structure for improved short
channel reliability. A 7 transistor (7T) memory cell is used for
superior single event upset hardening, while three layer
metal power bussing and the low collection volume SIMOX
substrate provide improved dose rate hardening.
FEATURES
HX6228
2
FUNCTIONAL DIAGRAM
CE
NCS
NWE
NOE
MODE
DQ
H
L
H
L
Read
Data Out
H
L
L
X
Write
Data In
X
H
XX
XX
Deselected
High Z
L
X
XX
XX
Disabled
High Z
TRUTH TABLE
SIGNAL DEFINITIONS
A: 0-16
Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Not chip select, when at a low level allows normal operation. When at a high level NCS forces the SRAM to
a precharge condition, holds the data output drivers in a high impedance state and disables all the input
buffers except CE. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
Notes:
X: VI=VIH or VIL
XX: VSS
VI
VDD
NOE=H: High Z output state maintained
for NCS=X, CE=X, NWE=X
NCS
A:3-7,12,14-16
CE
NWE
NOE
WE CS CE
NWE CS CE OE
Column Decoder
Data Input/Output
Row
Decoder
131,072 x 8
Memory
Array
A:0-2, 8-11, 13
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
1 = enabled
Signal
8
DQ:0-7
(0 = high Z)
8
8
9
HX6228
3
Total Dose
1x10
6
rad(SiO
2
)
Transient Dose Rate Upset (3)
1x10
11
rad(Si)/s
Transient Dose Rate Survivability
1x10
12
rad(Si)/s
Soft Error Rate
<1x10
-10
upsets/bit-day
Neutron Fluence
1x10
14
N/cm
2
Parameter
Limits (2)
Test Conditions
RADIATION HARDNESS RATINGS (1)
The SRAM will meet any functional or electrical specifica-
tion after exposure to a radiation pulse up to the transient
dose survivability specification,when applied under recom-
mended operating conditions. Note that the current con-
ducted during the pulse by the RAM inputs, outputs, and
power supply may significantly exceed the normal operat-
ing levels. The application design must accommodate
these effects.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This as-
sumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
The SRAM is capable of meeting the specified Soft Error
Rate (SER), under recommended operating conditions.
This hardness level is defined by the Adams 90% worst
case cosmic ray environment for geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above radiation
exposure conditions when applied under recommended
operating conditions. Fabrication with the SIMOX sub-
strate material provides oxide isolation between adjacent
PMOS and NMOS transistors and eliminates any potential
SCR latchup structures. Sufficient transistor body tie con-
nections to the p- and n-channel substrates are made to
ensure no source/drain snapback occurs.
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electrical
and timing performance parameters will remain within
specifications after rebound at VDD = 5.5 V and T =125
C
extrapolated to ten years of operation. Total dose hardness
is assured by wafer level testing of process monitor transis-
tors and RAM product using 10 KeV X-ray and Co60
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 KeV X-rays applied at
a dose rate of 1x10
5
rad(SiO
2
)/min at T = 25
C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient ionizing
radiation pulse up to the specified transient dost rate upset
specification, when applied under recommended operat-
ing conditions. To ensure validity of all specified perfor-
mance parameters before, during, and after radiation (tim-
ing degradation during transient pulse radiation is
20%),
it is suggested that stiffening capacitance be placed on or
near the package VDD and VSS, with a maximum induc-
tance between the package (chip) and stiffening capaci-
tance of 0.7 nH per part. If there are no operate-through or
valid stored data requirements, typical circuit board
mounted de-coupling capacitors are recommended.
Units
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, -55
C to 125
C.
(3) Applies to 40-lead flat pack only. Assume
1x100
9
rad(Si))/s for 32-lead flat pack. Stiffening capacitance is suggested for optimum expected
dose rate upset performance as stated above.
T
A
=125
C, Adams 90%
worst case environment
Pulse width
50 ns, X-ray,
VDD=6.0 V, T
A
=25
C
Pulse width
1
s
T
A
=25
C
1 MeV equivalent energy,
Unbiased, T
A
=25
C
RADIATION CHARACTERISTICS
HX6228
4
VDD
Supply Voltage Range (2)
-0.5
6.5
V
VPIN
Voltage on Any Pin (2)
-0.5
VDD+0.5
V
TSTORE
Storage Temperature (Zero Bias)
-65
150
C
TSOLDER
Soldering Temperature (5 Seconds)
270
C
PD
Maximum Power Power Dissipation (3)
2.5
W
IOUT
DC or Average Output Current
25
mA
VPROT
ESD Input Protection Voltage (4)
1500
V
JC
Thermal Resistance (Jct-to-Case)
2
C/W
TJ
Junction Temperature
175
C
Parameter
Symbol
Units
ABSOLUTE MAXIMUM RATINGS (1)
Max
Min
Rating
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 1 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Supply Voltage (referenced to VSS)
4.5
5.0
5.5
V
TA
Ambient Temperature
-55
25
125
C
VPIN
Voltage on Any Pin (referenced to VSS)
-0.3
VDD+0.3
V
Max
Typ
Units
Description
Parameter
Min
CI
Input Capacitance
6
7
pF
VI=VDD or VSS, f=1 MHz
CO
Output Capacitance
8
9
pF
VIO=VDD or VSS, f=1 MHz
Parameter
Max
Min
Symbol
Test Conditions
Worst Case
Units
CAPACITANCE (1)
(1) This parameter is tested during initial design characterization only.
Typical
Symbol
Test Conditions
Min
DATA RETENTION CHARACTERISTICS
Max
Parameter
Typical
(1)
Units
NCS=VDD=VDR
VI=VDR or VSS
VDR
Data Retention Voltage (3)
2.5
V
IDR
Data Retention Current
200
1.0
mA
NCS=VDR
VI=VDR or VSS
(1) Typical operating conditions: TA= 25
C, pre-radiation.
(2) Worst case operating conditions: TA= -55
C to +125
C, past total dose at 25
C.
(3) To maintain valid data storage during transient radiation, VDD must be held within the recommended operating range.
Worst Case
(2)
HX6228
5
DC ELECTRICAL CHARACTERISTICS
IDDSB
Static Supply Current
0.4
2.0
mA
IDDSBMF Standby Supply Current - Deselected
0.4
2.0
mA
IDDOPW
Dynamic Supply Current, Selected
(Write)
4.5
6.0
mA
IDDOPR
Dynamic Supply Current, Selected
(Read)
2.8
4.5
mA
II
Input Leakage Current
-5
+5
A
IOZ
Output Leakage Current
-10
+10
A
VIL
Low-Level Input Voltage
VIH
High-Level Input Voltage
Units
Test Conditions
Min
Max
Worst Case
(2)
Symbol
Parameter
Typical
(1)
NCS=VDD, IO=0,
f=40 MHz,
VIH=VDD, IO=0,
VIL=VSS, f=0MHz
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
VSS
VI
VDD
VSS
VIO
VDD
Output=high Z
CMOS
3.2
0.7xV
DD
V
March Pattern
TTL
2.2
V
VDD = 5.5V
0.3
0.4
V
VDD = 4.5V, IOL = 10 mA
0.005
0.1
V
VDD = 4.5V, IOL = 200
A
4.3
4.2
V
VDD = 4.5V, IOH = -5 mA
4.5
V
DD
-0.1
V
VDD = 4.5V, IOH = -200
A
CMOS
1.7
0.3xV
DD
V
March Pattern
TTL
0.8
V
VDD = 4.5V
VOL
Low-Level Output Voltage
VOH
High-Level Output Voltage
(1) Typical operating conditions: VDD= 5.0 V,TA=25
C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55
C to +125
C, post total dose at 25
C.
(3) All inputs switching. DC average current.
DUT
output
Valid low
output
Vref1
CL >50 pF*
249
Tester Equivalent Load Circuit
2.9 V
Valid high
output
Vref2
-
+
-
+
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
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