4 2

4 3

4 4

4 5

4 6

4 0

4 1

3 3

3 0

3 1

3 2

2 7

2 8

2 9

2 6

3 4

3 5

3 6

4 7

4 8

4 9

5 0

S S

I/O15
I/O14
I/O13
I/O12

I/O11
I/O10
I/O 9
I/O 8

S S

L C A S
U C A S
OE

A 8
A 7
A 6
A 5
A 4

S S

A 9

S S

I/O15
I/O14
I/O13
I/O12

3 8

3 9

4 0

4 1

4 2

I/O11
I/O10
I/O 9
I/O 8
NC

3 2

3 3

3 4

3 5

3 6

S S

3 7

L C A S
U C A S
OE

2 9

3 0

3 1

A 9
A 8
A 7

2 6

2 7

2 8

A 6
A 5
A 4

2 3

2 4

2 5

S S

2 2

T h e G M 7 1 C ( S ) 1 6 1 6 0 C /C L i s t h e n e w
generation dynamic RAM organized 1,048,576
x 16 bit. GM71C(S)16160C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71C(S)16160C/CL offers
Fast Page Mode as a high speed access mode.
M u l t i p l e x e d a d d r e s s i n p u t s p e r m i t t h e
G M 7 1 C ( S ) 1 6 1 6 0 C /C L t o b e p a c k a g e d i n
standard 400 mil 42 pin plastic SOJ , and
standard 400mil 44(50)pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.

Description

F eatur es

* 1 ,048,576 Words x 16 Bit Organization
* Fast Page Mode Capability
* S ingle Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time

P in Configuration

1,048,576 WORDS x 16 BIT

CMOS DYNAMIC RAM

GM71CS16160CL

(Unit: ns)

GM71C(S)16160C/CL-5
GM71C(S)16160C/CL-6
GM71C(S)16160C/CL-7

R A C

C A C

R C

50
60

13
15

9 0

110

35
40

130

* Low Power
Active : 605/550/495mW (MAX)
S tandby : 11mW (CMOS level : MAX )
0.83mW (L-version : MAX )
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 4096 Refresh Cycles/64ms
* 4096 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* B attery B ack Up Operation (L-version)
* 2 CAS byte Control

(Top View)

1 1

1 0

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

2 5

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

C C

W E

R A S

A11
A10

A 0
A 1

C C

A 2
A 3

44(50) TSOP II

C C

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

1 0

1 1

C C

W E

R A S

1 2

1 3

1 4

A11
A10

A 0

1 5

1 6

1 7

A 1
A 2
A 3

1 8

1 9

2 0

C C

2 1

42 SOJ

GM71C16160C

Rev 0.1 / Apr'01

GM71CS16160CL

GM71C16160C

Rev 0.1 / Apr'01

P in Descr iption

P in

F unction

P in

F unction

C C

S S

Address Inputs

Refresh Address Inputs

Data Input/ Data Output

Row Address Strobe

Read/W rite Enable

Power (+5V)

Ground

No Connection

Ordering Information

R A S

W E

Column Address Strobe

Output Enable

O E

Absolute Maximum Ratings*

1.0

Power Dissipation

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

Symbol

Parameter

Rating

Unit

S T G

IN/OUT

C C

O U T

0 ~

-55 ~

125

Ambient Temperature under B ias

S torage Temperature (Plastic)

Voltage on any Pin Relative to V

S S

Voltage on V

C C

Relative to V

S S

Short Circuit Output Current

-1.0 ~

7.0V

-1.0 ~

7.0V

T ype No.

Access Time

Package

GM71C(S)16160CJ/C L J - 5
GM71C(S)16160CJ/C L J - 6
GM71C(S)16160CJ/C L J - 7

50ns
60ns
70ns

400 Mil
42 Pin
Plastic SOJ

50ns
60ns
70ns

400 Mil
44(50) Pin
Plastic TSOP II

GM71C(S)16160CT/CLT -5
GM71C(S)16160CT/CLT -6
GM71C(S)16160CT/CLT -7

UCAS, LCAS

GM71CS16160CL

GM71C16160C

Rev 0.1 / Apr'01

T r uth Table

Notes: 1. H: High (inactive) L: Low(active) D: H or L
2.

W C S

>= 0ns Early write cycle

W C S

<= 0ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

L C A S

Output

Open

Valid

Lower byte

Upper byte

Word

Operation

S tandby

RAS-only

Refresh cycle

Read cycle

Early write cycle

Open

Undefined

Delayed Write

cycle

H to L

C B R R e f resh

Self Refresh

(L-series)

H to L

RAS

UCAS

W E

O E

Notes

1,3

1,2,3

1,3

Lower byte

Upper byte

Word

Lower byte

Upper byte

Word

Lower byte

Upper byte

Word

Undefined

Open

Valid

Word

Read-modify
-write cycle

Read cycle

(Output disabled)

H to L

L to H

R ecommended DC Operating Conditions

= 0 ~

70C)

Symbol

Parameter

Unit

C C

S upply Voltage

Input High Voltage

Input Low Voltage

M a x

5.5

6.0

0.8

T yp

5.0

M in

4.5

2.4

-1.0

Note: All voltage referred to V ss.
T he supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.

GM71CS16160CL

GM71C16160C

Rev 0.1 / Apr 01

= 5V+/-10%, V ss

= 0 ~ 70C)

Symbol

Parameter

Note

O L

Output Level
Output "H" Level Voltage (I

O U T

-5mA

)

Unit

M a x

C C

0.4

M in

2.4

Output Level
Output "L" Level Voltage (I

O U T

2mA)

C C 1

C C 2

S tandby Current (TTL)
Power Supply Standby Current
(RAS, UCAS, LCAS = V

O U T

High-Z)

C C 3

RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode

R C

min)

C C 4

C C 5

S tandby Current (CMOS)
Power Supply Standby Current
(RAS, UCAS or LCAS >= V

- 0.2V, D

OUT

= High-Z)

C C 6

CAS-before-RAS Refresh Current
(t

R C

min)

150

L(I)

-10

L(O)

-10

Input Leakage Current
Any Input (0V

6V)

Output Leakage Current
(D

O U T

is Disabled, 0V

O U T

6V)

Fast Page Mode Current

Fast Page Mode
(

= t

min)

110

50ns

100

1, 2

110

50ns

100

115

50ns

105

110

50ns

C C 8

(Standby with CBR Refresh)
(

=31.3us

0.3

O U T

500

C C 9

(RAS, UCAS or LCAS<=0.2V

O U T

300

Note: 1. I

C C

depends on output load condition when the device is selected.
(max) is specified at the output open condition.

2. Address can be changed once or less while RAS = V

I L

3. Address can be changed once or less while LCAS and UCAS = V

5. L-version.

Operating Current

(RAS, UCAS or LCAS Cycling

R C

min)

CAS, LCAS = V

O U T

GM71CS16160CL

GM71C16160C

Rev 0.1 / Apr'01

Capacitance

= 5V+/-10%, T

= 25C)

Symbol

Parameter

Note

I/O

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

1, 2

Unit

M a x

M in

AC Characteristics

= 5V+/-10%, T

= 0 ~

70C, Vss = 0V, Note 1, 2, 3, 19)

Test Conditions

Input rise and fall times : 5 ns

Output timing reference levels : 0.4V, 2.4V

Input timing reference levels : 0.8V , 2.4V

Output load : 2TTL gate + C

(100 pF)

(Including scope and jig)

Note: 1. Capacitance measured with B oonton Meter or effective capacitance measuring method.
2. UCAS and LCAS = V

to disable D

O U T

R ead, W r ite, Read-Modify-W r ite and Refr esh Cycles

(Common Parameters)

Symbol

Parameter

Note

Max

Unit

Min

Max

Min

Max

Min

R C

Random Read or Write Cycle Time

9 0

110

130

R P

R A S

10,000

C A S

10,000

A S R

Row Address Set up Time

R A H

Row Address Hold Time

A S C

Column Address Set-up Time

CAH

Column Address Hold Time

R C D

R A D

R S H

RAS Hold Time

CSH

C R P

T ransition Time (Rise and Fall)

R A S Precharge Time

CAS Pulse Width

RAS to CAS Delay Time

RAS to Column Address Delay Time

CAS Hold Time

CAS to RAS Precharge Time

DZO

DZC

OE Delay Time from D

CAS Delay Time from D

G M 7 1 C ( S ) 1 6 1 6 0
C / C L - 5

OE to D

Delay Time

C A S Precharge Time

O D D

G M 7 1 C ( S ) 1 6 1 6 0
C / C L - 6

G M 7 1 C ( S ) 1 6 1 6 0
C / C L - 7

RAS Pulse Width

Электронный компонент: GM71CS16160CJ/CLJ-6