The GM71V(S)16160C/CL is the new
generation dynamic RAM organized 1,048,576
x 16 bit. GM71V(S)16160C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71V(S)16160C/CL offers
Fast Page Mode as a high speed access mode.
M u l t i p l e x e d a d d r e s s i n p u t s p e r m i t t h e
GM71V(S)16160C/CL to be packaged in
standard 400 mil 42pin plastic SOJ, and
standard 400mil 44(50)pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.

Description

Features

* 1,048,576 Words x 16 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (3.3V+/-0.3V)
* Fast Access Time & Cycle Time

Pin Configuration

1,048,576 WORDS x 16 BIT

CMOS DYNAMIC RAM

GM71VS16160CL

* Low Power
Active : 396/360/324mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
0.54mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
*4096 Refresh Cycles/64ms
* 4096 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-version)
* 2 CAS byte Control

(Unit: ns)

GM71V(S)16160C/CL-5
GM71V(S)16160C/CL-6

GM71V(S)16160C/CL-7

RAC

CAC

50
60

13
15

110

35
40

130

(Top View)

44(50) TSOP II

42 SOJ

I/O15
I/O14
I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

LCAS

UCAS

A8
A7
A6
A5
A4

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

LCAS

UCAS

I/O0
I/O1
I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

RAS

A11
A10

A0
A1

A2
A3

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

RAS

A11

A10

GM71V16160C

Rev 0.1 / Apr'01

GM71VS16160CL

GM71V16160C

Rev 0.1 / Apr'01

Pin Description

Pin

Function

Pin

Function

A0-A11

I/O0-I/O15

RAS

Address Inputs

Refresh Address Inputs

Data Input/ Data Output

Row Address Strobe

Read/Write Enable

Power (+3.3V)

Ground

No Connection

Ordering Information

UCAS, LCAS

Column Address Strobe

Output Enable

Absolute Maximum Ratings*

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

Type No.

Access Time

Package

GM71V(S)16160CJ/CLJ -5
GM71V(S)16160CJ/CLJ -6
GM71V(S)16160CJ/CLJ -7

50ns
60ns
70ns

400 Mil
42 Pin
Plastic SOJ

50ns
60ns
70ns

400 Mil
44(50) Pin
Plastic TSOP II

GM71V(S)16160CT/CLT -5
GM71V(S)16160CT/CLT -6
GM71V(S)16160CT/CLT -7

Symbol

Parameter

Rating

Unit

STG

IN/OUT

OUT

0 ~ 70

-55 ~ 125

-0.5 ~ Vcc+0.5
(<=4.6V(MAX))

-0.5 ~ 4.6

Ambient Temperature under Bias

Storage Temperature

Voltage on any Pin Relative to V

Supply Voltage Relative to V

Short Circuit Output Current

1.0

Power Dissipation

GM71VS16160CL

GM71V16160C

Rev 0.1 / Apr'01

Truth Table

Notes: 1. H: High (inactive) L: Low(active) D: H or L
2.

WCS

>= 0ns Early write cycle

WCS

<= 0ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

RAS

LCAS UCAS

Output

Open

Valid

Lower byte

Upper byte

Word

Operation

Standby

RAS-only

Refresh cycle

Read cycle

Early write cycle

Open

Undefined

Delayed Write

cycle

H to L

CBR Refresh

Self Refresh

(L-series)

H to L

Notes

1,3

1,2,3

1,3

Lower byte

Upper byte

Word

Lower byte

Upper byte

Word

Lower byte

Upper byte

Word

Undefined

Open

Valid

Word

Read-modify
-write cycle

Read cycle

(Output disabled)

H to L

L to H

Recommended DC Operating Conditions (T

= 0 ~

70C)

Symbol

Parameter

Unit

Supply Voltage

Input High Voltage

Input Low Voltage

Max

3.6

+ 0.3

0.8

Typ

3.3

Min

3.0

2.0

-0.3

Note: All voltage referred to Vss.
The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.

GM71VS16160CL

GM71V16160C

Rev 0.1 / Apr'01

DC Electrical Characteristics (V

= 3.3V+/-0.3V, Vss = 0V, T

= 0 ~ 70C)

Symbol

Parameter

Note

Output Level
Output "H" Level Voltage (I

OUT

-2mA

)

Unit

Max

0.4

Min

2.4

Output Level
Output "L" Level Voltage (I

OUT

2mA)

CC1

Operating Current
Average Power Supply Operating Current
(RAS, UCAS or LCAS Cycling

min)

CC2

Standby Current (TTL)
Power Supply Standby Current
(RAS, UCAS, LCAS = V

OUT

High-Z)

CC3

RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(t

min)

CC4

CC5

Standby Current (CMOS)
Power Supply Standby Current
(RAS, UCAS or LCAS >= V

- 0.2V, D

OUT

= High-Z)

CC6

CAS-before-RAS Refresh Current
(t

min)

150

L(I)

-10

L(O)

-10

Input Leakage Current
Any Input (0V

4.6V)

Output Leakage Current
(D

OUT

is Disabled, 0V

OUT

<= 4.

6V)

Fast Page Mode Current
Average Power Supply Current
Fast Page Mode
(t

= t

min)

110

50ns

60ns

70ns

100

1, 2

1, 3

110

50ns

60ns

70ns

100

115

50ns

60ns

70ns

105

110

50ns

60ns

70ns

100

CC7

CC8

Battery Back Up Operating Current
(Standby with CBR Refresh)
(t

=31.3us

RAS

0.3

us,

OUT

High-Z)

400

4,5

CC9

Self-Refresh Mode Current
(RAS, UCAS or LCAS<=0.2V

OUT

High-Z)

250

Note: 1. I

depends on output load condition when the device is selected.

(max) is specified at the output open condition.

2. Address can be changed once or less while RAS = V

3. Address can be changed once or less while

CAS and LCAS = V

4. UCAS = L (<=0.2) and LCAS = L (<=0.2) while RAS = L (<=0.2).

5. L-version.

Standby Current RAS = V

CAS, LCAS = V

OUT

Enable

GM71VS16160CL

GM71V16160C

Rev 0.1 / Apr'01

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

Capacitance (V

= 3.3V+/-0.3V, T

= 25C)

Symbol

Parameter

Note

I/O

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

1, 2

Unit

Max

Min

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. UCAS and LCAS = V

to disable D

OUT

AC Characteristics (V

= 3.3V+/-0.3V, T

= 0 ~

70C, Note 1, 2, 18, 19, 20)

Test Conditions

Input rise and fall times : 5 ns

Output timing reference levels : 0.8V, 2.0V

Input timing reference levels : 0.8V, 2.0V

Output load : 1TTL gate + C

(100 pF)

(Including scope and jig)

Symbol

Parameter

Note

Max

Unit

Min

Max

Min

Max

Min

Random Read or Write Cycle Time

110

130

RAS Precharge Time

RAS

RAS Pulse Width

10,000

CAS

CAS Pulse Width

10,000

ASR

Row Address Set up Time

RAH

Row Address Hold Time

ASC

Column Address Set-up Time

CAH

Column Address Hold Time

RCD

RAS to CAS Delay Time

RAD

RAS to Column Address Delay Time

RSH

RAS Hold Time

CSH

CAS Hold Time

CRP

CAS to RAS Precharge Time

Transition Time (Rise and Fall)

DZO

OE Delay Time from D

DZC

CAS Delay Time from D

GM71V(S)16160
C/CL-5

OE to D

Delay Time

CAS Precharge Time

ODD

GM71V(S)16160
C/CL-6

GM71V(S)16160
C/CL-7

Электронный компонент: GM71VS16160CCL-6