The GM71V(S)18163C/CL is the new
generation dynamic RAM organized 1,048,576
x 16 bit. GM71V(S)18163C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71V(S)18163C/CL offers
Extended Data out(EDO) Mode as a high speed
access mode. Multiplexed address inputs permit
the GM71V(S)18163C/CL to be packaged in
standard 400 mil 42pin plastic SOJ, and standard
400mil 44(50)pin plastic TSOP II. The package
size provides high system bit densities and is
compatible with widely available automated
testing and insertion equipment.

Description

Features

* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (3.3V+/-0.3V)
* Fast Access Time & Cycle Time

(Unit: ns)

Pin Configuration

1,048,576 WORDS x 16 BIT

CMOS DYNAMIC RAM

GM71VS18163CL

GM71V(S)18163C/CL-5
GM71V(S)18163C/CL-6

GM71V(S)18163C/CL-7

RAC

CAC

HPC

50
60

13
15

104

20
25

124

* Low Power
Active : 684/612/540mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 1024 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-version)
* 2 CAS byte Control

(Top View)

GM71V18163C

I/O15
I/O14
I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

LCAS

UCAS

A8
A7
A6
A5
A4

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

LCAS

UCAS

I/O0
I/O1
I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

RAS

A11
A10

A0
A1

A2
A3

44(50) TSOP II

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

RAS

42 SOJ

Rev 0.1 / Apr'01

GM71VS18163CL

GM71V18163C

Rev 0.1 / Apr'01

Pin Description

Pin

Function

Pin

Function

A0-A9

I/O0-I/O15

RAS

Address Inputs

Refresh Address Inputs

Data-In/Out

Row Address Strobe

Read/Write Enable

Power (+3.3V)

Ground

No Connection

Ordering Information

Column Address Strobe

Output Enable

Absolute Maximum Ratings*

Type No.

Access Time

Package

GM71V(S)18163CJ/CLJ -5
GM71V(S)18163CJ/CLJ -6
GM71V(S)18163CJ/CLJ -7

50ns
60ns
70ns

400 Mil
42 Pin
Plastic SOJ

50ns
60ns
70ns

400 Mil
44(50) Pin
Plastic TSOP II

GM71V(S)18163CT/CLT -5
GM71V(S)18163CT/CLT -6
GM71V(S)18163CT/CLT -7

Symbol

Parameter

Rating

Unit

STG

IN/OUT

OUT

0 ~ 70

-55 ~ 125

-0.5 ~ Vcc+0.5
(<=4.6V(MAX))

-0.5 ~ 4.6

Ambient Temperature under Bias

Storage Temperature

Voltage on any Pin Relative to V

Supply Voltage Relative to V

Short Circuit Output Current

1.0

Power Dissipation

UCAS, LCAS

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

GM71VS18163CL

GM71V18163C

Rev 0.1 / Apr'01

Truth Table

RAS

LCAS UCAS

Output

Open

Valid

Lower byte

Upper byte

Word

Operation

Standby

RAS-only

Refresh cycle

Read cycle

Early write cycle

Open

Undefined

Delayed Write

cycle

H to L

CBR Refresh

Self Refresh

(L-series)

H to L

Notes

1,3

1,2,3

1,3

Lower byte

Upper byte

Word

Lower byte

Upper byte

Word

Lower byte

Upper byte

Word

Undefined

Open

Valid

Word

Read-modify
-write cycle

Read cycle

(Output disabled)

H to L

L to H

Recommended DC Operating Conditions (T

= 0 ~ 70C)

Symbol

Parameter

Unit

Supply Voltage

Input High Voltage

Input Low Voltage

Max

3.6

+ 0.3

0.8

Typ

3.3

Min

3.0

2.0

-0.3

Note: All voltage referred to Vss.
The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.

Notes: 1. H: High (inactive) L: Low(active) D: H or L
2.

WCS

>= 0ns Early write cycle

WCS

<= 0ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

GM71VS18163CL

GM71V18163C

Rev 0.1 / Apr'01

DC Electrical Characteristics (V

= 3.3V+/-0.3V, Vss = 0V, T

= 0 ~ 70C)

Symbol

Parameter

Note

Output Level
Output "H" Level Voltage (I

OUT

-2mA

)

Unit

Max

0.4

Min

2.4

Output Level
Output "L" Level Voltage (I

OUT

mA)

CC1

Operating Current
Average Power Supply Operating Current
(RAS, UCAS or LCAS Cycling

min)

CC2

Standby Current (TTL)
Power Supply Standby Current
(RAS, UCAS, LCAS = V

OUT

High-Z)

CC3

RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(t

min)

CC4

CC5

Standby Current (CMOS)
Power Supply Standby Current
(RAS, UCAS or LCAS >= V

- 0.2V, D

OUT

= High-Z)

CC6

CAS-before-RAS Refresh Current
(t

min)

CC7

L(I)

-10

L(O)

-10

Input Leakage Current
Any Input (0V

4.6V)

Output Leakage Current
(D

OUT

is Disabled, 0V

OUT

<= 4.

6V)

EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(t

HPC

= t

HPC

min)

Note: 1. I

depends on output load condition when the device is selected.

(max) is specified at the output open condition.

2. Address can be changed once or less while RAS = V

3. Address can be changed once or less while LCAS and UCAS = V

4. UCAS = L (<=0.2) and LCAS = L (<=0.2) while RAS = L (<=0.2).

5. L-version.

Battery Back Up Operating Current(Standby with CBR Ref.)
(CBR refresh, t

=125us

RAS

0.3

us,

OUT

High-Z, CMOS interface)

400

4,5

CC8

CC9

Self-Refresh Mode Current
(RAS, UCAS or LCAS<=0.2V

OUT

High-Z)

250

150

1, 2

1, 3

Standby Current RAS = V

CAS, LCAS = V

OUT

Enable

190

50ns

60ns

70ns

170

150

190

50ns

60ns

70ns

170

150

185

50ns

60ns

70ns

165

145

190

50ns

60ns

70ns

170

150

GM71VS18163CL

GM71V18163C

Rev 0.1 / Apr'01

Capacitance (V

= 3.3V+/-0.3V, T

= 25C)

Symbol

Parameter

Note

I/O

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

1, 2

Unit

Max

Min

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. UCAS and LCAS = V

to disable D

OUT

AC Characteristics (V

= 3.3V+/-0.3V, T

= 0 ~

70C, Note 1, 2, 18, 19, 20)

Test Conditions

Input rise and fall times : 2 ns

Output timing reference levels : 0.8V, 2.0V

Input levels : V

= 0V, V

= 3V

Output load : 1TTL gate + C

(100 pF)

Input timing reference levels : 0.8V, 2.0V

(Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

Symbol

Parameter

Note

Max

Unit

Min

Max

Min

Max

Min

Random Read or Write Cycle Time

104

124

RAS Precharge Time

RAS

RAS Pulse Width

10,000

CAS

CAS Pulse Width

10,000

ASR

Row Address Set up Time

RAH

Row Address Hold Time

ASC

Column Address Set-up Time

CAH

Column Address Hold Time

RCD

RAS to CAS Delay Time

RAD

RAS to Column Address Delay Time

RSH

RAS Hold Time

CSH

CAS Hold Time

CRP

CAS to RAS Precharge Time

Transition Time (Rise and Fall)

DZO

OE Delay Time from D

DZC

CAS Delay Time from D

GM71V(S)18163
C/CL-5

OE to D

Delay Time

CAS Precharge Time

ODD

GM71V(S)18163
C/CL-6

GM71V(S)18163
C/CL-7

Электронный компонент: GM71VS18163CCL