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Description

The GMM27316230ETG is a 16M x 72bits
Synchronous Dynamic RAM MODULE
which is assembled 18 pieces of 16M x 4bits
Synchronous DRAMs in 54 pin TSOP II, 2
pieces of 16 bits Register in 48 pin TSSOP,
one clock distribution PLL in 24 pin SOP and
one 2048 bit EEPROM in 8 pin TSSOP
package mounted on a 168 pin printed circuit
board with decoupling capacitors. The
G M M 2 7 3 1 6 2 3 0 E T G i s o p t i m i z e d f o r
application to the systems which are required
high density and large capacity such as main
memory of the computers and an image
memory systems, and to the others which are
requested compact size.
The GMM27316230ETG provides common
data inputs and outputs.

GMM27316230ETG (Double Side)

Features

Pin Name

CK0, 1, 2, 3
CKE0
S0, 2
RAS
CAS
WE
A0 ~ A11
BA0,1
REGE
DQ0 ~ 63
CB0 ~ 7
DQMB0 ~ 7
V

NC
V

REF

SDA
SCL
SA0 ~ 2
WP
DU

Clock input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Bank Address input
Register Enable
Data input / output
Check Bits
Data input / output Mask
Power for internal circuit
Ground for internal circuit
No Connect
Power Supply for Reference
Serial Data input/ output
Serial Clock
Address in EEPROM
Write Protect for SPD
Don't Use

* PC133/PC100/PC66 Compatible

-7(143MHz)/-75(133MHz)/-8(125MHz)

-7K(PC100,2-2-2)/-7J(PC100,3-2-2)
* 3.3V ± 0.3V Power supply

* Maximum Clock frequency

100/125/133/143 MHz

* LVTTL Interface

* Burst read/write operation and burst read/

single write operation capability
* Programmable burst length ;

1, 2, 4, 8, Full page

* Programmable burst sequence

Sequential / Interleave

* Full Page burst length capability

Sequential burst
Burst stop capability

* Programmable CAS Latency ; 2, 3

* CKE power down mode

* Input / Output data masking

* 4096 Refresh Cycles / 64ms

* Auto refresh / Self refresh Capability
* Serial Presence Detect with EEPROM

-1-

16Mx72 bits

PC100/PC133 SDRAM Registered DIMM

based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh

GMM27316230ETG

This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.1/Apr.01

GMM27316230ETG

Rev. 1.1/Apr.01

Pin

Symbol

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Pin Configuration

Pin

Symbol

Pin

Symbol

Pin

Symbol

Pin

Symbol

Pin

Symbol

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112

DQ32
DQ33
DQ34
DQ35

DQ36
DQ37
DQ38
DQ39
DQ40

DQ41
DQ42
DQ43
DQ44
DQ45

DQ46
DQ47

CB4
CB5

NC
NC

CAS

DQMB4

DQ18
DQ19

DQ20

REF

, NC

*CKE1

DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27

DQ28
DQ29
DQ30
DQ31

CK2

SDA

SCL

DQMB1

A0
A2
A4
A6
A8

A10/AP

BA1

CK0

DQMB2
DQMB3

NC
NC

CB2
CB3

DQ16
DQ17

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

DQMB5

*S1

RAS

A1
A3
A5
A7
A9

BA0

A11

CK1

*A12

CKE0

*S3

DQMB6
DQMB7

*A13

NC
NC

CB6
CB7

DQ48
DQ49

141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

DQ50
DQ51

DQ52

REF

, NC

REGE

DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59

DQ60
DQ61
DQ62
DQ63

CK3

SA0
SA1
SA2

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7
DQ8

DQ9

DQ10
DQ11
DQ12
DQ13

DQ14
DQ15

CB0
CB1

NC
NC

DQMB0

* These pins are not used in this module

-2-

GMM27316230ETG

Rev. 1.1/Apr.01

Block Diagram

Capacitor
one 0.0022uF and one 0.22uF per SDRAM

SA2

Serial PD

SDA

SCL

U0 ~ U17

Vss

47kohm

CK1,2,3

12pF

10ohm

REGE

Vcc

10kohm

A0 ~ A11, BA0,1

RAS

CAS

CKE0, DQMB0~7

U0 - U17
U0 - U17
U0 - U17
U0 - U17
U0 - U17

S0,2

U0 - U17

DQ0

DQ1

DQ2

DQ3

U10

U11

U12

DQM CS

DQMB0

DQMB1

DQMB4

DQMB5

DQM CS

DQMB2

DQMB3

DQM CS

U13

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CB0

CB1
CB2
CB3

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

CB4

CB5
CB6
CB7

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

U14

U15

U16

U17

DQM CS

DQMB6

DQMB7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

PLL

CK0

3 SDRAMS
3 SDRAMS
3 SDRAMS
3 SDRAMS
3 SDRAMS

3 SDRAMS

2 Registers

12pF

PCK

SA0 SA1

-3-

GMM27316230ETG

Rev. 1.1/Apr.01

Pin Description

Pin Name

DESCRIPTION

CK0, 1, 2, 3

(input pins)

CK is the master clock input to this pin. The other input signals are
referred at CK rising edge.

CKE0

(input pin)

This pin determines whether or not the next CK is valid. If CKE is
High, the next CK rising edge is valid. If CKE is Low, the next CK
rising edge is invalid. This pin is used for power-down and clock
suspend modes.

When S is Low, the command input cycle becomes valid. When S is
high, all inputs are ignored. However, internal operations (bank active,
burst operations, etc.) are held.

S0, 2

(input pins)

Although these pin names are the same as those of conventional
DRAMs, they function in a different way. These pins define operation
commands (read, write, etc.) depending on the combination of their
voltage levels. For details, refer to the command operation section.

RAS, CAS and WE

(input pins)

A0 ~ A11

(input pins)

Row address (AX0 to AX11) is determined by A0 to A11 level at the
bank active command cycle CK rising edge. Column address is
determined by A0 to A8 level at the read or write command cycle CK
rising edge. And this column address becomes burst access start
address. A10 defines the precharge mode. When A10 = High at the
precharge command cycle, both banks are precharged. But when A10 =
Low at the precharge command cycle, only the bank that is selected by
BA0 is precharged.

BA0,1

(input pin)

BA0,1 are bank select signal. If BA0 is Low and BA1 is High, bank 0 is
selected. If BA0 is High and BA1 is Low, bank 1 is selected. If BA0 is
Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is
High, bank 3 is selected.

DQ0 ~ DQ63

CB0 ~ CB7

(I/O pins)

Data is input and output from these pins. These pins are the same as
those of a conventional DRAMs. Data is not latched in the register.

DQMB0 ~ DQMB7

(input pins)

DQMB controls input/output buffers.
*Read operation: If DQMB is High, The output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
*Write operation: If DQMB is High, the previous data is held (the new data
is not written). If DQMB is Low, the data is written.

(power supply pins)

3.3 V is applied. (V

is for the internal circuit)

(power supply pins)

Ground is connected. (V

is for the internal circuit)

No Connection pins.

REGE

If REGE input is high, permits the DIMM to operate in `registered mode`.
If REGE input is low, permits the DIMM to operate in `buffered mode`.

-4-

GMM27316230ETG

Rev. 1.1/Apr.01

Registered DIMM Operation

1. All control and address signals are registered on-DIMM register and hence delayed by one cycle in
arriving at the SDRAMs. But data is not registered in the register.

2. CAS latency defines the delay from when a READ command is registered on a rising clock edge to
when the data from that READ command becomes available at the outputs. Do not confuse DIMM
CAS latency with the SDRAM CAS latency which is one clock less.

Absolute Maximum Ratings

Notes : 1. Respect to V

Symbol

Value

Unit

Note

Parameter

-0.5 to Vcc+0.5

(<= 4.6 (max))

Voltage on any pin relative to V

-0.5 to +4.6

Supply voltage relative to V

OUT

Short circuit output current

1.0

Power dissipation

Topr

0 to +70

Operating temperature

Tstg

-55 to +125

Storage temperature

Notes : 1. All voltage referred to V

2. V

(max) = 5.6V for pulse width <= 3ns

3. V

(min) = -2.0V for pulse width <= 3ns

Recommended DC Operating Conditions (Ta = 0 to + 70C)

Symbol

Min

Unit

Note

, V

CCQ

, V

SSQ

Input high voltage

1, 2

Input low voltage

1,3

Supply voltage

Parameter

Max

3.0

3.6

2.0

Vcc+0.3

-0.3

0.8

-5-

GMM27316230ETG

Rev. 1.1/Apr.01

DC Characteristics (Ta = 0 to 70C, V

, V

CCQ

= 3.3 V +/- 0.3 V, V

, V

SSQ

= 0 V)

Parameter

Symbol

Unit Test conditions Notes

Operating

current

Standby current in

power down

CC2P

Self refresh current

CC6

>=V

- 0.2

<=0.2V

Burst length= 1

= min

1, 2, 3

CKE = V

= 12 ns

CC1

Standby current in

power down

(input signal stable)

CC2PS

CKE=V

= infinity

Standby current in

non power down

(CAS Latency=2)

CC2N

CKE,CS = V

= 12ns

Standby current in

non power down

(input signal stable)

CC2NS

CKE = V

= infinity

Active standby current

in power down

CC3P

CKE = V

= 12 ns,

DQ = High-Z

1,2,5

Active standby current

in power down

(input signal stable)

CC3PS

CKE = V

= infinity

2,6

Active standby current

in non power down

CC3N

CKE,CS = V

= 12 ns,

DQ = High-Z

1,2,4

Active standby current

in non power down

(input signal stable)

CC3NS

CKE = V

= infinity

2,8

Burst

operating

current

CC4

= min

BL = 4

1,2,3

( CL= 2 )

CC4

( CL= 3 )

Refresh current

= min

CC5

- 8

Max

-7J

1200

350

- 75

Max

1300

Max

-7K

- 7

Max

280

110

1600

550

1800

1500

1600

1500

1800

1600

1500

1800

1600

-6-

GMM27316230ETG

Rev. 1.1/Apr.01

Notes : 1. I

depends on output load condition when the device is selected. I

CC (

max) is specified at the

output open condition.
2. One bank operation.
3. Addresses are changed once per one cycle.
4. Addresses are changed once per two cycles.
5. After Power down mode, CLK operating current.
6. After Power down mode, no CLK operating current.
7. After self refresh mode set, self refresh current.
8. Input signals are V

I H

or V

fixed.

Input leakage current

0 <=Vin <=V

Output leakage current

0<=Vout<=V

DQ = disable

Output high voltage

= -2 mA

Output low voltage

=2 mA

-1

-1.5

1.5

0.4

Parameter

Symbol

Unit Test conditions Notes

Min

Max

- 7, - 75, - 8, - 7K, - 7J

2.4

Capacitance (Ta = 25C, V

, V

CCQ

= 3.3V +/- 0.3V)

Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. DQMB = V

to disable Dout.

3. This parameter is sampled and not 100% tested.

Symbol

Parameter

Min

Max

Unit

Notes

Input capacitance (A0 ~ A11, BA0, BA1)

1, 3

Input capacitance (RAS, CAS, WE, CKE0)

Input capacitance (CK0, CK1, CK2, CK3)

Input capacitance (S0,S2)

I/O

I/O capacitance (DQ0 ~ 63, CB0 ~ 7)

1, 3

1, 2, 3

Input capacitance (DQMB0,1,2,3,4,5,6,7)

1, 3

-7-

GMM27316230ETG

Rev. 1.1/Apr.01

AC Characteristics (Ta = 0 to 70C, V

, V

CCQ

= 3.3 V +/- 0.3 V, V

, V

SSQ

= 0 V)

Symbol

Unit Notes

Parameter

System clock
cycle time

(CL=2)

(CL=3)

CKH

CLK high pulse width

CKL

CLK low pulse width

Access time
from CLK

(CL=2)

(CL=3)

1, 2

Data-out hold time

1, 2, 3

CLK to Data-out low
impedance

CLK to Data-out
high impedance
( CL = 2,3 )

1, 4

Data-in setup time

Data-in hold time

Address setup time

Address hold time

CES

1, 5

CKE setup time

CESP

CKE setup time for
power down exit

CEH

CKE hold time

Command (CS, RAS,
CAS, WE, DQM)
setup time

Ref/Active to Ref/Active
command period

Command (CS, RAS,
CAS, WE, DQM)
hold time

RAS

Active to Precharge
command period

RCD

Active command to
column command
(same bank)

Precharge to active
command period

- 7K

Min Max

120000

- 7J

Min Max

120000

- 8

Min Max

120000

- 75

Min Max

7.5

2.5

5.4

2.7

1.5

5.4

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

120000

- 7

Min Max

2.5

5.4

2.7

1.5

5.4

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

120000

-8-

GMM27316230ETG

Rev. 1.1/Apr.01

AC Characteristics (Ta = 0 to 70C, V

, V

CCQ

= 3.3 V +/-0.3 V, V

, V

SSQ

= 0 V)

(Continued)

Notes : 1. AC measurement assumes

= 1ns. Reference level for timing of input signals is 1.40V.

is longer than 1ns,transition time compensation should be considered.

2. Access time is measured at 1.40V. Load condition is C

= 50pF without termination.

(min)defines the time at which the outputs achieves the low impedance state.

(max)defines the time at which the outputs achieves the high impedance state.

CES

define CKE setup time to CKE rising edge except Power down exit command.

6. The on-DIMM PLL must be given enough clock cycles to stabilize (

STAB

) before any

operation can be guaranteed.

Test Condition

· Input and output-timing reference levels: 1.4V
· Input waveform and output load: See following figures

20%

0.4V

2.4V

I/O

80%

OPEN

input

Symbol

Notes

Parameter

RRD

Active (a) to Active (b)
command period

REF

Refresh period

RWL

Write recovery or data-in
to precharge lead time

Unit

- 8

Min Max

- 7K

Min Max

- 7J

Min Max

- 75

Min Max

7.5

- 7

Min Max

STAB

PLL Stabilization time

200

-9-

GMM27316230ETG

Rev. 1.1/Apr.01

Relationship Between Frequency and Minimum Latency

Notes

RCD

Active command to column
command (same bank)

= [

RAS

], 1

Active command to active
command (same bank)

RAS

Active command to Precharge
command (same bank)

Precharge command to active
command (same bank)

RWL

Write recovery or last data-in to
Precharge command

(same bank)

RRD

Active command to active
command (different bank)

SREX

Self refresh exit time

APW

= [

RWL

], 1

Last data in to active command
(Auto Precharge, same bank)

SEC

= [

]

Self refresh exit to command
input

HZP

Precharge
command to
high impedance

HZP

(CL=2)

(CL=3)

APR

Last data out to active
command
(auto Precharge) (same bank)

Last data out to
Precharge
(early Precharge)

(CL=2)

(CL=3)

CCD

Column command to column
command

WCD

Write command to data in
latency

DID

DQM to data in

DOD

DQM to data out

PEC

Power down exit to command
input

CLE

CKE to CLK disable

RSA

CDD

Parameter

(ns)

frequency(MHz)

CS to command disable

Symbol

-7J

100

- 2

-75

133

7.5

-2

-8

125

-2

100

-1

-2

-1

- 2

-7

143

-2

100

- 1

- 2

-7K

100

-1

-2

100

-1

-2

100

- 1

- 2

-10-

GMM27316230ETG

Rev. 1.1/Apr.01

Relationship Between Frequency and Minimum Latency

Notes : 1.

RCD

RRD

are recommended value.

Symbol

Notes

BSR

Burst stop to
output valid
data hold

BSR

(CL=2)

(CL=3)

BSH

Burst stop to
output high
impedance

BSH

(CL=2)

(CL=3)

BSW

Burst stop to write data ignore

Parameter

(ns)

frequency(MHz)

- 7K

- 7J

-7

143

- 8

125

100

-75

133

7.5

100

-11-

GMM27316230ETG

Rev. 1.1/Apr.01

Package Dimension

NOTE : 1. Tolerances on all dimensions ±5 (0.127) unless otherwise specified.

2. Thickness includes Plating and / or Metallization.

168

5250(133.35)

5013.78(127.35)

1700(43.18)

1450(36.83)

2150(54.61)

450(11.43)

250(6.35)

700(17.78)

157.48(4.0)

1650(41.91)

"C"

"B"

"A"

4550(115.57)

DETAIL "B"

DETAIL "A"

5.9(0.15)

100(2.54)

min.

39.37(1.0)

50(1.27)

78.74(2.0)

39.37(1.0)

DETAIL "C"

78.74(2.0)

122.83(3.12)

39.37(1.0)

125(3.175)

Unit: mil (mm)
* (1 mil = 1/1000 inches)

R78.74

(2.0)

R78.74

(2.0)

(Front Side)

(Rear Side)

50(1.27)

157.48(4.0)

min.

157.48(4.0) max.

-12-

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