INTRO.PDF

Table of Contents

Chapter 1

Introduction

Outline of Characteristics
Characteristics
Block Diagram
Pin Assignment and Terminal
Pin Dimension
Pin Description and Circuit
I/O circuit types and options
Electrical Characteristics

Chapter 2

Architecture

Block Description
Program Memory (ROM)
EPROM Address Register
Data Memory (RAM)
X-Register (X)
Y-Register (Y)
Accumulator (Acc)
Arithmetic and Logic Unit (ALU)
State Counter (SC)
Clock Generator
Pulse Generator
Initial Reset Circuit
Watch Dog Timer (WDT)
Stop Function
Port Operation

Chapter 3

Instruction

Table of Contents

............................................................................................1-1

.................................................................1-1

..................................................................................1-1

..................................................................................1-2

..........................................................1-3

..................................................................................1-4

.................................................................1-7

.............................................................1-8

................................................................1-10

...........................................................................................2-1

.............................................................................2-1

..................................................................2-1

................................................................2-2

........................................................................2-3

...................................................................................2-3
...................................................................................2-4

............................................................................2-4

.......................................................2-4

...........................................................................2-5

...............................................................................2-6
...............................................................................2-7

............................................................................2-8

.................................................................2-8

....................................................................................2-9

..................................................................................2-9

........................................................................................3-1

Table of Contents

Chapter 4

EPROM
GMS34004TK/34112TK/34140TK

Mode Define
Port Define
Programming Data
Write/Read Data Conversion
Checksum
Programming Control
Programming DC Specification
EPROM read mode(1/2)
EPROM read mode (2/2)
EPROM write mode (1/2)
EPROM write mode (2/2)
Lock bit write mode (1/2)
Lock bit write mode (2/2)
Lock bit read mode (1/2)
Lock bit read mode (2/2)
GMS34004T/112T/140T (Pin assignment & Package)
EPROM (KHz) mode
EPROM write only mode

GMS34004TK/34112TK/34140TK

Mode Define
Port Define
Programming Data
Write/Read Data Conversion
Checksum
Programming Control
Programming DC Specification
EPROM read mode(1/2)
EPROM read mode (2/2)
EPROM write mode (1/4)
EPROM write mode (2/4)
EPROM write mode (3/4)
EPROM write mode (4/4)
Lock bit write mode (1/3)
Lock bit write mode (2/3)
Lock bit write mode (3/3)
Lock bit read mode (1/2)
Lock bit read mode (2/2)

.................................................................................................4-1

.........................................................4-1

.....................................................................................4-1

.......................................................................................4-2

...........................................................................4-2

............................................................4-3

.........................................................................................4-3

........................................................................4-3

.........................................................4-3

...................................................................4-4

..................................................................4-4
..................................................................4-5
..................................................................4-5
..................................................................4-6
..................................................................4-6
..................................................................4-7
..................................................................4-7

.....................4-8

.........................................................................4-9

..................................................................4-9

.............................................................4-10

.....................................................................................4-10

........................................................................................4-11

...........................................................................4-11

............................................................4-12

........................................................................................4-12

......................................................................4-12

........................................................4-12

...................................................................4-13
...................................................................4-13

..................................................................4-14
..................................................................4-14
..................................................................4-15

..................................................................4-15
..................................................................4-16
..................................................................4-16
..................................................................4-16
..................................................................4-18
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1 - 1

CHAPTER 1. Introduction

OUTLINE OF CHARACTERISTICS

The GMS340 series are remote control transmitter which uses CMOS technology,

and the EPROM version of GMS34XXX series.
This enables transmission code outputs of different configurations, multiple custom
code output, and double push key output for easy fabrication.
The GMS340 series are suitable for remote control of TV, VCR, FANS, Air-
conditioners, Audio Equipments, Toys, Games etc.

Characteristics

Program memory : 512bytes for GMS34004T

1,024 bytes for GMS34112T/140T

Data memory : 32

¡¿

4 bits

43 types of instruction set

3 levels of subroutine nesting

1 bit output port for a large current (REMOUT signal)

Operating frequency :300KHz~500KHz at KHz version

2.4MHz~4MHz at MHz version
300KHz~4.2MHz at WIDE version

Instruction cycle : f

OSC

/6 at KHz and WIDE version

OSC

/48 at MHz version

CMOS process (3.0V or 5.0V power supply)

Stop mode (Through internal instruction)

Released stop mode by key input

Built in capacitor for ceramic oscillation circuit at KHz version

Built in a watch dog timer (WDT)

Low operating voltage

: 2.2~4.5V (at KHz and MHz version)

Normal operating voltage: 4.0~5.0V (at WIDE version)

Table 1-1 GMS34XXXT series members

Chapter 1. Introduction

Series

Program memory

Data memory

I/O ports

Input ports

Output ports

Package

KHz version

MHz version

WIDE version

GMS34004T

512

¡¿

D0 ~ D5

16DIP

GMS34004TK

GMS34004TM

GMS34004TW

GMS34112T

1,024

¡ç

¡ç
¡ç
¡ç

20DIP/SOP/SSOP

GMS34112TK

GMS34112TM

GMS34112TW

GMS34140T

¡ç

D0 ~ D9

24DIP/SOP

GMS34140TK

GMS34140TM

GMS34140TW

1 - 3

Pin Assignment and terminals

Pin Assignment

Fig 1-2 GMS34004T Pin Assignment

(16PDIP)

Fig 1-3 GMS34112T Pin Assignment

(20DIP/SOP)

Fig 1-4 GMS34112T Pin Assignment

(20SSOP only)

Chapter 1. Introduction

Fig 1-5 GMS34140T Pin Assignment

(24DIP/SOP)

VDD

OSC1

OSC2

REMOUT

RESET/Vpp

GND

RESET/Vpp

VDD

OSC1

OSC2

REMOUT

RESET/Vpp

VDD

OSC1

OSC2

REMOUT

GND

RESET/Vpp

GND

VDD

OSC1

OSC2

REMOUT

1 - 7

Pin

Function

Pin Description and Circuit

Pin Description

I/O

Connected to 2.2~4.5V power supply at KHz and MHz
version or 4.0 ~ 5.5V power supply at WIDE version.

Connected to 0V power supply.

Used to input a manual reset. When the pin goes "L",
the D-output ports and REMOUT-output port are initialized to
"L", and ROM address is set to address 0 on page 0.
For programming, this pin receives 12.5V programming
voltage.

4-bit input port.
STOP mode is released by "L" input of each pin.

The output is the structure of N-channel-open-drain.

4-bit I/O port. (Input mode is set only when each of them
output "H".)
In outputting, each can be set and reset independently(or at
once.)
The output is in the form of C-MOS.
STOP mode is released by "L" input of each pin.

High current output port.
The output is in the form of C-MOS.
The state of large current on is "H".

Oscillator input. Input to the oscillator circuit and connection
point for ceramic resonator.
Internal capacitors available at KHz version.
A feedback resistor is connected between this pin and OSC2.

Connect a resonator between this pin and OSC1.

GND

RESET

K0~K3

D0~D9

R0~R3

REMOUT

OSC1

OSC2

Input

Output

I/O

Output

Input

Output

Chapter 1. Introduction

1 - 9

Built in feedback-resistor
about 1

§Û

OSC2

Pin

I/O

Note

Built in resonance
Capacitor at KHz version
C1=C2 = 100pF

¡¾

15%

[C1,C2 are not available
for MHz and WIDE
version]

OSC1

I/O circuit

Built in damping-resistor
Rd = 4

§Ú

[No resistor in MHz
operation]

¡æ

¡ç

¡æ

¡ç

¡è

OSC2

OSC1

STOP

Chapter 1. Introduction

Frequency

Resonator Maker

Part Name

Load Capacitor

320KHz

ZTB320D

C1=C2=Open

ZTB500E

C1=C2=Open

500KHz

3.43MHz

ZTA3.43MG

C1=C2=30pF

TDK

FCR3.52M5

C1=C2=33pF

ZTA3.64MG

C1=C2=30pF

3.84MHz

TDK

FCR3.64M5

C1=C2=33pF

ZTA3.84MG

C1=C2=30pF

TDK

FCR3.84M5

C1=C2=33pF

CQ recommend 430KHz~500KHz resonator

3.52MHz

3.64MHz

4.00MHz

ZTA4.00MG

C1=C2=30pF

1 - 10

Parameter

Supply Voltage

Programming Voltage

Power dissipation

Storage temperature range

Input voltage

Output voltage

Unit

¡É

Electrical Characteristics

Absolute maximum ratings (Ta = 25

¡É

)

Symbol

Tstg

OUT

Max. rating

-0.3 ~ 7.0

-0.3 ~ 13.5

700 *

-55 ~ 125

-0.3 ~ V

+0.3

-0.3 ~ V

+0.3

* Thermal derating above 25

¡É

: 6mW per degree

¡É

rise in temperature.

Parameter

Supply Voltage

Operating temperature

Unit

¡É

Recommended operation condition

Rating

2.2 ~ 4.5

4.0 ~ 5.5

-20 ~ +70

Chapter 1. Introduction

Condition

300 ~ 500KHz

2.4 ~ 4MHz

300KHz ~ 4.2MHz

Symbol

Topr

1 - 11

Electrical characteristics for low voltage products (Ta=25

¡É

, V

=3V)

Chapter 1. Introduction

Parameter

Symbol

Limits

Unit

Condition

OSC

/48

OSC

Input H current

RESET input L current

K, R input L current

K, R input H voltage

RESET input H voltage

RESET input L voltage

D. R output L voltage

REMOUT output L voltage

REMOUT output H voltage

OSC2 output L voltage

OSC2 output H voltage

D, R output leakage current

Current on STOP mode

Operating supply current 1

Operating supply current 2

System
clock
frequency

K, R input L voltage

OSC

DD2

DD1

STOP

OH3

OL3

OH1

OL2

IL2

IH2

IL1

IH1

IL1

IL2

OL1

2.4

300

2.1

2.25

2.1

-9

-2

0.5

0.3

2.5

0.4

2.5

0.15

-25

-7.5

0.15

Min.

Typ.

Max.

500

4.0

0.9

0.4

0.75

0.9

-50

-16

0.4

MHz

KHz

OSC

=4MHz

OSC

=455KHz

At STOP mode

0UT

, Output off

=70uA

=-8mA

=1mA

VI=GND, Output
off, Pull-Up resistor
provided.

VI=GND

VI=V

=100uA

KHz version

MHz version

* I

DD1

, I

DD2

, is measured at RESET mode.

1 - 12

Parameter

Electrical characteristics (Ta=25

¡É

, V

=5V)

Symb

Limits

Unit

Condition

OSC

Input H current

RESET input L current

K, R input L current

K, R input H voltage

RESET input H voltage

RESET input L voltage

D. R output L voltage

REMOUT output L voltage

REMOUT output H voltage

OSC2 output L voltage

OSC2 output H voltage

D, R output leakage current

Current on STOP mode

Operating supply current

System
clock
frequency

K, R input L voltage

OSC

STOP

OH3

OL3

OH1

OL2

IL2

IH2

IL1

IH1

IL1

IL2

OL1

0.3

-1.0

0.75*V

0.7*V

-9

-2

Min.

Typ.

Max.

4.2

0.9

0.4

0.25*V

0.3*V

-150

-20

0.4

MHz

At RESET mode

At STOP mode

0UT

, Output off

=-70uA

=70uA

=-8mA

=2mA

VI=GND, Output
off, Pull-Up resistor
provided.

VI=GND

VI=V

=100uA

WIDE version

Chapter 1. Introduction

2 - 1

CHAPTER 2. Architecture

BLOCK DESCRIPTION

Program Memory (EPROM)

The GMS34XXXT series can incorporate maximum 1,024 words (64 words

¡¿

pages

¡¿

8bits) for program memory. Program counter PC (A0~A5) and page

address register (A6~A9) are used to address the whole area of program
memory having an instruction (8bits) to be next executed.
The program memory consists of 64 words on each page, and thus each page
can hold up to 64 steps of instructions.
The program memory is composed as shown below.

0 1

2 3

4 5

6 7

Program counter (PC)

Page address register (PA)

Page buffer (PB)

(Level "1")

(Level "2")

(Level "3")

(PSR)

(SR)

Stack register

Page 0

Page 1

Page 2

Page 15

A0~A5

A6~A9

Program capacity (pages)

Fig 2-1 Configuration of Program Memory

Chapter 2. Architecture

2 - 2

EPROM Address Register

The following registers are used to address the EPROM.

· Page address register (PA) :

Holds EPROM's page number (0~Fh) to be addressed.

· Page buffer register (PB) :

Value of PB is loaded by an LPBI command when newly addressing a page.
Then it is shifted into the PA when rightly executing a branch instruction (BR)
and a subroutine call (CAL).

· Program counter (PC) :

Available for addressing word on each page.

· Stack register (SR) :

Stores returned-word address in the subroutine call mode.

(1) Page address register and page buffer register :

Address one of pages #0 to #15 in the EPROM by the 4-bit binary counter.
Unlike the program counter, the page address register is usually unchanged
so that the program will repeat on the same page unless a page changing
command is issued. To change the page address, take two steps such as
(1) writing in the page buffer what page to jump (execution of LPBI) and
(2) execution of BR or CAL, because instruction code is of eight bits so
that page and word can not be specified at the same time.
In case a return instruction (RTN) is executed within the subroutine that has
been called in the other page, the page address will be changed at the
same time.

(2) Program counter :

This 6-bit binary counter increments for each fetch to address a word in the
currently addressed page having an instruction to be next executed.
For easier programming, at turning on the power, the program counter is
reset to the zero location. The PA is also set to "0". Then the program
counter specifies the next EPROM address in random sequence.
When BR, CAL or RTN instructions are decoded, the switches on each step
are turned off not to update the address. Then, for BR or CAL, address
data are taken in from the instruction operands (a

to a

), or for RTN, and

address is fetched from stack register No. 1.

(3) Stack register :

This stack register provides two stages each for the program counter (6
bits) and the page address register (4bits) so that subroutine nesting can be
made on two levels.

Chapter 2. Architecture

2 - 3

Data memory (RAM)

Up to 32 nibbles (16 words

¡¿

2pages

¡¿

4bits) is incorporated for storing data.

The whole data memory area is indirectly specified by a data pointer (X,Y). Page
number is specified by zero bit of X register, and words in the page by 4 bits in
Y-register. Data memory is composed in 16 nibbles/page. Figure 2-2 shows the
configuration.

Output port

Y-register (Y)

X-register (X)

D9 R0

R3 REMOUT

Page 0

Page 1

A0~A3

Data memory page (0~1)

X-register (X)

X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is only
used for selecting of D8~D9 with value of Y-register

Fig 2-2 Composition of Data Memory

X1=1

X1=0

Y=0

Y=1

Table 2-1 Mapping table between X and Y register

Chapter 2. Architecture

2 - 4

Y-register (Y)

Y-register has 4 bits. It operates as a data pointer or a general-purpose register.
Y-register specifies and address (a

) in a page of data memory, as well as it

is used to specify an output port. Further it is used to specify a mode of carrier
signal outputted from the REMOUT port. It can also be treated as a general-
purpose register on a program.

Accumulator (A

)

The 4-bit register for holding data and calculation results.

Arithmetic and Logic Unit (ALU)

In this unit, 4bits of adder/comparator are connected in parallel as it's main
components and they are combined with status latch and status logic (flag.)

(1) Operation circuit (ALU) :

The adder/comparator serves fundamentally for full addition and data
comparison. It executes subtraction by making a complement by processing
an inversed output of A

+1)

(2) Status logic :

This is to bring an ST, or flag to control the flow of a program. It occurs when
a specified instruction is executed in three cases such as overflow or
underflow in operation and two inputs unequal.

Chapter 2. Architecture

2 - 5

State Counter (SC)

A fundamental machine cycle timing chart is shown below. Every instruction is
one byte length. Its execution time is the same. Execution of one instruction
takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total).
Virtually these two cycles proceed simultaneously, and thus it is apparently
completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN
instructions is normal execution time since they change an addressing
sequentially. Therefore, the next instruction is prefetched so that its execution
is completed within the fetch cycle.

T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6

Fetch cycle N

Execute cycle N-1

Execute cycle N

Fetch cycle N-1

Machine

Cycle

Machine

Cycle

Phase

¥°

Phase

¥±

Phase

¥²

Fig. 2-3 Fundamental timing chart

Chapter 2. Architecture

2 - 6

Clock Generator

The GMS34XXXT series has an internal clock oscillator. The oscillator circuit is
designed to operate with an external ceramic resonator. Internal capacitors are
available at KHz version. Oscillator circuit is able to organize by connecting
ceramic resonator to outside.
* It is necessary to connect capacitor to outside in order to change ceramic
resonator, you must refer to a manufacturer`s resonator matching guide.

OSC1

OSC2

OSC1

OSC2

Oscillation Circuit

Operating Frequency

Chapter 2. Architecture

Version

KHz

MHz

WIDE

300KHz ~ 500KHz

2.4MHz ~ 4MHz

300KHz ~ 4.2MHz

Circuit 2

Circuit 1

Internal capacitor

No Internal capacitor

2 - 7

Pulse generator

The following frequency and duty ratio are selected for carrier signal outputted
from the REMOUT port depending on a PMR (Pulse Mode Register) value set in
a program.

REMOUT signal

T=1/f

PUL

= 12/f

OSC

[96/f

OSC

T1/T = 1/2

PMR

T=1/f

PUL

= 12/f

OSC

[96/f

OSC

T1/T = 1/3

T=1/f

PUL

= 8/f

OSC

[64/f

OSC

T1/T = 1/2

T=1/f

PUL

= 8/f

OSC

[64/f

OSC

T1/T = 1/4

T=1/f

PUL

= 11/f

OSC

[88/f

OSC

T1/T = 4/11

No Pulse (same to D0~D9)

* Default value is "0"
* [ ] means the value of "T", when Instruction cycle is f

OSC

/48 in MHz version

Table 2-2 PMR selection table

T=1/f

PUL

= 12/f

OSC

[96/f

OSC

T1/T = 1/4

Chapter 2. Architecture

No pulse (same to D0 ~ D9)

2 - 8

Initial Reset Circuit

RESET pin must be down to "L" more than 4 machine cycle by outside
capacitor or other for power on reset.
The mean of 1 machine cycle is 6/f

OSC

or 48/f

OSC

, however, operating voltage

must be in recommended operating conditions, and clock oscillating stability.
* It is required to adjust C value depending on rising time of power supply.

(Example shows the case of rising time shorter than 10ms.)

RESET

0.1uF

Chapter 2. Architecture

Watch Dog Timer (WDT)

Watch dog timer is organized binary of 14 steps. The signal of f

OSC

/6 cycle comes

in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
The overflow time is 6

¡¿

OSC

(108.026ms at f

OSC

=455KHz.)

¡¿

OSC

(108.026ms at f

OSC

= 3.64MHz)

Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR) or / and REMOUT port HIGH(Y-reg=8, So instruction execution).

* It is constantly reset in STOP mode. When STOP is released, counting is
restarted. (Refer to 2-9 STOP function>)

Binary counter
(14 steps)
RESET (edge-trigger)

OSC

/6 or f

OSC

/48

CPU reset

Reset
by instruction

REMOUT
output

2 - 9

STOP Operation

Stop mode can be achieved by STOP instructions.

In stop mode :

1. Oscillator is stopped, the operating current is low.

2. Watch dog timer is reset, D8~D9 output and REMOUT output are "L".

3. Part other than WDT, D8~D9 output and REMOUT output have a value before

come into stop mode.

Stop mode is released when one of K or R input is going to "L".

1. State of D0~D7 output and REMOUT output is return to state of before stop mode

is achieved.

2. After 1,024

¡¿

8 enable clocks for stable oscillating, First instruction start to operate.

3. In return to normal operation, WDT is counted from zero again.

But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction
is same to NOP instruction.

Port Operation

Value of X-reg

0 or 1

0 ~ 7

S0 : D(Y)

¡ç

R0 : D(Y)

¡ç

Operation

0 or 1

REMOUT port repeats "H" and "L" in pulse
frequency. (When PMR = 5, it is fixed at "H")
S0 : REMOUT(PMR)

¡ç

R0 : REMOUT(PMR)

¡ç

0 or 1

S0 : D0 ~ D9

¡ç

1 (High-Z)

R0 : D0 ~ D9

¡ç

0 or 1

A ~ D

S0 : R(Y-Ah)

¡ç

R0 : R(Y-Ah)

¡ç

0 or 1

S0 : R0 ~ R3

¡ç

R0 : R0 ~ R3

¡ç

0 or 1

S0 : D0 ~ D9

¡ç

1, R0 ~ R3

¡ç

R0 : D0 ~ D9

¡ç

0, R0 ~ R3

¡ç

2 or 3

S0 : D(8)

¡ç

R0 : D(8)

¡ç

2 or 3

S0 : D(9)

¡ç

R0 : D(9)

¡ç

Chapter 2. Architecture

3 - 1

Chapter 3. Instruction

CHAPTER 3. Instruction

Instruction Table

The GMS34XXXT series provides the following 43 basic instructions.

Category

LAY

LYA

LAZ

Mnemonic

¡ç

Function

¡ç

RAM to

LMA

LMAIY

LYM

M(X,Y)

¡ç

M(X,Y)

¡ç

A, Y

¡ç

Y+1

¡ç

M(X,Y)

LAM

XMA

¡ç

M(X,Y)

¡ê

M(X,Y)

Immediate

LYI i

LMIIY i

LXI n

¡ç

M(X,Y)

¡ç

i, Y

¡ç

Y+1

¡ç

RAM Bit

Manipulation

SEM n

REM n

TM n

M(n)

¡ç

M(n)

¡ç

TEST M(n) = 1

ROM

Address

BR a

CAL a

RTN

if ST = 1 then Branch

if ST = 1 then Subroutine call

Return from Subroutine

LPBI i

¡ç

Arithmetic

¡ç

A + M(X,Y)

¡ç

M(X,Y) - A

¡ç

M(X,Y) + 1

¡ç

M(X,Y) - 1

¡ç

A + 1

¡ç

Y + 1

¡ç

A - 1

3 - 2

Chapter 3. Instruction

Category

Arithmetic

EORM

NEGA

Mnemonic

¡ç

Y - 1

Function

¡ç

A + M (X,Y)

¡ç

A + 1

Comparison

ALEM

ALEI i

TEST A

¡Â

M(X,Y)

TEST A

¡Â

MNEZ

YNEA

TEST M(X,Y)

¡Á

TEST Y

¡Á

YNEI i

KNEZ

TEST Y

¡Á

TEST K

¡Á

RNEZ

TEST R

¡Á

Input /

Output

LAK

LAR

¡ç

Output(Y)

¡ç

Output(Y)

¡ç

Control

WDTR

STOP

Watch Dog Timer Reset

Stop operation

LPY

NOP

PMR

¡ç

No operation

Note) i = 0~f, n = 0~3, a = 6bit PC Address

*1 Column ST indicates conditions for changing status. Symbols have the following
meanings

S : On executing an instruction, status is unconditionally set.
C : Status is only set when carry or borrow has occurred in operation.
B : Status is only set when borrow has not occurred in operation.
E : Status is only set when equality is found in comparison.
N : Status is only set when equality is not found in comparison.
Z : Status is only set when the result is zero.

*2 Operation is settled by a value of Y-register.

4 - 2

Port define

Chapter 4. EPROM

NMOS open drain I/O
in EPROM mode

* Undefined ports in this table are N.C (No Connection)

Port Name

VDD

RESETB

OSC1

User Mode

3.0V

Reset (0, 3.0V)

Clock input

K0(Input)

K1(Input)

K2(Input)

K3(Input)

EPROM Mode

6.0V

Vpp (0, 12.5V)

Clock input

Read / Write Control
Address / Data Control

D0(Output)

D1(Output)

D2(Output)

D3(Output)

D4(Output)

D5(Output)

Da0

Da4

Lock bit output

GND

Da1

Da5

Da2

Da6

Da3

Da7

Programming data

Device Name

GMS34004TK

ROM Size

512bytes

Blank data

(HEX)

Lock bit

Yes

Device address

0000 ~ 01FF

File address

0000 ~ 01FF

GMS34112TK

1,024bytes

Yes

0000 ~ 03FF

GMS34140TK

1,024bytes

Yes

0000 ~ 03FF

- If lock bit is set, the EPROM of the device can not be read, because output is always FF.
- Input file : Intel Hexa format ( *.RHX )

4 - 3

Chapter 4. EPROM

Write / Read data conversion

- You must change MSB ~ LSB

¡ê

LSB ~ MSB.

- Example

Hex

Binary (MSB~LSB)

0010 1100

1110 0100

1000 1101

Write

Read

Hex

Binary (MSB~LSB)

0011 0100

0010 0111

1011 0001

File / buffer data

Device (D3 ~ D0)

Checksum

- It is calculated from the Buffer of the programmer.
- Address range is the same as device address.
- Calculate method is the same as normal EPROM devices (ex:27C128, 256 etc)

Programming control

- OSC1 & RESETB control OTP device, so you must count OSC1 clocks in every state.
- K ports control the internal state of the OTP device(ex: Read, Write...).
- D5~D0 ports are NMOS open drain I/O in EPROM mode.

It must be pulled up by resistors (about 4.7~ 47K ohm).

- The frequency rate of the OSC1 clock is 10KHz ~ 500KHz.

You can hold OSC1 HIGH or LOW state when you need.

Item

Range

VCC

0 ~ 6.0V

¡¾

0.25V

Programming DC specification

RESETB

0 ~ 12.5V

¡¾

0.5V

K-port

D-port

0 ~ 0.2VCC(Low)

0.8VCC ~ VCC (High)

4 - 4

Chapter 4. EPROM

EPROM read mode (1/2)

AL : Low Address (A4~0) Input Latch

OH : High Data (D7~4) Output

OL : Low Data (D3~0) Output

AH : High Address (A9~5) Input Latch

For device verify or read.
If you set Lock bit, output data is always FF.

* Note : 1. AH, AL, DH, DL Inputs released at 100~200nS after OSC rising edge and

width is 1OSC cycle ( if OSC is 500KHz, width is 2uS ).

RESETB

OSC

12.5V

CK1

CK2

CK3

K3 ~ K0

0110

D4 ~ D0

0000

VCC

1101

0000

1101

0000

1101

0000

1101

Addr. 0

Addr. 1

Addr. 2

Addr. 3

2us at 500KHz

¨ç ¨è

¨õ

¨ô

14.5clocks

EPROM read mode (2/2)

START

END

¨ç

Reset

(Set EPROM read mode)

Address=First address

¨è

Set address

¨é

Read data

Address ++

Address > Last address

RESETB=0V

VCC=0V

4 - 5

Chapter 4. EPROM

EPROM write mode (1/2)

RESETB

OSC

12.5V

CK1

CK2

CK3

K3 ~ K0

PGM Write ( 0110 )

D4 ~ D0

0000

1101

VCC

1000

1110

0000

1000

10times Repeat

12us X 10 = 120us

Verify

Next Write

AH : High bit Address Input Latch

AL : Low bit Address Input Latch

DH : High bit Data Input Latch

DL : Low bit Data Input Latch

OH : High bit Data Output

OL : Low bit Data Output

9.5V

* Note : 1. AH, AL, DH, DL Inputs are released at 100~200nS after OSC rising edge and

width is 1OSC cycle ( if OSC is 500KHz, width is 2uS ).

2us at 500KHz

¨ç ¨è

¨õ

¨ô

14.5clocks

EPROM write mode (2/2)

Fail

Yes

Pass

Fail

Pass

Yes

START

¨ç

Reset

(Set EPROM write mode)

Address=First address

¨è

Set address & data

¨é

EPROM write

Repeat until near 100uS.

When 500KHz OSC1, repeat 10

times (12uS*10=120uS)

RESETB=0V

VCC=0V

END

Count=0

Count ++

¨ê

Verify

Count=25?

Device fail

Address ++

¨é

EPROM write

(Write one more time)

Address > Last address

EPROM read mode

Verify all

RESETB=0V

VCC=0V

Device OK

4 - 11

Port define

NMOS open drain I/O
in EPROM mode

* Undefined ports in this table are N.C (No Connection)

Port Name

VDD

RESETB

OSC1

User Mode

3.0V

Reset (0, 3.0V)

Clock input

K0(Input)

K1(Input)

K2(Input)

K3(Input)

EPROM Mode

6.0V

Vpp (0, 12.5V)

Clock input

Read / Write Control
Address / Data Control

D0(Output)

D1(Output)

D2(Output)

D3(Output)

D4(Output)

D5(Output)

Da0

Da4

Lock bit output

GND

Da1

Da5

Da2

Da6

Da3

Da7

Programming data

Device Name

GMS34004TK

ROM Size

512bytes

Blank data

(HEX)

Lock bit

Yes

Device address

0000 ~ 01FF

File address

0000 ~ 01FF

GMS34112TK

1,024bytes

Yes

0000 ~ 03FF

GMS34140TK

1,024bytes

Yes

0000 ~ 03FF

- If lock bit is set, the EPROM of the device can not be read, because output is always FF.
- Input file : Intel Hexa format ( *.RHX )

Chapter 4. EPROM

4 - 12

Write / Read data conversion

- You must change MSB ~ LSB

¡ê

LSB ~ MSB.

- Example

Hex

Binary (MSB~LSB)

0010 1100

1110 0100

1000 1101

Write

Read

Hex

Binary (MSB~LSB)

0011 0100

0010 0111

1011 0001

File / buffer data

Device (D3 ~ D0)

Checksum

- It is calculated from the Buffer of the programmer.
- Address range is the same as device address.
- Calculate mathod is the same as normal EPROM devices (ex:27C128, 256 etc)

Programming control

It must be pulled up by resistors (about 4.7~ 47K ohm).

- The frequency rate of the OSC1 clock is 10KHz ~ 500KHz.

You can hold OSC1 HIGH or LOW state when you need.

Item

Range

VCC

0 ~ 6.0V

¡¾

0.25V

Programming DC specification

RESETB

0 ~ 12.5V

¡¾

0.5V

K-port

D-port

0 ~ 0.2VCC(Low)

0.8VCC ~ VCC (High)

Chapter 4. EPROM

4 - 15

EPROM write mode (3/4)

EPROM write mode (4/4)

RESETB

OSC1

K3 ~ K0

D4 ~ D0

1101

12.5V

D3~D0

D7~D4

Verify

A9~A5

A4~A0

D3~D0

D7~D4

0000

1000

High bit
Instruction
Latch

Low bit
Instruction
Latch

High bit
Address
Latch

Low bit
Address
Latch

High bit
Instruction
Output

Low bit
Instruction
Output

Next Address Input

Next Data Input

VCC

Data
Strobe
point
5Clock

Fail

Yes

Pass

Fail

Pass

Yes

START

¨ç

Reset

(Set EPROM write mode)

Address=First address

¨è

Set address & data

¨é

EPROM write

Repeat until near 100uS.

When 4MHz OSC1, repeat 10

times (12uS*10=120uS)

RESETB=0V

VCC=0V

END

Count=0

Count ++

¨ê

Verify

Count=25?

Device fail

Address ++

¨é

EPROM write

(Write one more time)

Address > Last address

EPROM read mode

Verify all

RESETB=0V

VCC=0V

Device OK

Chapter 4. EPROM

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS34140TW

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS34140TW