Revision 1.1

Published by MCU Application Team in HYNIX Semiconductor Inc.
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Table of Contents

Chapter 1

GMS36XXX

Description

........................................................1-1

Features

.......................................................1-1

Block diagram

.......................................................1-2

Pin assignment

.......................................................1-3

Pin description

.......................................................1-4

Pin circuit

.......................................................1-5

Port operation

.......................................................1-7

Optional features

.......................................................1-7

Electrical characteristics

.......................................................1-8

Chapter 2

GMS37XXX

Description

........................................................2-1

Features

.......................................................2-1

Block diagram

.......................................................2-2

Pin assignment

.......................................................2-3

Pin description

.......................................................2-4

Pin circuit

.......................................................2-5

Port operation

.......................................................2-7

Optional features

.......................................................2-7

Electrical characteristics

.......................................................2-8

Chapter 3

PACKAGE DIMENSIONS

Chapter 4

FUNCTIONAL DESCRIPTION

Program memory (ROM)

.......................................................4-1

ROM address register

.......................................................4-2

Data memory (RAM)

.......................................................4-3

X-register (X)

.......................................................4-3

Y-register (Y)

.......................................................4-4

Accumulator (Acc)

.......................................................4-4

Arithmetic and Logic Unit (ALU)

.......................................................4-4

State Counter (SC)

.......................................................4-5

Clock generator

.......................................................4-6

Pulse generator

.......................................................4-7

Reset operation

.......................................................4-8

Watch Dog Timer (WDT)

......................................................4-10

Stop operation

......................................................4-11

Table of Contents

Table of Contents

Chapter 5

INSTRUCTION

Instruction format

......................................................5-1

Instruction table

......................................................5-2

Details of instruction system

......................................................5-4

Chapter 6

APPLICATION

Guideline for S/W

......................................................6-1

GMS36112 Circuit diagram

......................................................6-2

GMS37112 Circuit diagram

......................................................6-3

Truth Table for example program ......................................................6-4

Output waveform of uPD6121G ......................................................6-5

Example program-uPD6121G ......................................................6-6
Reference to GMS36XXXT B/D

.....................................................6-12

Reference to GMS37XXXT B/D .....................................................6-13

Chapter 7

GMS36XXXT

Description

........................................................7-1

Features

.......................................................7-1

Pin description

.......................................................7-2

Stop operation

.......................................................7-3

Electrical characteristics

.......................................................7-4

Chapter 8

GMS37XXXT

Description

........................................................8-1

Features

.......................................................8-1

Pin description

.......................................................8-2

Stop operation

.......................................................8-3

Electrical characteristics

.......................................................8-4

Chapter 9

EPROM

Mode define

.......................................................9-1

Port define for GMS36XXXT

.......................................................9-1

Port define for GMS37XXXT

.......................................................9-2

AC/DC timing requirements for program / read mode

...................9-3

Program / verify timing diagrams in kHz version

...................9-4

Program / verify timing diagrams in MHz version

...................9-8

Caution when programming

..................9-14

1-1

1. GMS36XXX

Description

The GMS36XXX series are remote control transmitter which uses CMOS technology.

This enables transmission code outputs of different configurations, multiple custom code

output, and double push key output for easy fabrication.

The GMS36XXX series are suitable for remote control of TV, VCR, FANS, Air-

conditioners, Audio Equipment, Toys, Games etc.

Features

Program memory

: 1,024 bytes for GMS36004/112/140

Data memory : 32

4 bits

43 types of instruction set

3 levels of subroutine nesting

Operating frequency : 300kHz ~ 1MHz at kHz version

2.4MHz ~ 4MHz at MHz version

Instruction cycle :

OSC

/6 at kHz version

OSC

/48 at MHz version

CMOS process (Single 3.0V power supply)

Stop mode (Through internal instruction)

Released stop mode by key input (Masked option)

Built in Power-on Reset circuit

Built in Low Voltage Detection circuit

Built in capacitor for ceramic oscillation circuit at kHZ version

Built in a watch dog timer (WDT)

Built in transistor for I.R LED Drive : I

=210mA at V

=3V and V

=0.3V

Low operating voltage : 2.0 ~ 3.6V (at 300kHz ~ 4MHz)

Chapter 1. GMS36XXX

Series

GMS36004

GMS36112

GMS36140

Program memory

1,024

Data memory

I/O ports

Input ports

Output ports

6 (D0~D5)

10 (D0~D9)

Package

16DIP/SOP

20DIP/SOP/SSOP

24Skinny DIP/SOP

Table 1-1 GMS36XXX series members

1-2

Block Diagram

Fig 1-1 Block Diagram (In case of GMS36140)

RAM

16word x

2page x 4bit

Y-Reg

ACC

R-Latch

X-Reg

MUX

08;

Instruction

Decoder

Power-on

Reset

Watchdog

timer

OSC1 OSC2

K0 ~ K3

R0 ~ R3

D0 ~ D9

REMOUT

VDD GND

OSC

Control Signal

PGND

Low-Voltage

Detection

D-Latch

Program counter

3-level

Stack

ROM

64word

16page

8bit

I.R. LED
Drive Tr.

Pulse

Generator

ALU

RAM

Word

Selector

Chapter 1. GMS36XXX

1-3

Pin Assignment

Fig 1-2 GMS36004 Pin Assignment

(16DIP/SOP)

Fig 1-3 GMS36112 Pin Assignment

(20DIP/SOP/SSOP)

Fig 1-4 GMS36140 Pin Assignment

(24Skinny-DIP/SOP)

Chapter 1. GMS36XXX

GND

OSC1

OSC2

VDD

REMOUT

PGND

GND

OSC1

OSC2

VDD

REMOUT

PGND

GND

OSC1

OSC2

VDD

REMOUT

PGND

1-4

Pin

Function

I/O

Connected to 2.0~ 3.6V power supply

Connected to 0V power supply.

K0 ~ K3

Input

GND

VDD

Each can be set and reset independently.

The output is the structure of N-channel-open-drain.

High current output port driving I.R. LED.

The output is in the form of N-channel-open-drain.

D0 ~ D9

Output

R0 ~ R3

I/O

REMOUT

Output

Oscillator input. Input to the oscillator circuit and connection point for
ceramic resonator.

Internal capacitors available at kHz version.
A feedback resistor is internally connected between this pin and
OSC2.

Connect a resonator between this pin and OSC1.

OSC1

Input

OSC2

Output

High current Tr. ground pin. (connected to GND)

High current output Tr. is connected between this pin and
REMOUT.

PGND

Chapter 1. GMS36XXX

Pin Description

4-bit input port with built in pull-up resistor.
STOP mode is released by "L" input of each pin.(masked option)

4-bit I/O port. (Input mode is set only when each of them output "H".)

In outputting, each can be set and reset independently(or at once.)

The output is in the form of C-MOS.
Pull-up resistor and STOP release mode can be respectively selected

as masked option for each pin. (It is released by `'L'' input at STOP.)

1-7

Port Operation

Value of X-reg

0 or 1

SO : D(Y)

1 (High-Z)

RO : D(Y)

Operation

REMOUT port repeats `'L'' and `'H'' in pulse
frequency. (when PMR = 5, it is fixed at `'L'' )
SO : REMOUT (PMR)

RO : REMOUT (PMR)

1 (High-Z)

Value of Y-reg

0 ~ 7

0 or 1

SO : D0 ~ D9

1 (High-Z)

RO : D0 ~ D9

0 or 1

SO : R(Y-Ah)

RO : R(Y-Ah)

A ~ D

0 or 1

SO : R0 ~ R3

RO : R0 ~ R3

0 or 1

SO : D0 ~ D9

1 (High-Z), R0 ~ R3

RO : D0 ~ D9

R0 ~ R3

2 or 3

SO : D(8)

1 (High-Z)

RO : D(8)

2 or 3

SO : D(9)

1 (High-Z)

RO : D(9)

Optional Features

The GMS36XXX series offer the following optional features.

Theses options are masked.

I/O terminals having pull-up resistor : R0 ~ R3

Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3.

Output form at STOP mode

D0 ~ D9 : `'

L'' or keep before stop mode.

Theses options are offered default.

Ceramic oscillation circuit contained (or not contained)

[ This option is not available for MHz Ceramic oscillator. ]

Instruction cycle selection :

T = 48 / f

OSC

or 6 / f

OSC

Chapter 1. GMS36XXX

1-8

Electrical Characteristics

Absolute maximum ratings (Ta = 25

)

Recommended operating condition

Parameter

Supply Voltage

Power dissipation

Storage temperature range

Input voltage

Output voltage

Unit

Symbol

Tstg

OUT

Max. rating

-0.3 ~ 5.0

700 *

-55 ~ 125

-0.3 ~ V

+0.3

-0.3 ~ V

+0.3

* Thermal derating above 25

: 6mW per degree

rise in temperature.

Parameter

Supply Voltage

Operating temperature

Symbol

Topr

Condition

300KHz ~ 4MHz

Rating

2.0 ~ 3.6

-20 ~ +70

Unit

Chapter 1. GMS36XXX

1-9

Electrical characteristics (Ta=25

, V

= 3V)

*1 Refer to

Fig.1-5 I

OL2

vs. V

OL2

Graph

*2 Refer to

Fig.1-6 I

OL1

vs. V

OL1

Graph

*3 I

DD1

, I

DD2

, is measured at RESET mode.

Symbol

Limits

Min.

Typ.

Max.

Unit

-1

140

300

PU1

140

300

PU2

0.3

1.0

3.0

2.1

IH1

0.9

IL1

0.15

0.4

OL2

0.4

0.9

OL3

2.1

2.5

OH3

170

210

250

OLK1

OLK2

STP

0.2

1.0

DD1

0.5

1.5

DD2

300

1000

kHz

OSC

2.4

MHz

OSC

OL1

OSC

/48

Parameter

Input H current

Input L current

K, R Input H voltage

K, R Input L voltage

D, R Output L voltage

OSC2 Output L voltage

OSC2 Output H voltage

REMOUT Output L current

REMOUT leakage current

D, R Output leakage current

Current on STOP mode

Operating Supply current 1

Operating Supply current 2

System
colck
frequency

K Pull-up Resistance

R Pull-up Resistance

Feedback Resistance

Condition

= V

, R having no Pull-up

= GND, R having no Pull-up

OL2

= 3mA

OL3

= 40uA (kHz) , 150uA(MHz)

OH3

= -40uA (kHz), -150uA(MHz)

OL1

= 0.3V

OUT

= V

, Output off

OUT

= V

, Output off

At STOP mode

OSC

= 455kHz

OSC

= 4MHz

kHz Version

MHz Version.

= GND

= GND, Output off

OSC1

= GND, V

OSC2

= GND

Chapter 1. GMS36XXX

2-1

2. GMS37XXX

Description

The GMS37XXX series are remote control transmitter which uses CMOS technology.

This enables transmission code outputs of different configurations, multiple custom code

output, and double push key output for easy fabrication.

The GMS37XXX series are suitable for remote control of TV, VCR, FANS, Air-

conditioners, Audio Equipment, Toys, Games etc.

It is possible to structure the 8 x 7 key matrix for GMS37112, and the 4 x 7 key matrix

for GMS37004.

Features

Program memory

: 1,024 bytes for GMS37004/112/140

Data memory : 32

4 bits

43 types of instruction set

3 levels of subroutine nesting

Operating frequency : 300kHz ~ 1MHz at kHz version

2.4MHz ~ 4MHz at MHz version

Instruction cycle :

OSC

/6 at kHz version

OSC

/48 at MHz version

CMOS process (Single 3.0V power supply)

Stop mode (Through internal instruction)

Released stop mode by key input (Masked option)

Built in Power-on Reset circuit

Built in Low Voltage Detection circuit

Built in capacitor for ceramic oscillation circuit at kHZ version

Built in a watch dog timer (WDT)

Low operating voltage : 2.0 ~ 3.6V (at 300kHz ~ 4MHz)

Chapter 2. GMS37XXX

Table 2-1 GMS37XXX series members

Series

GMS37004

GMS37112

GMS37140

Program memory

1,024

Data memory

I/O ports

Input ports

Output ports

7 (D0~D6)

10 (D0~D9)

Package

16DIP/SOP

20DIP/SOP/SSOP

24Skinny DIP/SOP

2-2

Block Diagram

Fig 2-1 Block Diagram (In case of GMS37140)

RAM

16word x

2page x 4bit

Y-Reg

ACC

R-Latch

X-Reg

MUX

08;

Instruction

Decoder

Power-on

Reset

Watchdog

timer

OSC1 OSC2

K0 ~ K3

R0 ~ R3

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

REMOUT

VDD GND

OSC

Control Signal

Low-Voltage

Detection

D-Latch

Program counter

3-level

Stack

ROM

64word

16page

8bit

Pulse

Generator

ALU

RAM

Word

Selector

* NC : No connection

Chapter 2. GMS37XXX

2-3

Pin Assignment

Fig 2-2 GMS37004 Pin Assignment

(16DIP/SOP)

Fig 2-3 GMS37112 Pin Assignment

(20DIP/SOP/SSOP)

Fig 2-4 GMS37140 Pin Assignment

(24Skinny-DIP/SOP)

Chapter 2. GMS37XXX

GND

OSC1

OSC2

K3/Vpp

VDD

REMOUT

GND

OSC1

OSC2

K3/Vpp

VDD

REMOUT

GND

OSC1

OSC2

K3/Vpp

VDD

REMOUT

2-4

Pin Description

Pin

Function

I/O

Connected to 2.0~ 3.6V power supply

Connected to 0V power supply.

4-bit input port with built in pull-up resistor.

STOP mode is released by "L" input of each pin. ( masked option)

K0 ~ K3

Input

GND

VDD

Each can be set and reset independently.

The output is the structure of N-channel-open-drain.

4-bit I/O port. (Input mode is set only when each of them output "H".)

In outputting, each can be set and reset independently(or at once.)

The output is in the form of C-MOS.

Pull-up resistor and STOP release mode can be respectively selected
as masked option for each pin. (It is released by "L" input at STOP)

High current output port. The output is in the form of CMOS.

The state of large current on is "H".

D0 ~ D9

Output

R0 ~ R3

I/O

REMOUT

Output

Oscillator input. Input to the oscillator circuit and connection point for
ceramic resonator.

Internal capacitors available at kHz version.

A feedback resistor is internally connected between this pin and OSC2.

Connect a resonator between this pin and OSC1.

OSC1

Input

OSC2

Output

Chapter 2. GMS37XXX

2-7

Port operation

Value of X-reg

0 or 1

SO : D(Y)

1 (High-Z)

RO : D(Y)

Operation

Value of Y-reg

0 ~ 7

REMOUT port repeats `'H'' and `'L'' in pulse
frequency. (when PMR = 5, it is fixed at `'H'' )
SO : REMOUT (PMR)

RO : REMOUT (PMR)

0 or 1

SO : D0 ~ D9

1 (High-Z)

RO : D0 ~ D9

0 or 1

SO : R(Y-Ah)

RO : R(Y-Ah)

A ~ D

0 or 1

SO : R0 ~ R3

RO : R0 ~ R3

0 or 1

SO : D0 ~ D9

1 (High-Z), R0 ~ R3

RO : D0 ~ D9

R0 ~ R3

2 or 3

SO : D(8)

1 (High-Z)

RO : D(8)

2 or 3

SO : D(9)

1 (High-Z)

RO : D(9)

Optional Features

The GMS37XXX series offer the following optional features.

Theses options are masked.

I/O terminals having pull-up resistor : R0 ~ R3

Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3.

Output form at STOP mode

D0 ~ D9 :

`'L'' or keep before stop mode.

Theses options are offered default.

Ceramic oscillation circuit contained (or not contained)

[ This option is not available for MHz Ceramic oscillator. ]

Instruction cycle selection :

T = 48 / f

OSC

or 6 / f

OSC

Chapter 2. GMS37XXX

2-8

Electrical Characteristics

Absolute maximum ratings (Ta = 25

)

Recommended operating condition

Parameter

Supply Voltage

Power dissipation

Storage temperature range

Input voltage

Output voltage

Unit

Symbol

Tstg

OUT

Max. rating

-0.3 ~ 5.0

700 *

-55 ~ 125

-0.3 ~ V

+0.3

-0.3 ~ V

+0.3

* Thermal derating above 25

: 6mW per degree

rise in temperature.

Parameter

Supply Voltage

Operating temperature

Symbol

Topr

Condition

300KHz ~ 4MHz

Rating

2.0 ~ 3.6

-20 ~ +70

Unit

Chapter 2. GMS37XXX

2-9

Electrical characteristics (Ta=25

, V

= 3V)

*1 Refer to

Fig.2-5 I

OL2

vs. V

OL2

Graph

*2 Refer to

Fig.2-6 I

OL1

vs. V

OL1

Graph

*3 Refer to

Fig.2-7 I

OH1

vs. V

OH1

Graph

*4 I

DD1

, I

DD2

, is measured at RESET mode.

Symbol

Limits

Min.

Typ.

Max.

Unit

-1

140

300

PU1

140

300

PU2

0.3

1.0

3.0

2.1

IH1

0.9

IL1

0.15

0.4

OL2

0.4

0.9

OL3

2.1

2.5

OH3

2.2

-5

-15

-30

OLK2

STP

0.2

1.0

DD1

0.5

1.5

DD2

300

1000

kHz

OSC

2.4

MHz

OSC

OL1

OSC

/48

Parameter

Input H current

Input L current

K, R Input H voltage

K, R Input L voltage

D, R Output L voltage

OSC2 Output L voltage

OSC2 Output H voltage

REMOUT Output L current

REMOUT Output H current

D, R Output leakage current

Current on STOP mode

Operating Supply current 1

Operating Supply current 2

System
colck
frequency

K Pull-up Resistance

R Pull-up Resistance

Feedback Resistance

Condition

= V

, R having no Pull-up

= GND, R having no Pull-up

OL2

= 3mA

OL3

= 40uA (kHz), 150uA (MHz)

OH3

= -40uA (kHz), -150uA (MHz)

OL1

= 0.4V

OH1

= 2V

OUT

= V

, Output off

At STOP mode

OSC

= 455kHz

OSC

= 4MHz

kHz Version

MHz Version.

= GND

= GND, Output off

OSC1

= GND, V

OSC2

= GND

Chapter 2. GMS37XXX

OH1

4-1

4. FUNCTIONAL DESCRIPTION

Program Memory (ROM)

The GMS36/37XXX series can incorporate maximum 1,024 words (64 words

pages

8bits) for program memory. Program counter PC (A0~A5) and page

address register (A6~A9) are used to address the whole area of program memory

having an instruction (8bits) to be next executed.

The program memory consists of 64 words on each page, and thus each page

can hold up to 64 steps of instructions.

The program memory is composed as shown below.

Chapter 4. FUNCTIONAL DESCRIPTION

0 1

2 3

4 5

6 7

Program counter (PC)

Page address register (PA)

Page buffer (PB)

(Level "1")

(Level "2")

(Level "3")

(PSR)

(SR)

Stack register

Page 0

Page 1

Page 2

Page 15

A0~A5

A6~A9

Program capacity (pages)

Fig 4-1 Configuration of Program Memory

4-2

ROM Address Register

The following registers are used to address the ROM.

· Page address register (PA) :

Holds ROM's page number (0 ~ Fh) to be addressed.

· Page buffer register (PB) :

Value of PB is loaded by an LPBI command when newly addressing a page.

Then it is shifted into the PA when rightly executing a branch instruction (BR)

and a subroutine call (CAL).

· Program counter (PC) :

Available for addressing word on each page.

· Stack register (SR) :

Stores returned-word address in the subroutine call mode.

(1) Page address register and page buffer register :

Address one of pages #0 to #15 in the ROM by the 4-bit binary counter.

Unlike the program counter, the page address register is usually unchanged so

that the program will repeat on the same page unless a page changing command

is issued. To change the page address, take two steps such as (1) writing in the

page buffer what page to jump (execution of LPBI) and (2) execution of BR or CAL,

because instruction code is of eight bits so that page and word can not be specified

at the same time.

In case a return instruction (RTN) is executed within the subroutine that has been

called in the other page, the page address will be changed at the same time.

(2) Program counter :

This 6-bit binary counter increments for each fetch to address a word in the

currently addressed page having an instruction to be next executed.

For easier programming, at turning on the power, the program counter is

reset to the zero location. The PA is also set to "0". Then the program

counter specifies the next ROM address in random sequence.

When BR, CAL or RTN instructions are decoded, the switches on each step

are turned off not to update the address. Then, for BR or CAL, address

data are taken in from the instruction operands (a

to a

), or for RTN, and

address is fetched from stack register No. 1.

(3) Stack register :

This stack register provides two stages each for the program counter (6bits)

and the page address register (4bits) so that subroutine nesting can be

made on two levels.

Chapter 4. FUNCTIONAL DESCRIPTION

4-3

Data Memory (RAM)

Up to 32 nibbles (16 words

2pages

4bits) is incorporated for storing data.

The whole data memory area is indirectly specified by a data pointer (X,Y). Page

number is specified by zero bit of X register, and words in the page by 4 bits in

Y-register. Data memory is composed in 16 nibbles/page. Figure 2-2 shows the

configuration.

X-register (X)

X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is only

used for selecting of D8 ~ D9 with value of Y-register

X1=1

X1=0

Y=0

Y=1

Table 4-1 Mapping table between X and Y register

Chapter 4. FUNCTIONAL DESCRIPTION

Output port

Y-register (Y)

X-register (X)

D9 R0

R3 REMOUT

Page 0

Page 1

Data memory page (0~1)

Fig 4-2 Composition of Data Memory

4-4

Y-register (Y)

Y-register has 4 bits. It operates as a data pointer or a general-purpose register.

Y-register specifies an address (a

) in a page of data memory, as well as it

is used to specify an output port. Further it is used to specify a mode of carrier

signal outputted from the REMOUT port. It can also be treated as a general-

purpose register on a program.

Accumulator (A

)

The 4-bit register for holding data and calculation results.

Arithmetic and Logic Unit (ALU)

In this unit, 4bits of adder/comparator are connected in parallel as it's main

components and they are combined with status latch and status logic (flag.)

(1) Operation circuit (ALU) :

The adder/comparator serves fundamentally for full addition and data

comparison. It executes subtraction by making a complement by processing

an inversed output of A

+1)

(2) Status logic :

This is to bring an ST, or flag to control the flow of a program. It occurs when

a specified instruction is executed in three cases such as overflow or underflow

in operation and two inputs unequal.

Chapter 4. FUNCTIONAL DESCRIPTION

4-5

State Counter (SC)

A fundamental machine cycle timing chart is shown below. Every instruction is

one byte length. Its execution time is the same. Execution of one instruction

takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total).

Virtually these two cycles proceed simultaneously, and thus it is apparently

completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN

instructions is normal execution time since they change an addressing sequentially.

Therefore, the next instruction is prefetched so that its execution is completed

within the fetch cycle.

Fig. 4-3 Fundamental timing chart

T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6

Fetch cycle N

Execute cycle N-1

Execute cycle N

Fetch cycle N-1

Phase

Machine

Cycle

Machine

Cycle

Chapter 4. FUNCTIONAL DESCRIPTION

4-1

Clock Generator

The GMS36/37XXX series has an internal clock oscillator. The oscillator circuit is

designed to operate with an external ceramic resonator. Internal capacitors are

available at kHz version. Oscillator circuit is able to organize by connecting

ceramic resonator to outside.

* It is necessary to connect capacitor to outside in order to change ceramic resonator,

you must refer to a manufacturer`s resonator matching guide.

Chapter 4. FUNCTIONAL DESCRIPTION

OSC1

OSC2

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n~m`[[p

m`[[

n\hn]hz

a_[s¥

n~ma_[{

ma_[

n\hn]hz

rx~^aZ^b\\]x

^Ya_xs¥

^Yc_xs¥

_Y[[xs¥

qn}^Ya_x~n`

qn}_Y[x~n`

vznp}l

vm}X^Ya_xvp

vm}X^Yc_xvp

vm}X_Y[[xvp

x}ll

n~~[^a_xr[a

n~~[^c_xr[a

n~~[_[[xr[^

x}ll

n~nn^Ya_xr[sa

n~nn^Yc_xr[sa

n~nn_Y[[xr

^Ya_xr

^Yc_xr

_Y[[xr

nz}ppns

n}^Ya_x~

n}^Yc_x~

n}_Y[[x~

* All type have the built-in loading capacitors.

4-7

Pulse Generator

The following frequency and duty ratio are selected for carrier signal outputted

from the REMOUT port depending on a PMR (Pulse Mode Register) value set in

a program.

* Default value is "0"
* [ ] means the value of "T", when Instruction cycle is f

OSC

/48 in MHz version

Table 4-2 PMR selection table

REMOUT signal

T=1/f

PUL

= 12/f

OSC

[96/f

OSC

], T1/T = 1/2

PMR

T=1/f

PUL

= 12/f

OSC

[96/f

OSC

T1/T = 1/3

T=1/f

PUL

= 8/f

OSC

[64/f

OSC

T1/T = 1/2

T=1/f

PUL

= 8/f

OSC

[64/f

OSC

T1/T = 1/4

T=1/f

PUL

= 11/f

OSC

[88/f

OSC

T1/T = 4/11

No Pulse (same to D0 ~ D9)

T=1/f

PUL

= 12/f

OSC

[96/f

OSC

T1/T = 1/4

No pulse (same to D0 ~ D9)

Chapter 4. FUNCTIONAL DESCRIPTION

4-8

Reset Operation

GMS36/37XXX has three reset sources. One is a built-in Power-on reset circuit, another

is a built-in Low VDD Detection circuit, the other is the overflow of Watch Dog Timer. (WDT)

All reset operations are internal in the GMS36/37XXX.

Built-in Power On Reset Circuit

GMS36/37XXX has a built-in Power-on reset circuit consisting of an about 1

Resistor

and a 3pF Capacitor. When the Power-on reset pulse occurs, system reset signal is

latched and WDT is cleared. After the overflow time of WDT (2

x System clock time)

system reset signal is released.

reset

VCC

System
RESETB

About 108msec at
fosc = 455kHz

9''

*1'

&RXQWHU

:'7

6\VWHP

5(6(7%

<GMS36/37XXX>

Fig. 4-4 Power-On Reset Circuit and Timing Chart

Chapter 4. FUNCTIONAL DESCRIPTION

4-9

[Y[

[Y]

[Y_

[Ya

[Yc

\Y[

\Y]

\Y_

\Ya

\Yc

]Y[

]Y]

]Y_

]Ya

]Yc

^Y[

X][

X\[

[

][

w¢ o

xYz n{W }zx

Built-in Low VDD Detection Circuit

GMS36/37XXX has a Low VDD detection circuit.

If VDD become Reset Voltage of Low VDD Detection circuit at active status, system

reset occur and WDT is cleared. After VDD is increased upper Reset Voltage again,

WDT is re-counted and if WDT is overflowed, system reset is released.

Fig. 4-5 Low Voltage Detection diagram

Fig. 4-6 Low Voltage vs Temperature

VDD

Reset Voltage

Internal
RESETB

About 108msec at fosc =455kHz

Chapter 4. FUNCTIONAL DESCRIPTION

4-10

Watch Dog Timer (WDT)

Watch dog timer is organized binary of 14 steps. The signal of f

OSC

/6 cycle comes

in the first step of WDT after WDT reset. If this counter was overflowed, reset

signal automatically come out so that internal circuit is initialized.

The overflow time is 6

OSC

(108.026ms at f

OSC

=455KHz.)

OSC

(108.026ms at f

OSC

= 3.64MHz)

Normally, the binary counter must be reset before the overflow by using reset

instruction (WDTR), Power-on reset pulse or Low VDD detection pulse.

* It is constantly reset in STOP mode. When STOP is released, counting is

restarted.

OSC

/6 or f

OSC

/48

CPU reset

Reset
by instruction

Power-On Reset

Low VDD Detection

Binary counter(14 steps)

RESET (edge-trigger)

Fig. 4-7 Block Diagram of Watch-dog Timer

Chapter 4. FUNCTIONAL DESCRIPTION

4-11

STOP Operation

Stop mode can be achieved by STOP instructions.

In stop mode :

1. Oscillator is stopped, the operating current is low.

2. Watch dog timer is reset, REMOUT output is disable

(High-Z at GMS36XXX(T) , "L" at GMS37XXX(T))

3. Part other than WDT and REMOUT output have a value before

come into stop mode.

* But the state of D0 ~ D9 output in stop mode is able to choose as masked option.

"L" output or same level before come into stop mode.

The Function to release stop mode is able to choose each bit of K or R input as masked option.

Stop mode is released when one of K or R input is going to "L".

1. State of D0 ~ D9 output and REMOUT output is return to state of before stop mode is

achieved.

2. After 2

{System clock time} for stable oscillating, first instruction start to operate.

3. In return to normal operation, WDT is counted from zero again.

But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction

is same to NOP instruction.

Chapter 4. FUNCTIONAL DESCRIPTION

5-1

CHAPTER 5. INSTRUCTION

INSTRUCTION FORMAT

All of the 43 instruction in GMS36/37XXX(T) series is format in two fields of OP
code and operand which consist of eight bits. The following formats are available
with different types of operands.

*Format

All eight bits are for OP code without operand.

*Format

Two bits are for operand and six bits for OP code.
Two bits of operand are used for specifying bits of RAM and X-register (bit 1 and
bit 7 are fixed at

)

*Format

Four bits are for operand and the others are OP code.
Four bits of operand are used for specifying a constant loaded in RAM or Y-
register, a comparison value of compare command, or page addressing in ROM.

*Format

Six bits are for operand and the others are OP code.
Six bits of operand are used for word addressing in the ROM.

Chapter 5. INSTRUCTION

5-2

INSTRUCTION TABLE

The GMS36/37XXX(T) series provides the following 43 basic instructions.

Category

LAY

LYA

LAZ

Mnemonic

Function

RAM to

LMA

LMAIY

LYM

M(X,Y)

A, Y

Y+1

M(X,Y)

LAM

XMA

M(X,Y)

Immediate

LYI i

LMIIY i

LXI n

M(X,Y)

i, Y

Y+1

RAM Bit

Manipulation

SEM n

REM n

TM n

M(n)

TEST M(n) = 1

ROM

Address

BR a

CAL a

RTN

if ST = 1 then Branch

if ST = 1 then Subroutine call

Return from Subroutine

LPBI i

Arithmetic

A + M(X,Y)

M(X,Y) - A

M(X,Y) + 1

M(X,Y) - 1

A + 1

Y + 1

A - 1

Chapter 5. INSTRUCTION

5-3

Category

Arithmetic

EORM

NEGA

Mnemonic

Y - 1

Function

A + M (X,Y)

A + 1

Comparison

ALEM

ALEI i

TEST A

M(X,Y)

TEST A

MNEZ

YNEA

TEST M(X,Y)

TEST Y

YNEI i

KNEZ

TEST Y

TEST K

RNEZ

TEST R

Input /

Output

LAK

LAR

Output

0 at GMS36XXX, 1 at GMS37XXX

Output

1 at GMS36XXX, 0 at GMS37XXX

Control

WDTR

STOP

Watch Dog Timer Reset

Stop operation

LPY

NOP

PMR

No operation

Note) i = 0~f, n = 0~3, a = 6bit PC Address

*1 Column ST indicates conditions for changing status. Symbols have the following
meanings

S : On executing an instruction, status is unconditionally set.
C : Status is only set when carry or borrow has occurred in operation.
B : Status is only set when borrow has not occurred in operation.
E : Status is only set when equality is found in comparison.
N : Status is only set when equality is not found in comparison.
Z : Status is only set when the result is zero.

Chapter 5. INSTRUCTION

5-4

DETAILS OF INSTRUCTION SYSTEM

All 43 basic instructions of the GMS36/37XXX(T) Series are one by one described

in detail below.

Description Form

Each instruction is headlined with its mnemonic symbol according to the
instructions table given earlier.
Then, for quick reference, it is described with basic items as shown below. After
that, detailed comment follows.

· Items :

- Naming :

Full spelling of mnemonic symbol

- Status :

Check of status function

- Format :

Categorized into

- Operand :

Omitted for Format

- Function

Chapter 5. INSTRUCTION

5-5

(1) LAY

Naming :

Load Accumulator from Y-Register

Status :

Set

Format :

Function :

Data of four bits in the Y-register is unconditionally transferred
to the accumulator. Data in the Y-register is left unchanged.

(2) LYA

Naming :

Load Y-register from Accumulator

Status :

Set

Format :

Function :

Load Y-register from Accumulator

(3) LAZ

Naming :

Clear Accumulator

Status :

Set

Format :

Function :

Data in the accumulator is unconditionally reset to zero.

(4) LMA

Naming :

Load Memory from Accumulator

Status :

Set

Format :

Function :

M(X,Y)

Data of four bits from the accumulator is stored in the RAM
location addressed by the X-register and Y-register. Such data
is left unchanged.

(5) LMAIY

Naming :

Load Memory from Accumulator and Increment Y-Register

Status :

Set

Format :

Function :

M(X,Y)

A, Y

Y+1

Data of four bits from the accumulator is stored in the RAM
location addressed by the X-register and Y-register. Such data
is left unchanged.

Chapter 5. INSTRUCTION

5-6

(6) LYM

Naming :

Load Y-Register form Memory

Status :

Set

Format :

Function :

M(X,Y)

Data from the RAM location addressed by the X-register and
Y-register is loaded into the Y-register. Data in the memory is
left unchanged.

(7) LAM

Naming :

Load Accumulator from Memory

Status :

Set

Format :

Function :

M(X,Y)

Data from the RAM location addressed by the X-register and
Y-register is loaded into the Y-register. Data in the memory is
left unchanged.

(8) XMA

Naming :

Exchanged Memory and Accumulator

Status :

Set

Format :

Function :

M(X,Y)

Data from the memory addressed by X-register and Y-register
is exchanged with data from the accumulator. For example,
this instruction is useful to fetch a memory word into the
accumulator for operation and store current data from the
accumulator into the RAM. The accumulator can be restored
by another XMA instruction.

(9) LYI i

Naming :

Load Y-Register from Immediate

Status :

Set

Format :

Operand :

Constant 0

Function :

To load a constant in Y-register. It is typically used to specify
Y-register in a particular RAM word address, to specify the
address of a selected output line, to set Y-register for
specifying a carrier signal outputted from OUT port, and to
initialize Y-register for loop control. The accumulator can be
restored by another XMA instruction.

Data of four bits from operand of instruction is transferred to
the Y-register.

Chapter 5. INSTRUCTION

5-7

(10) LMIIY i

Naming :

Load Memory from Immediate and Increment Y-Register

Status :

Set

Format :

Operand :

Constant 0

Function :

M(X,Y)

i, Y

Y + 1

Data of four bits from operand of instruction is stored into the
RAM location addressed by the X-register and Y-register.
Then data in the Y-register is incremented by one.

(11) LXI n

Naming :

Load X-Register from Immediate

Status :

Set

Format :

Operand :

X file address 0

Function :

A constant is loaded in X-register. It is used to set X-register in
an index of desired RAM page. Operand of 1 bit of command
is loaded in X-register.

(12) SEM n

Naming :

Set Memory Bit

Status :

Set

Format :

Operand :

Bit address 0

Function :

M(X,Y,n)

Depending on the selection in operand of operand, one of four
bits is set as logic 1 in the RAM memory addressed in
accordance with the data of the X-register and Y-register.

(13) REM n

Naming :

Reset Memory Bit

Status :

Set

Format :

Operand :

Bit address 0

Function :

M(X,Y,n)

Depending on the selection in operand of operand, one of four
bits is set as logic 0 in the RAM memory addressed in
accordance with the data of the X-register and Y-register.

Chapter 5. INSTRUCTION

5-8

(14) TM n

Naming :

Test Memory Bit

Status :

Comparison results to status

Format :

Operand :

Bit address 0

Function :

M(X,Y,n)

1 when M(X,Y,n)=1, ST

0 when M(X,Y,n)=0

A test is made to find if the selected memory bit is logic. 1
Status is set depending on the result.

(15) BR a

Naming :

Branch on status 1

Status :

Conditional depending on the status

Format :

Operand :

Branch address a (Addr)

Function :

When ST =1 , PA

PB, PC

a(Addr)

When ST = 0, PC

PC + 1, ST

Note : PC indicates the next address in a fixed sequence that
is actually pseudo-random count.

For some programs, normal sequential program execution can
be change.
A branch is conditionally implemented depending on the status
of results obtained by executing the previous instruction.

· Branch instruction is always conditional depending on the
status.
a. If the status is reset (logic 0), a branch instruction is not
rightly executed but the next instruction of the sequence is
executed.
b. If the status is set (logic 1), a branch instruction is executed
as follows.
· Branch is available in two types - short and long. The former
is for addressing in the current page and the latter for
addressing in the other page. Which type of branch to exeute
is decided according to the PB register. To execute a long
branch, data of the PB register should in advance be modified
to a desired page address through the LPBI instruction.

Chapter 5. INSTRUCTION

5-9

(16) CAL a

Naming :

Subroutine Call on status 1

Status :

Conditional depending on the status

Format :

Operand :

Subroutine code address a(Addr)

Function :

When ST =1 , PC

a(Addr)

SR1

PC + 1,

PSR1

SR2

SR1

PSR2

PSR1

SR3

SR2

PSR3

PSR2

When ST = 0 PC

PC + 1

PS ST

Note : PC actually has pseudo-random count against the next
instruction.

· In a program, control is allowed to be transferred to a mutual

subroutine. Since a call instruction preserves the return
address, it is possible to call the subroutine from different
locations in a program, and the subroutine can return control
accurately to the address that is preserved by the use of the
call return instruction (RTN).
Such calling is always conditional depending on the status.

a. If the status is reset, call is not executed.
b. If the status is set, call is rightly executed.

The subroutine stack (SR) of three levels enables a subroutine
to be manipulated on three levels. Besides, a long call (to call
another page) can be executed on any level.

· For a long call, an LPBI instruction should be executed before

the CAL. When LPBI is omitted (and when PA=PB), a short
call (calling in the same page) is executed.

Chapter 5. INSTRUCTION

5-10

(17) RTN

Naming :

Return from Subroutine

Status :

Set

Format :

Function :

SR1

PA, PB

PSR1

SR1

SR2

PSR1

PSR2

SR2

SR3

PSR2

PSR3

SR3

PSR3

PSR2

Control is returned from the called subroutine to the calling
program.

Control is returned to its home routine by transferring to the PC
the data of the return address that has been saved in the stack
register (SR1).
At the same time, data of the page stack register (PSR1) is
transferred to the PA and PB.

(18) LPBI i

Naming :

Load Page Buffer Register from Immediate

Status :

Set

Format :

Operand :

ROM page address 0

Function :

A new ROM page address is loaded into the page buffer
register (PB).
This loading is necessary for a long branch or call instruction.

The PB register is loaded together with three bits from 4 bit
operand.

(19) AM

Naming :

Add Accumulator to Memory and Status 1 on Carry

Status :

Carry to status

Format :

Function :

M(X,Y)+A, ST

1(when total>15),

0 (when total

15)

Data in the memory location addressed by the X and Y-register
is added to data of the accumulator. Results are stored in the
accumulator. Carry data as results is transferred to status.
When the total is more than 15, a carry is caused to put

in the status. Data in the memory is not changed.

Chapter 5. INSTRUCTION

5-11

(20) SM

Naming :

Subtract Accumulator to Memory and Status 1 Not Borrow

Status :

Carry to status

Format :

Function :

M(X,Y) - A

1(when A

M(X,Y))

0(when A > M(X,Y))

Data of the accumulator is, through a 2`s complemental

addition, subtracted from the memory word addressed by the
Y-register. Results are stored in the accumulator. If data of
the accumulator is less than or equal to the memory word, the
status is set to indicate that a borrow is not caused.

If more than the memory word, a borrow occurs to reset the
status to

(21) IM

Naming :

Increment Memory and Status 1 on Carry

Status :

Carry to status

Format :

Function :

M(X,Y) + 1

1(when M(X,Y)

15)

0(when M(X,Y) < 15)

Data of the memory addressed by the X and Y-register is
fetched. Adding 1 to this word, results are stored in the

accumulator. Carry data as results is transferred to the status.
When the total is more than 15, the status is set. The memory
is left unchanged.

(22) DM

Naming :

Decrement Memory and Status 1 on Not Borrow

Status :

Carry to status

Format :

Function :

M(X,Y) - 1

1(when M(X,Y)

0 (when M(X,Y) = 0)

Data of the memory addressed by the X and Y-register is
fetched, and one is subtracted from this word (addition of Fh)>
Results are stored in the accumulator. Carry data as results is
transferred to the status. If the data is more than or equal to
one, the status is set to indicate that no borrow is caused. The
memory is left unchanged.

Chapter 5. INSTRUCTION

5-12

(23) IA

Naming :

Increment Accumulator

Status :

Set

Format :

Function :

A+1

Data of the accumulator is incremented by one. Results are
returned to the accumulator.
A carry is not allowed to have effect upon the status.

(24) IY

Naming :

Increment Y-Register and Status 1 on Carry

Status :

Carry to status

Format :

Function :

Y + 1

1 (when Y = 15)

0 (when Y < 15)

Data of the Y-register is incremented by one and results are
returned to the Y-register.
Carry data as results is transferred to the status. When the
total is more than 15, the status is set.

(25) DA

Naming :

Decrement Accumulator and Status 1 on Borrow

Status :

Carry to status

Format :

Function :

A - 1

1(when A

0 (when A = 0)

Data of the accumulator is decremented by one. As a result
(by addition of Fh), if a borrow is caused, the status is reset to

by logic. If the data is more than one, no borrow occurs

and thus the status is set to

Chapter 5. INSTRUCTION

5-13

(26) DY

Naming :

Decrement Y-Register and Status 1 on Not Borrow

Status :

Carry to status

Format :

Function :

Y -1

1 (when Y

0 (when Y = 0)

Data of the Y-register is decremented by one.

Data of the Y-register is decremented by one by addition of
minus 1 (Fh).
Carry data as results is transferred to the status. When the
results is equal to 15, the status is set to indicate that no
borrow has not occurred.

(27) EORM

Naming :

Exclusive or Memory and Accumulator

Status :

Set

Format :

Function :

M(X,Y) + A

Data of the accumulator is, through a Exclusive OR,
subtracted from the memory word addressed by X and Y-
register. Results are stored into the accumulator.

(28) NEGA

Naming :

Negate Accumulator and Status 1 on Zero

Status :

Carry to status

Format :

Function :

A + 1

1(when A = 0)

0 (when A != 0)

The 2`s complement of a word in the accumulator is obtained.

The 2`s complement in the accumulator is calculated by adding
one to the 1`s complement in the accumulator. Results are
stored into the accumulator. Carry data is transferred to the
status. When data of the accumulator is zero, a carry is
caused to set the status to

Chapter 5. INSTRUCTION

5-14

(29) ALEM

Naming :

Accumulator Less Equal Memory

Status :

Carry to status

Format :

Function :

M(X,Y)

1 (when A

M(X,Y))

0 (when A > M(X,Y))

Data of the accumulator is, through a complemental addition,
subtracted from data in the memory location addressed by the
X and Y-register. Carry data obtained is transferred to the
status. When the status is

, it indicates that the data of

the accumulator is less than or equal to the data of the
memory word. Neither of those data is not changed.

(30) ALEI

Naming :

Accumulator Less Equal Immediate

Status :

Carry to status

Format :

Function :

1 (when A

0 (when A > i)

Data of the accumulator and the constant are arithmetically
compared.

Data of the accumulator is, through a complemental addition,
subtracted from the constant that exists in 4bit operand. Carry
data obtained is transferred to the status. The status is set
when the accumulator value is less than or equal to the

constant. Data of the accumulator is left unchanged.

(31) MNEZ

Naming :

Memory Not Equal Zero

Status :

Comparison results to status

Format :

Function :

M(X,Y)

1(when M(X,Y)

0 (when M(X,Y) = 0)

A memory word is compared with zero.

Data in the memory addressed by the X and Y-register is
logically compared with zero. Comparison data is thransferred
to the status. Unless it is zero, the status is set.

Chapter 5. INSTRUCTION

5-15

(32) YNEA

Naming :

Y-Register Not Equal Accumulator

Status :

Comparison results to status

Format :

Function :

1 (when Y

0 (when Y = A)

Data of Y-register and accumulator are compared to check if
they are not equal.

Data of the Y-register and accumulator are logically compared.
Results are transferred to the status. Unless they are equal,
the status is set.

(33) YNEI

Naming :

Y-Register Not Equal Immediate

Status :

Comparison results to status

Format :

Operand :

Constant 0

Function :

1 (when Y

0 (when Y = i)

The constant of the Y-register is logically compared with 4bit
operand. Results are transferred to the status. Unless the
operand is equal to the constant, the status is set.

(34) KNEZ

Naming :

K Not Equal Zero

Status :

The status is set only when not equal

Format :

Function :

When K

0, ST

A test is made to check if K is not zero.

Data on K are compared with zero. Results are transferred to
the status. For input data not equal to zero, the status is set.

(35) RNEZ

Naming :

R Not Equal Zero

Status :

The status is set only when not equal

Format :

Function :

When R

0, ST

A test is made to check if R is not zero.

Data on R are compared with zero. Results are transferred to
the status. For input data not equal to zero, the status is set.

Chapter 5. INSTRUCTION

5-16

(36) LAK

Naming :

Load Accumulator from K

Status :

Set

Format :

Function :

Data on K are transferred to the accumulator

(37) LAR

Naming :

Load Accumulator from R

Status :

Set

Format :

Function :

Data on R are transferred to the accumulator

(38) SO

Naming :

Set Output Register Latch

Status :

Set

Format :

Function :

D(Y)

REMOUT

0(PMR=5)

Y = 8 at GMS36XXX(T)

REMOUT

1(PMR=5)

Y = 8 at GMS37XXX(T)

D0~D9

1 (High-Z)

Y = 9

R(Y)

Y = Eh

D0~D9, R

Y = Fh

A single D output line is set to logic 1, if data of Y-register is
between 0 to 7.
Carrier frequency come out from REMOUT port, if data of
Y-register is 8.
All D output line is set to logic 1, if data of Y-register is 9.
It is no operation, if data of Y-register between 10 to 15.
When Y is between Ah and Dh, one of R output lines is set at
logic 1.
When Y is Eh, the output of R is set at logic 1.
When Y is Fh, the output D0~D9 and R are set at logic 1.

Data of Y-register is between 0 to 7, selects appropriate D
output.
Data of Y-register is 8, selects REMOUT port.
Data of Y-register is 9, selects all D port.
Data in Y-register, when between Ah and Dh, selects an
appropriate R output (R0~R3).
Data in Y-register, when it is Eh, selects all of R0~R3.
Data in Y-register, when it is Fh, selects all of D0~D9 and
R0~R3.

Chapter 5. INSTRUCTION

5-17

(39) RO

Naming :

Reset Output Register Latch

Status :

Set

Format :

Function :

D(Y)

REMOUT

Y = 8 at GMS36XXX(T)

REMOUT

Y = 8 at GMS37XXX(T)

D0~D9

Y = 9

R(Y)

Y = Eh

D0~D9, R

Y = Fh

A single D output line is set to logic 0, if data of Y-register is
between 0 to 9.
REMOUT port is set to logic 0, if data of Y-register is 9.
All D output line is set to logic 0, if data of Y-register is 9.
When Y is between Ah and Dh, one of R output lines is set at
logic 0.
When Y is Eh, the output of R is set at logic 0
When Y is Fh, the output D0~D9 and R are set at logic 1.

Data of Y-register is between 0 to 7, selects appropriate D
output.
Data of Y-register is 8, selects REMOUT port.
Data of Y-register is 9, selects D port.
Data in Y-register, when between Ah and Dh, selects an
appropriate R output (R0~R3).
Data in Y-register, when it is Eh, selects all of R0~R3.
Data in Y-register, when it is Fh, selects all of D0~D9 and
R0~R3.

(40) WDTR

Naming :

Watch Dog Timer Reset

Status :

Set

Format :

Function :

Reset Watch Dog Timer (WDT)

Normally, you should reset this counter before overflowed
counter for dc watch dog timer. this instruction controls this
reset signal.

Chapter 5. INSTRUCTION

6-1

Guideline for S/W

1. All rams need to be initialized to zero in reset address for proper design.

2. Make the output ports `H` after reset.

3. Do not use WDTR instruction in subroutine.

4. Before reading the input port the waiting time should be more than 200uS.

5. To decrease current consumption, make the output port as high in normal routine except
for key scan strobe and STOP mode.

6. We recommend you do not use all 64 bytes in a page. You had better write ` BR $` in
unused area. This will help you prevent unusual operation of MCU.

7. Be careful not to use long call or branch (CALL,BL) with arithmetic manipulation.
If you want to use branch right after arithmetic manipulation, the long call or branch will be
against your intention.

ex) LAR ; The value of R ports -> Accumulator
ALEI 14 ; A

14 : S = 1, A

14 : S = 0

BL TRUE ; S is always 1 because BL is composed of LPBI and BR.
-------------- Fail

LAR ; The value of R ports -> Accumulator
ALEI 14 ; A

14 : S = 1, A

14 : S = 0

BR TRUE ; When S is 1 Branch will occur. Otherwise Branch will not occur and
LAK

; next instruction will be operated.

-------------- Right

Chapter 6. Application

6-4

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Chapter 6. Application

6-5

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1st flame

C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D5 D7

Lead code

Custom code

Data code

9ms

4.5ms

- Bit Description

- Flame Interval : Tf

The transmitted waveform as long as a key is depressed

0.56ms

1.125ms

0.56ms

2.25ms

Bit

Tf=108mS

- Repeat code

9ms

2.25ms

0.56ms

Chapter 6. Application

6-6

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Chapter 6. Application

6-7

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Chapter 6. Application

6-8

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Chapter 6. Application

6-9

£ ¢ t t t t t t

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Chapter 6. Application

6-10

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t t t t t t t t t t t t t t t t t t
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Chapter 6. Application

6-11

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6-12

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Chapter 6. Application

7-1

CHAPTER 7. GMS36XXXT

Description

The GMS36XXXT series are remote control transmitter which uses CMOS technology

and the EPROM version.

This enables transmission code outputs of different configurations, multiple custom code

output and double push key output for easy fabrication.

The GMS36XXXT series are suitable for remote control of TV, VCR, FANS, Air-conditioners,

Audio Equipment, Toys, Games etc.

Features

Program memory

: 1,024 bytes for GMS36/004T/112T/140T

Data memory : 32

4 bits

43 types of instruction set

3 levels of subroutine nesting

Operating frequency : 300kHz ~ 1MHz at kHz version

2.4MHz ~ 4MHz at MHz version

Instruction cycle :

OSC

/6 at kHz version

OSC

/48 at MHz version

CMOS process (Single 3.0V power supply)

Stop mode (Through internal instruction)

Released stop mode by key input

Built in Power-on Reset circuit

Built in Low Voltage Detection circuit

Built in capacitor for ceramic oscillation circuit at kHz version

Built in a watch dog timer (WDT)

Built in transistor for I.R LED Drive : I

=190mA at V

=3V and V

=0.3V

Low operating voltage : 2.2 ~ 3.6V (at 300kHz ~ 4MHz)

Chapter 7.GMS36XXXT

Table 7-1 GMS36XXXT series members

Series

GMS36004T

GMS36112T

GMS36140T

Program memory

1,024

Data memory

I/O ports

Input ports

Output ports

6 (D0~D5)

10 (D0~D9)

Package

16DIP/SOP

20DIP/SOP/SSOP

24Skinny DIP/SOP

7-2

Pin Description

Pin

Function

I/O

Connected to 2.2~ 3.6V power supply

Connected to 0V power supply.

4-bit input port with built in pull-up resistor.

STOP mode is released by "L" input of each pin.

Especially, K3 is the input pin for VPP.

For programming K3 pin receives 12.5V(programming voltage).

K0 ~ K3

Input

GND

VDD

Each can be set and reset independently.

The output is the structure of N-channel-open-drain.

4-bit I/O port. (Input mode is set only when each of them output
"H".)

In outputting, each can be set and reset independently(or at once.)

The output is in the form of C-MOS.

STOP mode is released by "L" input of each pin.

High current output port driving I.R. LED.

The output is in the form of N-channel-open-drain.

D0 ~ D9

Output

R0 ~ R3

I/O

REMOUT

Output

Oscillator input. Input to the oscillator circuit and connection point for
ceramic resonator.

Internal capacitors available at kHz version.

A feedback resistor is internally connected between this pin and
OSC2.

Connect a resonator between this pin and OSC1.

OSC1

Input

OSC2

Output

High current Tr. ground pin. (connected to GND)

High current output Tr. is connected between this pin and
REMOUT.

PGND

Chapter 7. GMS36XXXT

7-3

STOP Operation

Stop mode can be achieved by STOP instructions.

In stop mode :

1. Oscillator is stopped, the operating current is low.

2. Watch dog timer is reset, D0~D3 output is "L"and REMOUT output is "H" (Output

Tr. is off.)

3. Part other than WDT, D0~D3 output and REMOUT output have a value before

come into stop mode.

Stop mode is released when one of K or R input is going to "L".

1. State of D0~D3 output and REMOUT output is return to state of before stop mode

is achieved.

2. After 2

System clock time for stable oscillating, first instruction start to operate.

3. In return to normal operation, WDT is counted from zero again.

But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction

is same to NOP instruction.

Chapter 7. GMS36XXXT

7-4

Parameter

Supply Voltage

Programming Voltage

Power dissipation

Storage temperature range

Input voltage

Output voltage

Unit

Electrical Characteristics

Absolute maximum ratings (Ta = 25

)

Symbol

Tstg

OUT

Max. rating

-0.3 ~ 5.0

-0.3 ~ 13.5

700 *

-55 ~ 125

-0.3 ~ V

+0.3

-0.3 ~ V

+0.3

* Thermal derating above 25

: 6mW per degree

rise in temperature.

Recommended operating condition

Parameter

Supply Voltage

Unit

Rating

2.2 ~ 3.6

Condition

300kHz ~ 4MHz

Symbol

Topr

Operating temperature

-20 ~ +70

Chapter 7. GMS36XXXT

7-5

Electrical characteristics (Ta=25

, V

= 3V)

*1 Refer to

Fig.7-1 I

OL2

vs. V

OL2

Graph

*2 Refer to

Fig.7-2 I

OL1

vs. V

OL1

Graph

*3 I

DD1

, I

DD2

, is measured at RESET mode.

Parameter

Symbol

Limits

Unit Condition

Min.

Typ.

Max.

Input H current

R Pull-up Resistance

IH1

PU1

2.1

140

300

VI=GND

VI=V

K Pull-up Resistance

PU2

140

300

VI=GND, Output off

Current on STOP mode

Operating supply current 1

Operating supply current 2

DD2

DD1

STP

1.0

0.8

3.0

1.5

OSC

=4MHz

OSC

=455KHz

At STOP mode

REMOUT leakage current

OLK1

OUT

, Output off

OSC2 output L voltage

OSC2 output H voltage

OH3

OL3

2.1

2.5

0.4

0.9

OH3

= -40uA (455kHz)

= -150uA (4MHz)

OL3

=40uA (455kHz)

= 150uA (4MHz)

D. R output L voltage

OL2

0.15

0.4

OL2

=3mA

K, R input H voltage

K, R input L voltage

IL1

0.9

OSC

/48

OSC

System
clock
frequency

OSC

2.4

300

1000

MHz

kHz

kHz version

MHz version

REMOUT output L current

OL1

150

190

230

OL1

=0.3V

D, R output leakage current

OLK2

OUT

, Output off

Feedback Resistance

0.3

1.0

3.0

OSC1

=GND, V

OSC2

=VDD

OL1

=0.4V

200

250

300

Chapter 7. GMS36XXXT

8-1

CHAPTER 8. GMS37XXXT

Description

The GMS37XXXT series are remote control transmitter which uses CMOS

technology and the EPROM version.

This enables transmission code outputs of different configurations, multiple

custom code output, and double push key output for easy fabrication.

The GMS37XXXT series are suitable for remote control of TV, VCR, FANS, Air-

conditioners, Audio Equipment, Toys, Games etc.

It is possible to structure the 8 x 7 key matrix for GMS37112T, and the 4 x 7 key

matrix for GMS37004T.

Features

Program memory

: 1,024 bytes for GMS37004T/112T/140T

Data memory : 32

4 bits

43 types of instruction set

3 levels of subroutine nesting

Operating frequency :

300kHz ~ 1MHz at kHz version

2.4MHz ~ 4MHz at MHz version

Instruction cycle :

OSC

/6 at kHz version

OSC

/48 at MHz version

CMOS process (Single 3.0V power supply)

Stop mode (Through internal instruction)

Released stop mode by key input

Built in Power-on Reset circuit

Built in Low Voltage Detection circuit

Built in capacitor for ceramic oscillation circuit at kHz version

Built in a watch dog timer (WDT)

Low operating voltage

: 2.2 ~ 3.6V (at 300kHz ~ 4MHz)

Chapter 8. GMS37XXXT

Table 8-1 GMS37XXXT series members

Series

GMS37004T

GMS37112T

GMS37140T

Program memory

1,024

Data memory

I/O ports

Input ports

Output ports

7 (D0~D6)

10 (D0~D9)

Package

16DIP/SOP

20DIP/SOP/SSOP

24Skinny DIP/SOP

8-2

Pin Description

Pin

Function

I/O

Connected to 2.2~ 3.6V power supply

Connected to 0V power supply.

4-bit input port with built in pull-up resistor.

STOP mode is released by "L" input of each pin.

Especially, K3 is the input pin for VPP.

For programming K3 pin receives 12.5V(programming voltage).

K0 ~ K3

Input

GND

VDD

Each can be set and reset independently.

The output is the structure of N-channel-open-drain.

4-bit I/O port. (Input mode is set only when each of them output
"H".)

In outputting, each can be set and reset independently(or at once.)

The output is in the form of C-MOS.

STOP mode is released by "L" input of each pin.

High current output port

The output is in the form of C-MOS.

The state of large current on is " H "

D0 ~ D9

Output

R0 ~ R3

I/O

REMOUT

Output

Oscillator input. Input to the oscillator circuit and connection point for
ceramic resonator.

Internal capacitors available at kHz version.

A feedback resistor is internally connected between this pin and
OSC2.

Connect a resonator between this pin and OSC1.

OSC1

Input

OSC2

Output

Chapter 8. GMS37XXXT

8-3

STOP Operation

Stop mode can be achieved by STOP instructions.

In stop mode :

1. Oscillator is stopped, the operating current is low.

2. Watch dog timer is reset, D0~D3 output is "L"and REMOUT output is "L"

3. Part other than WDT, D0~D3 output and REMOUT output have a value before

come into stop mode.

Stop mode is released when one of K or R input is going to "L".

1. State of D0~D3 output and REMOUT output is return to state of before stop mode

is achieved.

2. After 2

System clock time for stable oscillating, first instruction start to operate.

3. In return to normal operation, WDT is counted from zero again.

But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction

is same to NOP instruction.

Chapter 8. GMS37XXXT

8-4

Parameter

Supply Voltage

Programming Voltage

Power dissipation

Storage temperature range

Input voltage

Output voltage

Unit

Electrical Characteristics

Absolute maximum ratings (Ta = 25

)

Symbol

Tstg

OUT

Max. rating

-0.3 ~ 5.0

-0.3 ~ 13.5

700 *

-55 ~ 125

-0.3 ~ V

+0.3

-0.3 ~ V

+0.3

* Thermal derating above 25

: 6mW per degree

rise in temperature.

Recommended operating condition

Parameter

Supply Voltage

Unit

Rating

2.2 ~ 3.6

Condition

300kHz ~ 4MHz

Symbol

Topr

Operating temperature

-20 ~ +70

Chapter 8. GMS37XXXT

8-5

Electrical characteristics (Ta=25

, V

= 3V)

Parameter

Symbol

Limits

Unit Condition

Min.

Typ.

Max.

Input H current

R Pull-up Resistance

IH1

PU1

2.1

140

300

VI=GND

VI=V

K Pull-up Resistance

PU2

140

300

VI=GND, Output off

REMOUT output H current

OH1

-5

-15

-30

OH1

=2V

OSC2 output L voltage

OSC2 output H voltage

OH3

OL3

2.1

2.5

0.4

0.9

OH3

= -40uA (455kHz)

= -150uA (4Mhz)

OL3

=40uA (455kHz)

=150uA (4MHz)

D. R output L voltage

OL2

0.15

0.4

OL2

=3mA

K, R input H voltage

K, R input L voltage

IL1

0.9

REMOUT output L current

OL1

2.2

OL1

=0.4V

D, R output leakage
current

OLK2

OUT

, Output off

Feedback Resistance

0.3

1.0

3.0

OSC1

=GND, V

OSC2

=VDD

Current on STOP mode

Operating supply current 1

Operating supply current 2

DD2

DD1

STP

1.0

0.8

3.0

1.5

OSC

=4MHz

OSC

=455KHz

At STOP mode

OSC

/48

OSC

System
clock
frequency

OSC

2.4

300

1000

MHz

kHz

kHz version

MHz version

*1 Refer to Fig.8-1 < I

OL2

vs. V

OL2

Graph>

*2 Refer to Fig.8-2 < I

OL1

vs. V

OL1

Graph>

*3 Refer to Fig.8-3 < I

OH1

vs. V

OH1

Graph>

*4 I

DD1

, I

DD2

, is measured at RESET mode.

Chapter 8. GMS37XXXT

9-1

CHAPTER 9. EPROM

MODE Define

Device operation

Exact User pgm

Item

User mode

1Byte PGM Write & Verify

Lock bit Write mode

Lock bit Read mode

Address in, Data in

Data out

Lock bit write

Lock bit out (to D5 port)

Mode setting

K3~ K0 = 0 ~ 3V

Vcc=3V

Vcc=5.5V

K1~0=01/00

K1~0=01/01

Address in, Data out

EPROM read mode

Vcc=5.5V

K1~0=01/10

K3 =12.5V

Vcc=5.5V,

(Default : unlock)

K1~0=01/10

K2 = 0V

Reset mode

System reset before

all test

K2 = Vcc

* Mode setting (K1~0=01/10) means the serial input by 2bits.

Chapter 9. EPROM

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Chapter 9. EPROM

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Chapter 9. EPROM

9-4

Program / Verify Timing Diagrams In kHz Version.

1) EPROM Write & Verify Mode (1Byte)

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3. The Data will be inputted from the 19th rising edge of OSC1.

4. If not written during 10 times repeats (120us), repeat the 5 times until all is written.

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Chapter 9. EPROM

9-5

2) EPROM Read Mode (1Byte)

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3. The Data will be inputted from the 19th rising edge of OSC1.

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Chapter 9. EPROM

9-6

3) Lock Bit Write Mode

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3. If not written during 10 times repeats (120us), repeat the 5 times until all is written.

Chapter 9. EPROM

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3. Lock data is outputted from D5 port.

If you set Lock bit, the output data of D5 is always `H`.

Chapter 9. EPROM

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1) EPROM Write & Verify Mode (1Byte)

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3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck.

4. If not written during 10 times repeats (120us), repeat the 5 times until all is written.

5. For device verify. If you set Lock bit, output data is always `0F`h.

Chapter 9. EPROM

9-10

2) EPROM Read Mode

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Chapter 9. EPROM

9-12

3) Lock Bit Write Mode

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Chapter 9. EPROM

9-13

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#. Note :

1. Internal system is reset at VPP = 12.5V and K2=`Low`

2. OSC1 is made of a block of 8 x Tp clock.

3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck.

4. Lock data is outputted from D5 port.

If you set Lock bit, the output data of D5 is always `H`.

Chapter 9. EPROM

9-14

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Timing Flowchart for Eprom Program / Verify.

Chapter 9. EPROM

Writing should be done at the defined voltage and timing. In case of EPROM mode, programming
voltage is 12.5V. More than defined voltage can give device so great damage to destroy it.
Before writing you had better ascertain the characteristics of socket and socket adapter of EPROM
writer. It can happen to write error when you touch socket adapter or device. We recommend below
flow to improve reliability after writing.

MASK ORDER & VERIFICATION SHEET
GMS3 -R

2. Device Information

Package

4. Marking Specification

6. ROM CODE Verification

20 SSOP

16 SOP (150mil)

16 SOP (300mil)

16 DIP

20 SOP

20 DIP

24 SOP

3. Mask Option

Inclusion of

Pull-up

Port

Y/N

R0* R1* R2* R3*

Inclusion of

condensor

for Osc.

Y/N

System

Clock

Selection

focs / 6

fosc / 48

Release of

Stop mode

Port

Y/N

K0 K1 K2 K3 R0* R1* R2* R3*

Status of

D port while

Stop mode

Port

a/b

D0 D1 D2 D3 D4 D5 D6 D7**

5. Delivery Schedule

Mask Sample

Risk Order

Date

. .

Quantity

pcs

Confirmation

. .

HYNIX Semiconductor Inc. write in below

Customer write in below

Name &
Signature

Verification Date :

Please confirm our verification data.

Check Sum :

TEL :

82-431-270-4078

FAX :

82-431-270-4075

Approval Date : . .

I agree with your verification data and confirm
you to make mask set.

TEL : FAX :

Company Name :
Section Name :
Signature :

@27c256

4. If you use fosc/6, we recommend inclusion of condensor and
fosc/48, no inclusion of condensor

* : Marked port is not available for GMS36/37004
** : Marked port is not available for GMS36/37004/112
5. D6 port is available for GMS37004/112 but
not available for GMS36004/112

1. Don't use WDTR instruction in subroutine.
2. Use Br $ at start (except 0 page ) , end and
unused address in every page.
3. a: State of " L" forcibly, b: Remain the state just before
stop instruction. You must select "a" option when you use
Dport as key application.

Standard Marking

User Marking

R YWW

File Name

Check Sum

Mask Data

E-Mail

( )

. DMP

@27C256

. RHX

User LOGO

HYNIX Semiconductor Inc.

MCU APPLICATION TEAM

1. Customer Information

Company Name

Name & Signature

Tel:

Fax:

Order Date

D8**D9**

24 DIP

HYNIX

YWW

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS36ser

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS36ser