Version 2.0

Published by
MCU Application Team

Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Repre-
sentatives listed at address directory.

Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no
way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

Revision History

Ver 2.0 (this manual) May, 01, 2001

The manuals of GMS81508B/16B/24B and GMS82512/16/24 are integrated.
Choice-Gang4 writer(for PC) is replaced with Choice-Gang4(for stand alone).

Ver 1.05 (before manual) Sep., 20, 2000

Choice-Dr writer is omitted on the page 76 because it is not available any longer.
For the Hynix MCU on the ALL-07, writer program is only available from Hynix sales part. Please ask to Hynix
sales. Hi-Lo systems does not support the software of ALL-07 in their web site currently.

Ver 1.04 (before version) Dec., 1999

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Table of Contents

1. OVERVIEW ...........................................1

Description .........................................................1

Features .............................................................1

Development Tools ............................................2

Ordering Information

2. BLOCK DIAGRAM ................................3
3. PIN ASSIGNMENT ...............................5
4. PACKAGE DIAGRAM ...........................8
5. PIN FUNCTION ...................................11
6. PORT STRUCTURES .........................13
7. ELECTRICAL CHARACTERISTICS ...15

Absolute Maximum Ratings .............................15

Recommended Operating Conditions ..............15

A/D Converter Characteristics .........................15

DC Electrical Characteristics ...........................16

AC Characteristics ...........................................17

Serial Interface Timing Characteristics ............18

Typical Characteristic Curves ..........................19

8. MEMORY ORGANIZATION ................21

Registers ..........................................................21

Program Memory .............................................24

Data Memory ...................................................27

Addressing Mode .............................................30

9. I/O PORTS ..........................................34
10. BASIC INTERVAL TIMER .................37
11. TIMER/EVENT COUNTER ...............39

8-bit Timer / Counter Mode ..............................41

16-bit Timer / Counter Mode ............................45

8-bit Capture Mode ..........................................46

16-bit Capture Mode ........................................47

12. ANALOG DIGITAL CONVERTER .....49
13. SERIAL COMMUNICATION .............51

Transmission/Receiving Timing .......................53

The Serial I/O operation by SRDY pin ............ 53

The method of Serial I/O ................................. 54

The Method to Test Correct Transmission ...... 54

14. PWM OUTPUT .................................55
15. BUZZER FUNCTION ........................58
16. INTERRUPTS ...................................60

Interrupt Sequence .......................................... 62

BRK Interrupt .................................................. 63

Multi Interrupt .................................................. 64

External Interrupt ............................................. 64

17. WATCHDOG TIMER ........................67
18. POWER DOWN OPERATION ..........69

STOP Mode .................................................... 69

Minimizing Current Consumption .................... 70

19. OSCILLATOR CIRCUIT ....................72
20. RESET ..............................................73

External Reset Input ........................................ 73

Watchdog Timer Reset ................................... 73

21. POWER FAIL PROCESSOR ............74
22. OTP PROGRAMMING ......................76

How to Program .............................................. 76

Pin Function .................................................... 76

Programming Specification ............................. 80

A. CONTROL REGISTER LIST ................. i
B. SOFTWARE EXAMPLE ...................... iii

7-segment LED display .................................... iii

C. INSTRUCTION ...................................viii

Terminology List .............................................. viii

Instruction Map ..................................................ix

Alphabetic order table of instruction ...................x

Instruction Table by Function ...........................xv

D. MASK ORDER SHEET

........................ xxi

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

GMS81508B/16B/24B

GMS82512/16/24

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

WITH A/D CONVERTER

1. OVERVIEW

1.1 Description

The GMS81508B/16B/24B are advanced CMOS 8-bit microcontrollers with 8K/16K/24K bytes of ROM and 64pin package.
And the GMS82512/16/24 are the same except for 12K/16K/24K bytes of ROM and 42pin package. The GMS825xx is a
cut-down product of GMS815xxB microcontroller, that is, the function and package are reduced. These are powerful micro-
controllers which provide a highly flexible and cost effective solution to many general application. These includes several
peripheral functions such as Timer, A/D converter, Programmable buzzer driver, Serial I/O communication(GMS815xxB
only), Pulse Width Modulation function( GMS815xxB only), etc. The RAM, ROM, and I/O are placed on the same memory
map in addition to simple instruction set. Also, they support power saving mode to reduce power consumption.
The GMS815xxB is functionally 100% compatible with earier GMS81508/16 or GMS81508A/16A, and has better charac-
teristics such as strong EMS, wide operating voltage, temperature, frequency and fast programming time for the OTP.

1.2 Features

· 8K/16K/24K Bytes On-chip Program ROM

(12K/16K/24K Bytes in GMS825xx)

· 448 Bytes of On-chip Data RAM

(Included stack memory)

· Minimum Instruction Execution Time

0.5

µ
µ
µ
µ

s at 8MHz

· One 8-bit Basic Interval Timer

· Four 8-bit Timer/Event counter

or Two 16-bit Timer/Event counter

· One 6-bit Watchdog timer

· Eight channel 8-bit A/D converter

(Four channel in GMS825xx)

· Two channel 8-bit PWM

(Not support in GMS825xx)

· One 8-bit Serial Communication Interface

(Not support in GMS825xx)

· Four External Interrupt input ports

· Buzzer Driving port

- 500Hz ~ 250kHz@8MHz

· 52 I/O Ports, 4 Input Ports

(35 I/O ports in GMS825xx)

· Twelve Interrupt sources

- Basic Interval Timer: 1
- External input: 4
- Timer/Event counter: 4
- ADC: 1
- Serial Interface: 1(Not support in GMS825xx)
- WDT: 1

· Built in Noise Immunity Circuit

Device name

ROM Size

RAM Size

I/O

OTP

Package

GMS81508B

8K bytes

448 bytes

52 I/O, 4Input

GMS81516BT

64SDIP, 64MQFP,
64LQFP

GMS81516B

16K bytes

448 bytes

52 I/O, 4Input

GMS81516BT

GMS81524B

24K bytes

448 bytes

52 I/O, 4Input

GMS81524BT

GMS82512

12K bytes

448 bytes

35 I/O

GMS82524T

42SDIP, 44MQFP

GMS82516

16K bytes

448 bytes

35 I/O

GMS82524T

GMS82524

24K bytes

448 bytes

35 I/O

GMS82524T

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

- Noise filter
- Power fail processor

· Power Down Mode

- STOP mode

· 2.2V to 5.5V Wide Operating Range

· 1~10MHz Wide Operating Frequency

· 64SDIP, 64MQFP, 64LQFP package types

(42SDIP,44MQFP in GMS825xx)

· Available 16K, 24K bytes OTP version

(Available 24K bytes in GMS825xx)

1.3 Development Tools

The GMS815xxB and GMS825xx are supported by a full-
featured macro assembler, an in-circuit emulator
CHOICE-Dr.

and OTP programmers. There are two

different type programmers such as single type, gang
type(Stand-alone gang4). For more detail, Refer to "22.
OTP PROGRAMMING" on page 76. Macro assembler
operates under the MS-Windows 95/98

Please contact sales part of Hynix Semiconductor.

1.4 Ordering Information

Device name

ROM Size

RAM size

Package

Mask version

GMS81508B K
GMS81508B Q
GMS81508B LQ
GMS81516B K
GMS81516B Q
GMS81516B LQ
GMS81524B K
GMS81524B Q
GMS81524B LQ
GMS82512 K
GMS82512 Q
GMS82516 K
GMS82516 Q
GMS82524 K
GMS82524 Q

8K bytes
8K bytes
8K bytes
16K bytes
16K bytes
16K bytes
24K bytes
24K bytes
24K bytes
12K bytes
12K bytes
16K bytes
16K bytes
24K bytes
24K bytes

448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes

64SDIP
64MQFP
64LQFP
64SDIP
64MQFP
64LQFP
64SDIP
64MQFP
64LQFP
42SDIP
44MQFP
42SDIP
44MQFP
42SDIP
44MQFP

OTP version

GMS81516BT K
GMS81516BT Q
GMS81516BT LQ
GMS81524BT K
GMS81524BT Q
GMS81524BT LQ
GMS82524 K
GMS82524 Q

16K bytes OTP
16K bytes OTP
16K bytes OTP
24K bytes OTP
24K bytes OTP
24K bytes OTP
24K bytes
24K bytes

448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes

64SDIP
64MQFP
64LQFP
64SDIP
64MQFP
64LQFP
42SDIP
44MQFP

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

2. BLOCK DIAGRAM

2.1 GMS81508B/GMS81516B/GMS81524B(64 pin package)

ALU

Interrupt Controller

Data Memory

8-bit

ADC

8-bit

Counter

Timer/

Program

Memory

Data Table

8-bit Basic

Timer

Interval

Watchdog

Timer

PSW

System controller

Timing generator

System

Clock Controller

ClockGenerator

RESET

TEST

OUT

R40 / INT0
R41 / INT1
R42 / INT2
R43 / INT3
R44 / EC0
R45 / EC2
R46 / T1O
R47 / T3O

R50 / SIN

R20~R27

Power
Supply

8-bit serial

R51 / SOUT
R52 / SCLK
R53 / SRDY
R54 / WDTO
R55 / BUZ
R56 / PWM0
R57 / PWM1

R10~R17

R00~R07

R30~R37

Interface

Buzzer

Driver

R60 / AN0
R61 / AN1
R62 / AN2
R63 / AN3
R64 / AN4
R65 / AN5
R66 / AN6
R67 / AN7

(448 bytes)

8-bit PWM

ADC Power
Supply

Stack Pointer

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

3. PIN ASSIGNMENT

3.1 GMS81508B/GMS81516B/GMS81524B(64 pin package)

TEST

R67
R66
R65
R64
R63
R62
R61
R60
R57
R56
R55
R54

AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0

PWM1
PWM0

BUZ

WDTO

R53
R52
R51
R50
R47
R46
R45
R44
R43
R42
R41
R40

RESET

XIN

XOUT

SRDY

SCLK

SOUT

SIN

T3O
T1O
EC2
EC0

INT3
INT2
INT1
INT0

R30
R31
R32
R33
R34
R35
R36
R37
R00
R01
R02
R03
R04
R05
R06
R07
R10
R11
R12
R13
R14
R15
R16
R17
R20
R21
R22
R23
R24
R25
R26
R27

R66

R36
R35
R34
R33
R32
R31
R30
V

TEST

R67

AN6

AN7

R42

R22
R23
R24
R25
R26
R27
V

XOUT
XIN
RESET
R40
R41

INT2

INT0
INT1

R37

R01

R02

R03

R04

R05

R06

R07

R10

R11

R12

R13

R14

R15

R16

R17

R00

R20

R21

R65

R63

R62

R61

R60

R57

R56

R55

R54

R53

R52

R51

R50

R47

R46

R45

R64

R44

R43

AN5

AN3

AN2

AN1

AN0

PWM1

PWM0

BUZ

WDTO

SRDY

SCLK

SOUT

SIN

T3O

T1O

EC2

AN4

EC0

INT

32
31
30
29
28
27
26
25
24
23
22
21
20

52
53
54
55
56
57
58
59
60
61
62
63
64

64MQFP

64SDIP

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

GMS81508B/16B/24B

(Top View)

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

R20
R21
R22
R23
R24
R25
R26
R27
V

XOUT
XIN
RESET
R40
R41
R42
R43

R00

R01

R02

R03

R04

R05

R06

R07

R10

R11

R12

R13

R14

R15

R16

R17

R63

R62

R61

R60

R57

R56

R55

R54

R53

R52

R51

R50

R47

R46

R45

R44

R37
R36
R35
R34
R33
R32
R31
R30
V

TEST

R67
R66
R65
R64

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

GMS81508B/16B/24B

64LQFP

AN3

AN2

AN1

AN0

PWM1

PWM0

BUZ

WDTO

SRDY

SCLK

SOUT

SIN

T3O

T1O

EC2

EC0

INT2

INT0
INT1

INT3

AN5

AN7
AN6

AN4

(Top View)

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

3.2 GMS82512/GMS82516/GMS82524(42 pin package)

R30
V

TEST

R67
R66
R65
R64
R55
R54
R44
R43
R42
R41
R40

RESET

AN7
AN6
AN5
AN4

BUZ

WDTO

EC0

INT3
INT2
INT1
INT0

XIN

XOUT

R27
R26

R31
R32
R33
R34
R35
R36
R37
R00
R01
R02
R03
R04
R05
R06
R07
R20
R21
R22
R23
R24
R25

42SDIP

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

GMS82512/16/24

(Top View)

R21
R22
R23
R24
R25
R26
R27
V

XOUT
XIN
RESET

R37

R00

R01

R02

R03

R04

R05

R06

R07

R20

R66

R65

R64

N.C.

R55

R54

R44

R43

R42

R41

R40

R36
R35
R34
R33
R32
R31
R30
V

TEST

R67

17
16
15
14
13
12

34
35
36
37
38
39
40
41
42
43
44

GMS82512/16/24

44MQFP

AN6

AN5

AN4

BUZ

WDTO

EC0

INT3

INT2

INT1

INT0

AN7

N .C .

: N o C o n n e ctio n

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

5. PIN FUNCTION

: Supply voltage.

: Circuit ground.

TEST: Used for Test Mode. For normal operation, it
should be connected to V

RESET: Reset the MCU.

: Input to the inverting oscillator amplifier and input to

the internal main clock operating circuit.

OUT

: Output from the inverting oscillator amplifier.

R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
These pins are NOT served on GMS825xx.

R20~R27: R2 is an 8-bit CMOS bidirectional I/O port. R2
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

R30~R37: R3 is an 8-bit CMOS bidirectional I/O port. R3
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

R40~R47: R4 is an 8-bit CMOS bidirectional I/O port. R4
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
R45, R46, R47 are NOT served on GMS825xx.

In addition, R4 serves the functions of the various follow-
ing special features.

R50~R57: R5 is an 8-bit CMOS bidirectional I/O port. R5
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

R50~R53, R56, R57 are NOT served on GMS825xx.

In addition, R5 serves the functions of the various follow-
ing special features.

R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
R60~R63 are NOT served on GMS825xx.

In addition, R6 is shared with the ADC input.

Note: On the MDS(Choice-Dr, Jr), when the MCU is RE-
SET, R60 can not be used digital input port. For more detail,
refer to "9. I/O PORTS" on page 34.

: Supply voltage to the ladder resistor of ADC cir-

cuit. To enhance the resolution of analog to digital convert-
er, use independent power source as well as possible, other
than digital power source.

: ADC circuit ground.

is NOT served on GMS825xx but it is connected to

internally.

Port pin

Alternate function

R40
R41
R42
R43
R44
R45
R46
R47

INT0 (External interrupt 0)
INT1 (External interrupt 1)
INT2 (External interrupt 2)
INT3 (External interrupt 3)
EC0 (Event counter input 0)
EC2 (Event counter input 2)
T1O (Timer/Counter 1 output)
T3O (Timer/Counter 3 output)

Port pin

Alternate function

R50
R51
R52
R53
R54
R55
R56
R57

SIN (Serial data input)
SOUT (Serial data output)
SCLK (Serial clock)
SRDY (Serial ready)
WDTO (Watchdog Timer output)
BUZ (Buzzer driver output)
PWM0 (PWM output 0)
PWM1 (PWM output 1)

Port pin

Alternate function

R60
R61
R62
R63
R64
R66
R66
R67

AN0 (Analog Input 0)
AN1 (Analog Input 1)
AN2 (Analog Input 2)
AN3 (Analog Input 3)
AN4 (Analog Input 4)
AN5 (Analog Input 5)
AN6 (Analog Input 6)
AN7 (Analog Input 7)

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

This pins are Not Served on GMS825xx.

1. The parenthesis means alternate function.

PIN NAME

In/Out

Function

Basic

Alternate

Supply voltage

Circuit ground

TEST

Controls test mode of the chip,
For normal operation, it should be connected at V

RESET

Reset signal input

Oscillation input

OUT

Oscillation output

R00~R07

I/O

8-bit general I/O ports

R10~R17

I/O

8-bit general I/O ports

R20~R27

I/O

8-bit general I/O ports

R30~R37

I/O

8-bit general I/O ports

R40 (INT0)

I/O (I)

8-bit general I/O ports

External interrupt 0 input

R41 (INT1)

I/O (I)

External interrupt 1 input

R42 (INT2)

I/O (I)

External interrupt 2 input

R43 (INT3)

I/O (I)

External interrupt 3 input

R44 (EC0)

I/O (I)

Timer/Counter 0 external input

R45 (EC2)

I/O (I)

Timer/Counter 2 external input

R46 (T1O)

I/O (O)

Timer/Counter 1 output

R47 (T3O)

I/O (O)

Timer/Counter 3 output

R50 (SIN)

I/O (I)

8-bit general I/O ports

Serial data input

R51 (SOUT)

I/O (O)

Serial data output

R52 (SCLK)

I/O (I/O)

Serial clock I/O

R53 (SRDY)

I/O (I/O)

Receive enable I/O

R54 (WDTO)

I/O (O)

Watchdog timer overflow output

R55 (BUZ)

I/O (O)

Buzzer driving output

R56 (PWM0)

I/O (O)

PWM pulse output

R57 (PWM1)

I/O (O)

R60~R63 (AN0~AN3)

I (I)

General input ports

Analog voltage input

R64~R67 (AN4~AN7)

I/O (I)

General I/O ports

Ground level input pin for ADC

Supply voltage input pin for ADC

Table 5-1 Port Function Description

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

6. PORT STRUCTURES

R00~R07, R10~R17, R20~R27, R30~37

R40/INT0, R41/INT1, R42/INT2, R43/INT3, R44/
EC0, R45/EC2, R50/SIN

R46/T1O, R47/T3O, R51/SOUT, R54/WDTO
R55/BUZ, R56/PWM0, R57/PWM1

R52/SCLK

S53/SRDY

Data Reg.

Dir.

VSS

Reg.

Data Bus

M U X

Data Bus

Data Reg.

Direction

Reg.

PMR Selection

Alternate Function

EX) INT0

M U X

Data Bus

Data Reg.

Direction

Reg.

M U X

Selection

Secondary function

M U X

Data Bus

Data Reg.

Direction

Reg.

M U X

Selection

SCK Output

M U X

SCK Input

exck

M U X

Data Bus

Data Reg.

Direction

Reg.

M U X

Selection

SRDY Output

SRDY Input

SRDY

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage ............................................. -0.3 to +7.0 V

Storage Temperature .................................. -40 to +125

Voltage on any pin with respect to Ground (V

)

..................................................................-0.3 to V

+0.3

Maximum current out of V

pin .......................... 150 mA

Maximum current into V

pin .............................. 80 mA

Maximum current sunk by (I

per I/O Pin) .......... 20 mA

Maximum output current sourced by (I

per I/O Pin)

................................................................................... 8 mA

Maximum current (

) ...................................... 100 mA

Maximum current (

)........................................ 50 mA

Note: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.

7.2 Recommended Operating Conditions

7.3 A/D Converter Characteristics

=25

C, V

=0V, V

=AV

=5.12V@f

XIN

=8MHz, V

=AV

=3.072V@f

XIN

=4MHz)

Parameter

Symbol

Condition

Specifications

Unit

Min.

Max.

Supply Voltage

XIN

=1 ~ 10 MHz

XIN

=1 ~ 8 MHz

XIN

=1 ~ 4 MHz

4.5
2.7
2.2

5.5
5.5
5.5

Operating Frequency

XIN

=4.5~5.5V

=2.7~5.5V

=2.2~5.5V

1
1
1

8
4

MHz

Operating Temperature

OPR

Normal Version
Temperature Extention Version

-20
-40

85
85

Parameter

Symbol

Specifications

Unit

Min.

Typ.

Max.

XIN

=4MHz

XIN

=8MHz

Analog Input Voltage Range

AIN

Non-linearity Error

NLE

1.0

±1.5

LSB

Differential Non-linearity Error

DNLE

1.0

±1.5

LSB

Zero Offset Error

ZOE

0.5

±1.5

LSB

Full Scale Error

FSE

0.35

±0.5

LSB

Gain Error

1.0

±1.5

LSB

Overall Accuracy

ACC

1.0

±1.5

LSB

Input Current

REF

0.5

1.0

Conversion Time

CONV

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

7.4 DC Electrical Characteristics

=-20~85

C, V

=2.7~5.5V, Ta= -20~85

C, f

XIN

=8MHz, V

=0V)

Analog Power Supply Input Range

0.9V

1.1V

1. Data in "Typ" column is at 25

C unless otherwise stated. These parameters are for design guidance only and are not tested.

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

1. Data in "Typ." column is at 4.5V, 25

C unless otherwise stated. These parameters are for design guidance only and are not tested.

Max.

Input High Voltage

IH1

=4.5

=2.7

, RESET,

R4, R5, R6

0.8V

+0.3

IH2

R0, R1, R2, R3

0.7V

+0.3

Input Low Voltage

IL1

=4.5

=2.7

, RESET,

R4, R5, R6

0.2V

IL2

R0, R1, R2, R3

0.3V

Output High Voltage

=4.5

=2.7

OH1

=-2mA

R0,R1,R2,R3,R4,R5
R6

-1.0

Output Low Voltage

=4.5

=2.7

OL1

=5mA

R0,R1,R2,R3,R4,R5
R6

1.0

Power Fail Detect
Voltage

PFD

=3.0V

PFD

=2.4V

@ T

=25

0.9V

PFD

1.1V

PFD

Input High
Leakage Current

IH1

All input pins

-5.0

5.0

Input Low
Leakage Current

All input pins

-5.0

5.0

Hysteresis

T+

, V

T-

RESET, EC0, EC2,
SIN, SCLK, INT0~INT3

0.3

0.8

Power Current

DD1

XIN

=8M H z

A ll input = V

S S

C rystal O scillator,
C

= C

=30pF

DD2

XIN

=4M H z

STOP

A ll input = V

S S

Parameter

Symbol

Specifications

Unit

Min.

Typ.

Max.

XIN

=4MHz

XIN

=8MHz

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

7.5 AC Characteristics

=-20~+85

C, V

=5V

10%, V

=0V)

Figure 7-1 Timing Chart

Parameter

Symbol

Pins

Specifications

Unit

Min.

Typ.

Max.

Operating Frequency

XIN

1.0

10.0

MHz

Oscillation Stabilizing
Time

, X

OUT

External Clock Pulse
Width

CPW

External Clock Transi-
tion Time

RCP,

FCP

Interrupt Pulse Width

INT0, INT1, INT2, INT3

SYS

RESET Input Width

RST

RESET

SYS

Event Counter Input
Pulse Width

ECW

EC0, EC2

SYS

Event Counter Transi-
tion Time

REC,

FEC

EC0, EC2

RCP

FCP

XIN

INT0~INT3

0.5V

-0.5V

0.2V

0.8V

0.2V

RESET

REC

FEC

0.2V

0.8V

EC0, EC2

RST

ECW

SYS

= 1/f

XIN

CPW

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

7.6 Serial Interface Timing Characteristics

=-20~+85

C, V

=5V

10%, V

=0V, f

XIN

=8MHz)

Figure 7-2 Serial I/O Timing Chart

Parameter

Symbol

Pins

Specifications

Unit

Min.

Typ.

Max.

Serial Input Clock Pulse

SCYC

SCLK

SYS

+200

Serial Input Clock Pulse Width

SCKW

SCLK

SYS

+70

Serial Input Clock Pulse Transition
Time

FSCK

RSCK

SCLK

SIN Input Pulse Transition Time

FSIN

RSIN

SIN

SIN Input Setup Time (External SCLK)

SUS

SIN

100

SIN Input Setup Time (Internal SCLK)

SUS

SIN

200

SIN Input Hold Time

SIN

SYS

+70

Serial Output Clock Cycle Time

SCYC

SCLK

SYS

16t

SYS

Serial Output Clock Pulse Width

SCKW

SCLK

SYS

-30

Serial Output Clock Pulse Transition
Time

FSCK

RSCK

SCLK

Serial Output Delay Time

OUT

SOUT

100

SCLK

SIN

0.2V

SOUT

0.2V

0.8V

SCYC

SCKW

RSCK

FSCK

0.8V

SUS

0.2V

0.8V

RSIN

FSIN

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

7.7 Typical Characteristic Curves

This graphs and tables provided in this section are for de-
sign guidance only and are not tested or guaranteed.

In some graphs or tables the data presented are out-
side specified operating range (e.g. outside specified
V

range). This is for information only and devices

are guaranteed to operate properly only within the
specified range.

The data presented in this section is a statistical summary
of data collected on units from different lots over a period
of time. "Typical" represents the mean of the distribution
while "max" or "min" represents (mean + 3

) and (mean

) respectively where

is standard deviation

IH2

(V)

IH2

(V)

IH1

(V)

IH1

(V)

Ta=25

XIN

=8MHz

Ta=25

XIN

=8MHz

XIN, RESET,

R0, R1, R2, R3 pins

-12

-9

-6

-3

0.3

0.6

0.9

1.2

1.5 (V)

Ta=25

=4.5V

R0~R6 pins

(mA)

-V

OL1

(mA)

0.2

0.4

0.6

0.8

1.0

(V)

Ta=25

=4.5V

R0~R6 pins

-12

-9

-6

-3

0.3

0.6

0.9

1.2

1.5 (V)

Ta=25

=3.0V

R0~R6 pins

(mA)

-V

OL2

(mA)

0.2

0.4

0.6

0.8

1.0

(V)

Ta=25

=3.0V

R0~R6 pins

R4, R5, R6 pins

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

8. MEMORY ORGANIZATION

The GMS81508B/16B/24B and GMS82512/16/24 have
separate address spaces for Program memory and Data
Memory. Program memory can only be read, not written

to. It can be up to 24K bytes of Program memory. Data
memory can be read and written to up to 448 bytes includ-
ing the stack area.

8.1 Registers

This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.

Figure 8-1 Configuration of Registers

Accumulator: The Accumulator is the 8-bit general pur-
pose register, used for data operation such as transfer, tem-
porary saving, and conditional judgement, etc.

The Accumulator can be used as a 16-bit register with Y
Register as shown below.

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the spec-
ified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have in-
crement, decrement, comparison and data transfer func-
tions, and they can be used as simple accumulators.

Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).

Generally, SP is automatically updated when a subroutine

call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.

The stack can be located at any position within 100

1FF

of the internal data memory. The SP is not initialized

by hardware, requiring to write the initial value (the loca-
tion with which the use of the stack starts) by using the ini-
tialization routine. Normally, the initial value of "FE

" is

used.

Note: The Stack Pointer must be initialized by software be-
cause its value is undefined after RESET.

Example: To initialize the SP

LDX

#0FEH

TXSP

; SP

FEH

Address 01FF

can not be used as stack. Don not use

1FF

, or malfunction would be occurred.

Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset rou-
tine address (PC

:0FF

, PC

:0FE

Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3. It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.

ACCUMULATOR

X REGISTER

Y REGISTER

STACK POINTER

PROGRAM COUNTER

PROGRAM STATUS

WORD

PCL

PSW

PCH

Two 8-bit Registers can be used as a "YA" 16-bit Register

Stack Address (100

~ 1FE

)

Bit 15

Bit 0

8 7

Hardware fixed

~FE

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

[Zero flag Z]

This flag is set when the result of an arithmetic operation

or data transfer is "0" and is cleared by any other result.

Figure 8-3 PSW (Program Status Word) Register

[Interrupt disable flag I]

This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to "0". This flag immedi-
ately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.

[Half carry flag H]

After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
dress.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00

to 0FF

when this flag is "0". If it is set to "1",

addressing area is assigned 100

to 1FF

. It is set by

SETG instruction and cleared by CLRG.

[Overflow flag V]

This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
ceeds +127(7F

) or -128(80

). The CLRV instruction

clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.

NEGATIVE FLAG

MSB

LSB

RESET VALUE: 00

PSW

OVERFLOW FLAG

BRK FLAG

CARRY FLAG RECEIVES

ZERO FLAG

INTERRUPT ENABLE FLAG

CARRY OUT

HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS

SELECT DIRECT PAGE

when G=1, page is selected to "page 1"

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Figure 8-4 Stack Operation

At execution of
a CALL/TCALL/PCALL

PCL

PCH

01FB

SP after
execution

SP before
execution

01FC

01FD

01FE

Push
down

At acceptance
of interrupt

PCL

PCH

01FB

01FC

01FD

01FE

Push
down

PSW

At execution
of RET instruction

PCL

PCH

01FB

01FE

01FC

01FD

01FE

01FC

Pop
up

At execution
of RET instruction

PCL

PCH

01FB

01FE

01FC

01FD

01FE

01FB

Pop
up

PSW

0100H

01FEH

Stack
depth

At execution
of PUSH instruction

01FB

01FD

01FC

01FD

01FE

Push
down

SP after
execution

SP before
execution

PUSH A (X,Y,PSW)

At execution
of POP instruction

01FB

01FE

01FC

01FD

01FE

01FD

Pop
up

POP A (X,Y,PSW)

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

8.2 Program Memory

A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 24K bytes program memory
space only physically implemented. Accessing a location
above FFFF

will cause a wrap-around to 0000

Figure 8-5, shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFE

and FFFF

as shown in Figure 8-6.

As shown in Figure 8-5, each area is assigned a fixed loca-
tion in Program Memory. Program Memory area contains
the user program.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL in-
stead of 3 bytes CALL instruction. If it is frequently called,

it is more useful to save program byte length.

Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0

for TCALL15, 0FFC2

for

TCALL14, etc., as shown in Figure 8-7.

Example: Usage of TCALL

The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to loca-
tion 0FFFA

. The interrupt service locations spaces 2-byte

interval: 0FFF8

and 0FFF9

for External Interrupt 1,

0FFFA

and 0FFFB

for External Interrupt 0, etc.

Any area from 0FF00

to 0FFFF

, if it is not going to be

used, its service location is available as general purpose
Program Memory.

Figure 8-6 Interrupt Vector Area

Interrupt

Vector Area

D000

FEFF

FF00

FFC0

FFDF

FFE0

FFFF

PCALL area

E000

C000

TCALL area

1508B

,
8K

GMS81516B/GMS82516, 16K ROM

GMS81524B/GMS82524, 24K ROM

GMS82512, 12K ROM

A000

0FFE0

Address

Vector Area Memory

E4
E6
E8
EA
EC
EE
F0

F2
F4
F6
F8
FA
FC
FE

-
-

Serial Communication Interface

Basic Interval Timer

-
-
-

External Interrupt 2

Timer/Counter 1 Interrupt

External Interrupt 0

RESET Vector Area

External Interrupt 1

Watchdog Timer Interrupt

"-" means reserved area.

NOTE:

Timer/Counter 2 Interrupt

External Interrupt 3

Timer/Counter 0 Interrupt

Timer/Counter 3 Interrupt

A/D Converter

" is NOT served on GMS825xx.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Figure 8-7 PCALL and TCALL Memory Area

PCALL

rel

4F35

PCALL 35H

TCALL

TCALL 4

0FFC0

Address

Program Memory

C2
C3
C4
C5
C6
C7
C8

0FF00

Address

PCALL Area Memory

0FFFF

PCALL Area

(256 Bytes)

* means that the BRK software interrupt is using

same address with TCALL0.

NOTE:

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

TCALL 8

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF

0FF35

0FF00

0FFFF

11111111 11010110

01001010

PC:

DH 6H

0FFD6

0FF00

0FFFF

0FFD7

0D125

Reverse

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Example: The usage software example of Vector address for GMS81524B.

ORG

0FFE0H

NOT_USED

SIO

; Serial Interface

BIT_TIMER

; Basic Interval Timer

WD_TIMER

; Watchdog Timer

ADC

; ADC

TIMER3

; Timer-3

TIMER2

; Timer-2

TIMER1

; Timer-1

TIMER0

; Timer-0

INT3

; Int.3

INT2

; Int.2

INT1

; Int.1

INT0

; Int.0

NOT_USED

; -

RESET

; Reset

ORG

0A000H

; 24K ROM Start address

;

ORG

0C000H

; 16K ROM Start address

;

ORG

0D000H

; 12K ROM Start address

;

ORG

0E000H

; 8K ROM Start address

;*******************************************
;

MAIN PROGRAM

;*******************************************
;
RESET:

;Disable All Interrupts

CLRG
LDX

RAM_CLR: LDA

;RAM Clear(!0000H->!00BFH)

STA

{X}+

CMPX

#0C0H

BNE

RAM_CLR

;

LDX

#0FEH

;Stack Pointer Initialize

TXSP

;

LDM

R0, #0

;Normal Port 0

LDM

R0DD,#82H

;Normal Port Direction

:
:
:
LDM

TDR0,#250

;8us x 250 = 2000us

LDM

TM0,#1FH

;Start Timer0, 8us at 8MHz

LDM

IRQH,#0

LDM

IRQL,#0

LDM

IENH,#0C8H

;Enable Timer0, INT0, INT1

LDM

IENL,#0

LDM

IEDS,#55H

;Select falling edge detect on INT pin

LDM

PMR4,#3H

;Set external interrupt pin(INT0, INT1)

;Enable master interrupt

:
:
:

:
:

NOT_USED:NOP

RETI

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa-
ble. Data Memory is divided into four groups, a user RAM,
control registers, Stack, and LCD memory.

Figure 8-8 Data Memory Map

User Memory

The GMS815xxB and GMS825xx have 448

8 bits for the

user memory (RAM).

Control Registers

The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore, these registers contain control and sta-
tus bits for the interrupt system, the timer/ counters, analog
to digital converters and I/O ports. The control registers are
in address range of 0C0

to 0FF

Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.

More detailed informations of each register are explained
in each peripheral section.

Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write instruc-
tion. Use byte manipulation instruction, for example "LDM".

Example; To write at CKCTLR

LDM

CLCTLR,#09H

;Divide ratio(

32)

Stack Area

The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.

When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.

The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 23.

User Memory

Control

Registers

or Stack Area

0000

00BF

00C0

00FF

0100

01FF

PAGE0

User Memory

PAGE1

When "G-flag=0",

When "G-flag=1"

this page is selected

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Address

Register Name

Symbol

R/W

Initial Value

Page

7 6 5 4 3 2 1 0

00C0

R0 port data register

R/W

Undefined

page 34

00C1

R0 port I/O direction register

R0DD

0 0 0 0 0 0 0 0

page 34

00C2

R1 port data register

R/W

Undefined

page 34

00C3

R1 port I/O direction register

R1DD

0 0 0 0 0 0 0 0

page 34

00C4

R2 port data register

R/W

Undefined

page 34

00C5

R2 port I/O direction register

R2DD

0 0 0 0 0 0 0 0

page 34

00C6

R3 port data register

R/W

Undefined

page 34

00C7

R3 port I/O direction register

R3DD

0 0 0 0 0 0 0 0

page 34

00C8

R4 port data register

R/W

Undefined

page 34

00C9

R4 port I/O direction register

R4DD

0 0 0 0 0 0 0 0

page 34

00CA

R5 port data register

R/W

Undefined

page 34

00CB

R5 port I/O direction register

R5DD

0 0 0 0 0 0 0 0

page 34

00CC

R6 port data register

R/W

Undefined

page 34

00CD

R6 port I/O direction register

R6DD

0 0 0 0 - - - -

page 34

00D0

R4 port mode register

PMR4

0 0 0 0 0 0 0 0

page 34, page 66

00D1

R5 port mode register

PMR5

- - 0 0 - - - -

page 34, page 58

00D3

Basic interval timer mode register

BITR

Undefined

page 37

Clock control register

CKCTLR

- - 0 1 0 1 1 1

page 37

00E0

Watchdog Timer Register

WDTR

- 0 1 1 1 1 1 1

page 67

00E2

Timer mode register 0

TM0

R/W

0 0 0 0 0 0 0 0

page 39

00E3

Timer mode register 2

TM2

R/W

0 0 0 0 0 0 0 0

page 39

00E4

Timer 0 data register

TDR0

Undefined

page 39

Timer 0 counter register

Undefined

page 39

00E5

Timer 1 data register

TDR1

Undefined

page 39

Timer 1 counter register

Undefined

page 39

00E6

Timer 2 data register

TDR2

Undefined

page 39

Timer 2 counter register

Undefined

page 39

00E7

Timer 3 data register

TDR3

Undefined

page 39

Timer 3 counter register

Undefined

page 39

00E8

A/D converter mode register

ADCM

R/W

- - 0 0 0 0 0 1

page 49

00E9

A/D converter data register

ADR

Undefined

page 49

00EA

Serial I/O mode register

SIOM

R/W

- 0 0 0 0 0 0 1

page 51

00EB

Serial I/O register

SIOR

R/W

Undefined

page 51

00EC

Buzzer driver register

BUR

Undefined

page 58

Table 8-1 Control Registers

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

00F0

PWM0 duty register

PWMR0

Undefined

page 55

00F1

PWM1 duty register

PWMR1

Undefined

page 55

00F2

PWM control register

PWMCR

0 0 0 0 0 0 0 0

page 55

00F4

Interrupt enable register low

IENL

R/W

0 0 0 0 - - - -

page 60

00F5

Interrupt request flag register low

IRQL

R/W

0 0 0 0 - - - -

page 60

00F6

Interrupt enable register high

IENH

R/W

0 0 0 0 0 0 0 0

page 60

00F7

Interrupt request flag register high

IRQH

R/W

0 0 0 0 0 0 0 0

page 60

00F8

External interrupt edge selection register

IEDS

0 0 0 0 0 0 0 0

page 60

00F9

Power fail detection register

PFDR

R/W

- - - - 1 1 0 0

page 74

Address

Register Name

Symbol

R/W

Initial Value

Page

7 6 5 4 3 2 1 0

Table 8-1 Control Registers

Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation

Registers are controlled by both bit and byte manipulation instruction.

R/W

instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.

- : this bit location is reserved.

: this bit is NOT served on GMS825xx.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

8.4 Addressing Mode

The GMS800 series MCU uses six addressing modes;

· Register addressing

· Immediate addressing

· Direct page addressing

· Absolute addressing

· Indexed addressing

· Register-indirect addressing

(1) Register Addressing

(2) Immediate Addressing

#imm

In this mode, second byte (operand) is accessed as a data
immediately.

Example:

0435

ADC

#35H

When G-flag is 1, then RAM address is defined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.

Example: G=1

E45535

LDM

35H,#55H

(3) Direct Page Addressing

In this mode, a address is specified within direct page.

Example; G=0

C535

LDA

35H

RAM[35H]

A+35H+C

MEMORY

0F100H

data ¨ 55H

data

0135H

0F102H

0F101H

data

35H

0E551H

data

0E550H

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

(4) Absolute Addressing

!abs

Absolute addressing sets corresponding memory data to
Data, i.e. second byte (Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY

Example;

0735F0

ADC

!0F035H

ROM[0F035H]

The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

regard-

less of G-flag.

983501

INC

!0135H

ROM[135H]

(5) Indexed Addressing

X indexed direct page (no offset)

{X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15

, G=1

LDA

{X}

;ACC

RAM[X].

X indexed direct page, auto increment

{X}+

In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.

LDA, STA

Example; G=0, X=35

LDA

{X}+

X indexed direct page (8 bit offset)

dp+X

This address value is the second byte (Operand) of com-
mand plus the data of

-register. And it assigns the mem-

ory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5

0F100H

data

0F035H

0F102H

0F101H

A+data+C

address: 0F035

0F100H

data

135H

0F102H

0F101H

data+1

data

address: 0135

data

115H

0E550H

data

35H

data Æ A

36H Æ X

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

C645

LDA

45H+X

Y indexed direct page (8 bit offset)

dp+Y

This address value is the second byte (Operand) of com-
mand plus the data of Y-register, which assigns Memory in
Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute

!abs+Y

Sets the value of 16-bit absolute address plus Y-register
data as Memory.This addressing mode can specify memo-
ry in whole area.

Example; Y=55

D500FA

LDA

!0FA00H+Y

(6) Indirect Addressing

Direct page indirect

[dp]

Assigns data address to use for accomplishing command
which sets memory data (or pair memory) by Operand.
Also index can be used with Index register X,Y.

JMP, CALL

Example; G=0

3F35

JMP

[35H]

X indexed indirect

[dp+X]

Processes memory data as Data, assigned by 16-bit pair
m e m o r y w h i c h i s d e t e r m i n e d b y p a i r d a t a
[dp+X+1][dp+X] Operand plus

X-register data in Direct

page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10

1625

ADC

[25H+X]

Y indexed indirect

[dp]+Y

Processes memory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Di-
rect page

plus Y-register data.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, Y=10

data

3AH

0E551H

data

0E550H

45H+0F5H=13AH

0F100H

data

0FA55H

0FA00H+55H=0FA55H

0F102H

0F101H

35H

jump to

0FA00H

36H

0E30AH

address 0E30AH

35H

0E005H

0FA00H

36H

0E005H

data

A + data + C

25 + X(10) = 35H

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

9. I/O PORTS

The GMS815xxB and GMS825xx have four input ports
and fifty two input/output ports(R00~R67) and the
GMS825xx has thirty five input/output ports. These ports
pins may be multiplexed with an alternate function for the
peripheral features on the device.

All pins have data direction registers which can define
these ports as output or input. A "1" in the port direction
register configure the corresponding port pin as output.
Conversely, write "0" to the corresponding bit to specify it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbered bits as input
ports, write "55

" to address 0C1

(R0 port direction reg-

ister) during initial setting as shown in Figure 9-1.

All the port direction registers in the GMS815xxB and
GMS825xx have 0 written to them by reset function. On
the other hand, its initial status is input.

Figure 9-1 Example of port I/O assignment

R0 and R0DD register: R0 is an 8-bit CMOS bidirection-
al I/O port (address 0C0

). Each I/O pin can independently

used as an input or an output through the R0DD register
(address 0C1

R1 and R1DD register: R1 is an 8-bit CMOS bidirection-
al I/O port (address 0C2

). Each I/O pin can independently

used as an input or an output through the R1DD register
(address 0C3

R10~R17 are NOT served on GMS825xx.

R2 and R2DD register: R2 is an 8-bit CMOS bidirection-
al I/O port (address 0C4

). Each I/O pin can independently

used as an input or an output through the R2DD register
(address 0C5

I: INPUT PORT

WRITE "55

" TO PORT R0 DIRECTION REGISTER

0 1 0 1 0 1 0 1

I O I O I O I O

R0 data

R1 data

R0 direction

R1 direction

0C0

0C1

0C2

0C3

7 6 5 4 3 2 1 0

BIT

7 6 5 4 3 2 1 0

PORT

O: OUTPUT PORT

R0 Data Register

ADDRESS: 0C0

RESET VALUE: Undefined

R07 R06 R05 R04 R03 R02 R01 R00

Port Direction

R0 Direction Register

R0DD

ADDRESS: 0C1

RESET VALUE: 00

0: Input
1: Output

Input / Output data

R1 Data Register

ADDRESS: 0C2

RESET VALUE: Undefined

R17 R16 R15 R14 R13 R12 R11 R10

Port Direction

R1 Direction Register

R1DD

ADDRESS: 0C3

RESET VALUE: 00

0: Input
1: Output

Input / Output data

R2 Data Register

ADDRESS: 0C4

RESET VALUE: Undefined

R27 R26 R25 R24 R23 R22 R21 R20

Port Direction

R2 Direction Register

R2DD

ADDRESS: 0C5

RESET VALUE: 00

0: Input
1: Output

Input / Output data

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

R3 and R3DD register: R3 is an 8-bit CMOS bidirection-
al I/O port (address 0C6

). Each I/O pin can independently

used as an input or an output through the R3DD register
(address 0C7

R4 and R4DD register: R4 is an 8-bit CMOS bidirection-
al I/O port (address 0C8

). Each I/O pin can independently

used as an input or an output through the R4DD register
(address 0C9

In addition, Port R4 is multiplexed with various special
features. The control register PMR4 (address 0D0

) con-

trols the selection of alternate function. After reset, this
value is "0", port may be used as normal I/O port.
To use alternate function such as external interrupt, exter-
nal counter input or timer clock out, write "1" in the corre-
sponding bit of PMR4.

R45~R47 are NOT served on GMS825xx.

Regardless of the direction register R4DD, PMR4 is select-
ed to use as alternate functions, port pin can be used as a
corresponding alternate features.

Port Pin

Alternate Function

R40
R41
R42
R43
R44

R45

R46
R47

INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
INT2 (External Interrupt 2)
INT3 (External Interrupt 3)
EC0 (External count input to Timer/
Counter 0)
EC2 (External count input to Timer/
Counter 2)
T1O (Timer 1 Clock-out)
T3O (Timer 3 Clock-out)

R3 Data Register

ADDRESS: 0C6

RESET VALUE: Undefined

R37 R36 R35 R34 R33 R32 R31 R30

Port Direction

R3 Direction Register

R3DD

ADDRESS: 0C7

RESET VALUE: 00

0: Input
1: Output

Input / Output data

R4 Port Mode Register

PMR4

ADDRESS: 0D0

RESET VALUE: 00

0: R40
1: INT0

0: R41
1: INT1

0: R42
1: INT2

0: R43
1: INT3

0: R44
1: EC0

0: R45
1: EC2

0: R46
1: T1O

0: R47
1: T3O

Edge Selection Register

IEDS

ADDRESS: 0F8H
RESET VALUE: 00H

INT0

INT1

INT2

INT3

External Interrupt Edge Select

00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)

R4 Data Register

ADDRESS: 0C8

RESET VALUE: Undefined

R47 R46 R45 R44 R43 R42 R41 R40

Port Direction

R4 Direction Register

R4DD

ADDRESS: 0C9

RESET VALUE: 00

0: Input
1: Output

Input / Output data

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

R5 and R5DD register: R5 is an 8-bit CMOS bidirection-
al I/O port (address 0CA

). Each I/O pin can independent-

ly used as an input or an output through the R5DD register
(address 0CB

The control register PMR5 (address D1

) controls the se-

lection alternate function. After reset, this value is "0", port
may be used as general I/O ports. To use buzzer function,
write "1" to the PMR5 and the pin R55 must be defined as
output mode (the bit 5 of R5DD=1).

Also, Port R5 can be used to alternate function by SI-
OM(address 0EAH) and PWMCR(0F2H).

R50~R53, R56 and R57 are NOT served on GMS825xx.

R6 and R6DD register: R6 is an 8-bit CMOS bidirection-
al I/O port (address 0CC

). Each I/O pin can independent-

ly used as an input or an output through the R6DD register
(address 0CD

R60~R63 are NOT served on GMS825xx.

R6DD (address CD

) controls the direction of the R6 pins,

even when they are being used as analog inputs. The user
must make sure to keep the pins configured as inputs when
using them as analog inputs.

Note: On the MDS(Choice-Dr,Jr), when the MCU is RE-
SET, R60 can not be used digital input port, because this
port is selected as an analog input port by ADCM register.
To use this port as a digital I/O port, change the value of
lower 4 bits of ADCM (address 0E8

). On the other hand,

R6 port, all eight pins can not be used as digital I/O port si-
multaneously on the MDS. At least one pin is used as an
analog input. But on the OTP and Main chip, R6 port, all
eight pins can be used as digital I/O port at the same time.

Port Pin

Alternate Function

R50
R51
R52
R53
R54
R55
R56
R57

SIN(Serial data input)
SOUT(Serial data output)
SCLK(Serial clock)
SRDY(ready signal)
WDTO (Watchdog timer output)
BUZ (Square-wave output for buzzer)
PWM0
PWM1

R5 Port Mode Register

PMR5

ADDRESS: 0D1

RESET VALUE: --00----

R54/WDTO Selection

BUZ

0: R54
1: WDTO (Output)

R55/BUZ Selection
0: R55
1: BUZ (Output)

W D TO

R5 Data Register

ADDRESS: 0CA

RESET VALUE: Undefined

R57 R56 R55 R54 R53 R52 R51 R50

Port Direction

R5 Direction Register

R5DD

ADDRESS: 0CB

RESET VALUE: 00

0: Input
1: Output

Input / Output data

Port Pin

Alternate Function

R60
R61
R62
R63
R64
R65
R66
R67

AN0 (ADC input 0)
AN1 (ADC input 1)
AN2 (ADC input 2)
AN3 (ADC input 3)
AN4 (ADC input 4)
AN5 (ADC input 5)
AN6 (ADC input 6)
AN7 (ADC input 7)

R6 Data Register

ADDRESS: 0CC

RESET VALUE: Undefined

R67 R66 R65 R64 R63 R62 R61 R60

Port Direction

R6 Direction Register

R6DD

ADDRESS: 0CD

RESET VALUE: 0000----

0: Input
1: Output

Input / Output data

R60~R63 are input

Input data

only

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

10. BASIC INTERVAL TIMER

The GMS815xxB and GMS825xx have one 8-bit Basic In-
terval Timer that is free-run and can not stop. Block dia-
gram is shown in Figure 10-1.

In addition, the Basic Interval Timer generates the time
base for watchdog timer counting. It also provides a Basic
interval timer interrupt (BITIF). As the count overflow
from FF

to 00

, this overflow causes the interrupt to be

generated. The Basic Interval Timer is controlled by the
clock control register (CKCTLR) shown in Figure 10-2.

Source clock can be selected by lower 3 bits of CKCTLR.

BITR and CKCTLR are located at same address, and ad-
dress 0F9

is read as a BITR, and written to CKCTLR.

Figure 10-1 Block Diagram of Basic Interval Timer

Table 10-1 Basic Interval Timer Interrupt Time

MUX

Basic Interval Timer Interrupt

BITR

Select Input clock 3

Basic Interval Timer

source
clock

8-bit up-counter

BTS[2:0]

BTCL

2048

1024

512

256

128

To Watchdog timer (WDTCK)

CKCTLR

clear

overflow

Internal bus line

clock control register

[0D3

]

[0F9

]

BITIF

Read

Prescaler

CKCTLR

[2:0]

Source clock

Interrupt (overflow) Period (ms)

@ f

XIN

= 8MHz

000
001
010
011
100
101
110
111

XIN

128

XIN

256

XIN

512

XIN

1024

XIN

2048

0.512
1.024
2.048
4.096
8.192

16.384
32.768
65.536

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Figure 10-2 BITR: Basic Interval Timer Mode Register

Example 1:

Interrupt request flag is generated every 8.192ms at 4MHz.

:
LDM

CKCTLR,#1BH

SET1

BITE

EI
:

Example 2:

Interrupt request flag is generated every 8.192ms at 8MHz.

:
LDM

CKCTLR,#1CH

SET1

BITE

EI
:

BTCL

WDTON

BTS1

Basic Interval Timer source clock select
000: f

XIN

001: f

XIN

010: f

XIN

011: f

XIN

128

100: f

XIN

256

101: f

XIN

512

110: f

XIN

1024

111: f

XIN

2048

Clear bit

0: Normal operation (free-run)

1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically

INITIAL VALUE: --01 0111

ADDRESS: 0D3

after one machine cycle, and starts counting.

CKCTLR

INITIAL VALUE: Undefined

ADDRESS: 0D3

BITR

Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.

Caution:

8-BIT FREE-RUN BINARY COUNTER

ENPCK

BTS0

BTS2

BTCL

Enable Peripheral clock

If this bit is 0, all peripherals are disabled such as Timer, ADC, PWM, etc.

0: Operate as a 6-bit general timer
1: Enable Watchdog Timer operation
See the section "Watchdog Timer".

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

11. TIMER/EVENT COUNTER

The GMS815xxB and GMS825xx have four Timer/
Counter registers. Each module can generate an interrupt
to indicate that an event has occurred (i.e. timer match).

Timer 0 and Timer 1 are can be used either two 8-bit Tim-
er/Counter or one 16-bit Timer/Counter with combine
them. Also Timer 2 and Timer 3 are same.

In the "timer" function, the register is increased every in-
ternal clock input. Thus, one can think of it as counting in-
ternal clock input. Since a least clock consists of 4 and
most clock consists of 64 oscillator periods, the count rate
is 1/4 to 1/64 of the oscillator frequency.

In the "counter" function, the register is incremented in re-
sponse to a 1-to-0 (in case of falling edge) transition at its
corresponding external input pin, EC0 or EC2.

(EC2 are NOT served on GMS825xx.)

In addition the "capture" function, the register is incre-
mented in response external or internal clock sources same
with timer or counter function. When external clock edge
input, the count register is captured into Timer data register
correspondingly.

It has four operating modes: "8-bit timer/counter", "16-bit
timer/counter", "8-bit capture", "16-bit capture" which are
selected by bit in Timer mode register TM0 and TM2 as
shown in Table 11-1.

In operation of Timer 2, Timer 3, their operations are same
with Timer 0, Timer 1, respectively as shown in Table 11-
2.

EC0, EC2, T1O(Timer 3 rectangular pulse output) and

T3O are determined by PMR4.

TM0

TIMER 0

TIMER 1

CAP

T1ST

T1SL

[1:0]

T0ST

T0CN

T0SL[1:0]

01 or
10 or

01 or 10 or 11

8-bit Timer

8-bit Event counter

8-bit Timer

01 or 10 or 11

8-bit Capture (internal clock)

8-bit Timer

8-bit Capture (external clock)

8-bit Timer

01 or 10 or 11

16-bit Timer

16-bit Event counter

01 or 10 or 11

16-bit Capture (internal clock)

16-bit Capture (external clock)

Table 11-1 TM0 Timer Mode Register

TM2

TIMER 2

TIMER 3

CAP

T3ST

T3SL

[1:0]

T2ST

T2CN

T2SL[1:0]

01 or
10 or

01 or 10 or 11

8-bit Timer

8-bit Event counter

8-bit Timer

01 or 10 or 11

8-bit Capture (internal clock)

8-bit Timer

8-bit Capture (external clock)

8-bit Timer

01 or 10 or 11

16-bit Timer

16-bit Event counter

01 or 10 or 11

16-bit Capture (internal clock)

16-bit Capture (external clock)

Table 11-2 TM2 Timer Mode Register

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Figure 11-1 TM0, TM2 Registers

BTCL

T3ST

CAP2

T2SL1

INITIAL VALUE: 00

ADDRESS: 0E3

TM2

T2SL0

T2CN

T2ST

T3SL1 T3SL0

Bit Name

Bit Posi-
tion

Description

CAP2

TM2.7

0: Timer/Counter mode
1: Capture mode selection flag

T3ST

TM2.6

0: When cleared, stop the counting.
1: When set, Timer 3 count register is cleared and start again.

T3SL1
T3SL0

TM2.5
TM2.4

00: 16-bit mode (Clock source is selected by T2SL1, T2SL0)
01: 8-bit mode, Clock source is f

XIN

10: 8-bit mode, Clock source is f

XIN

11: 8-bit mode, Clock source is f

XIN

T2ST

TM2.3

0: When cleared, stop the counting.
1: When set, Timer 2 Count Register is cleared and start again.

T2CN

TM2.2

0: Stop the timer
1: A logic 1 starts the timer.

T2SL1
T2SL0

TM2.1
TM2.0

00: EC2 (External clock)
01: 8-bit Timer, Clock source is f

XIN

10: 8-bit Timer, Clock source is f

XIN

11: 8-bit Timer, Clock source is f

XIN

TIMER 2

B T C L

T 1S T

C A P 0

T 0S L1

IN IT IA L V A LU E : 00

A D D R E S S : 0E 2

TM0

T 0S L0

T 0C N

T 0S T

T 1S L1 T 1S L0

Bit Name

Bit Position

Description

CAP0

TM0.7

0: Timer/Counter mode
1: Capture mode selection flag

T1ST

TM0.6

0: When cleared, stop the counting.
1: When set, Timer 1 count register is cleared and start again.

T1SL1
T1SL0

TM0.5
TM0.4

00: 16-bit mode (Clock source is selected by T0SL1, T0SL0)
01: 8-bit mode, Clock source is f

XIN

10: 8-bit mode, Clock source is f

XIN

11: 8-bit mode, Clock source is f

XIN

T0ST

TM0.3

0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.

T0CN

TM0.2

0: Stop the timer
1: A logic 1 starts the timer.

T0SL1
T0SL0

TM0.1
TM0.0

00: EC0 (External clock)
01: 8-bit Timer, Clock source is f

XIN

10: 8-bit Timer, Clock source is f

XIN

11: 8-bit Timer, Clock source is f

XIN

TIMER 1

TIMER 0

INITIAL VALUE: Undefined

ADDRESS: 0E4

~ 0E7

TDR0~TDR3

Read: Count value read

Write: Compare data write

R/W R/W R/W R/W R/W R/W R/W R/W

R/W

TIMER 3

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

11.1 8-bit Timer / Counter Mode

The GMS815xxB and GMS825xx have four 8-bit Timer/
Counters, Timer 0, Timer 1, Timer 2, Timer 3. The Timer
0, Timer 1 are shown in Figure .

The "timer" or "counter" function is selected by control
registers TM0, TM2 as shown in Table 11-1 and Table 11-
2. To use as an 8-bit timer/counter mode, bit CAP0 of TM0
is cleared to "0" and bits T1SL1, T1SL0 of TM0 or bits

T3SL1, T3SL0 of TM2 should not set to zero. These timers
have each 8-bit count register and data register. The count
register is increased by every internal or external clock in-
put. The internal clock has a prescaler divide ratio option
of 4, 16, 64 (selected by control bits TxSL1, TxSL0 of reg-
ister TMx).

Figure 11-2 8-bit Timer/Counter 0, 1

Example 1:

Timer0 = 4ms 8-bit timer mode at 4MHz
Timer1 = 1ms 8-bit timer mode at 4MHz

LDM

TDR0,#250

LDM

TDR1,#250

LDM

TM0,#0110_1111B

SET1

T0E

SET1

T1E

Example 2:

Timer0 = 8-bit event counter mode
Timer1 = 1ms 8-bit timer mode at 4MHz

LDM

TDR0,#250

LDM

TDR1,#250

LDM

TM0,#0110_1100B

SET1

T0E

SET1

T1E

EC0 PIN

XIN PIN

MUX

Prescaler

T0IF

clear

0: Stop
1: Clear and start

T0ST

T0SL[1:0]

TIMER 0
INTERRUPT

T0CN

MUX

T1IF

clear

0: Stop
1: Clear and start

T1ST

T1SL[1:0]

TIMER 1
INTERRUPT

TDR0 (8-bit)

TDR1 (8-bit)

T1 (8-bit)

T0 (8-bit)

Comparator

TIMER 0

TIMER 1

T1O PIN

F/F

BTCL

T1ST

CAP0

T0SL1

INITIAL VALUE: 00

ADDRESS: 0E2

TM0

T0SL0

T0CN

T0ST

T1SL1 T1SL0

X means don't care

01 or 10 or 11

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Note: The contents of Timer data register TDRx should be
initialized 1

~FF

, not 0

, because it is undefined after re-

set.

In the Timer 0, timer register T0 increments from 00

until

it matches TDR0 and then reset to 00H. The match output
of Timer 0 generates Timer 0 interrupt (latched in T0IF bit)

As TDRx and Tx register are in same address, when read-
ing it as a Tx, written to TDRx.

In counter function, the counter is increased every 1-to-0
(falling edge) transition of EC0 or EC2 pin. In order to use
counter function, the bit 4, bit 5 of the Port mode register
PMR4 are set to "1". The Timer 0 can be used as a counter
by pin EC0 input, but Timer 1 can input by internal clock.
Similarly, Timer 2 can be used by pin EC2 input but Timer
3 can not.

EC2 are NOT served on GMS825xx.

Figure 11-3 8-bit Timer/Counter 2, 3

Example 3:

Timer2 = 8-bit timer mode, 2ms interval at 8MHz
Timer3 = 8-bit timer mode, 500us interval at 8MHz

LDM

TDR2,#250

LDM

TDR3,#250

LDM

TM2,#0110_1111B

SET1

T2E

SET1

T3E

Example 4:

Timer2 = 8-bit event counter mode
Timer3 = 500us 8-bit timer mode at 8MHz

LDM

TDR2,#250

LDM

TDR3,#250

LDM

TM2,#0110_1100B

SET1

T2E

SET1

T3E

EC2 PIN

XIN PIN

MUX

Prescaler

T2IF

clear

0: Stop
1: Clear and start

T2ST

T2SL[1:0]

TIMER 2
INTERRUPT

T2CN

MUX

T3IF

clear

0: Stop
1: Clear and start

T3ST

T3SL[1:0]

TIMER 3
INTERRUPT

TDR2 (8-bit)

TDR3 (8-bit)

T3 (8-bit)

T2 (8-bit)

Comparator

TIMER 2

TIMER 3

T3O PIN

F/F

BTCL

T3ST

CAP2

T2SL1

INITIAL VALUE: 00

ADDRESS: 0E3

TM2

T2SL0

T2CN

T2ST

T3SL1 T3SL0

X means don't care

01 or 10 or 11

Edge Detector

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

8-bit Timer Mode

In the timer mode, the internal clock is used for counting
up. Thus, you can think of it as counting internal clock in-
put. The contents of TDRn are compared with the contents
of up-counter, Tn. If match is found, a timer 1 interrupt
(T1IF) is generated and the up-counter is cleared to 0.
Counting up is resumed after the up-counter is cleared.

As the value of TDRn is changeable by software, time in-
terval is set as you want

Figure 11-4 Timer Mode Timing Chart

Figure 11-5 Timer Count Example

Value of

TM[1:0]

Clock
Source

Resolution

(A t f

XIN

=8 M H z)

Maximum Time

Setting

(A t f

XIN

=8 M H z)

EC1

XIN

1/f

EC1

0.5

sec

1/f

EC1

256

128

512

2048

sec

Table 11-1 Timer Source clock Interrupt Time

n-2

n-1

Source clock

Up-counter

TDR1

T1IF interrupt

Start count

Match
Detect

Counter
Clear

Timer 1 (T1IF)
Interrupt

TDR1

TIME

Occur interrupt

Interrupt period

-c

Count Pulse

= 8

s x 125

MATCH

Example: Make 1ms

interrupt using by Timer0 at 8MHz

LDM

TM0,#1FH

; divide by 64

LDM

TDR0,#125

; 8us x 125= 1ms

SET1

T0E

; Enable Timer 0 Interrupt

; Enable Master Interrupt

Period

When

TDR0 = 125

= 7D

XIN

= 8 MHz

INTERRUPT PERIOD =

106 Hz

125 = 1 ms

TM0 = 0001 1111

(8-bit Timer mode, Prescaler divide ratio = 64)

(TDR0 = T0)

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

8-bit Event Counter Mode

In this mode, counting up is started by an external trigger.
This trigger means falling edge of the EC0 or EC2 pin in-
put. Source clock is used as an internal clock selected with
timer mode register TM0 or TM2. The contents of timer
data register TDRn (n = 0,1,2,3) are compared with the
contents of the up-counter Tn. If a match is found, an timer
interrupt request flag TnIF is generated, and the counter is
cleared to "0". The counter is restart and count up contin-
uously by every falling edge of the ECn pin input.

The maximum frequency applied to the ECn pin is f

XIN

[Hz].

In order to use event counter function, the bit 4, 5 of the
Port Mode Register PMR4(address 0D0

) is required to be

set to "1".

EC2 are NOT served on GMS825xx.

After reset, the value of timer data register TDRn is unde-
fined, it should be initialized to between 1

~FF

not to

"0"The interval period of Timer is calculated as below
equation.

Figure 11-6 Event Counter Mode Timing Chart

Figure 11-7 Count Operation of Timer / Event counter

Period (sec)

XIN

-----------

Divide Ratio

TDRn

n-1

n pin input

Up-counter

TDR1

T1IF interrupt

Start count

Timer 1 (T1IF)
Interrupt

TDR1

TIME

Occur interrupt

stop

clear & start

disable

enable

Start & Stop

T1ST

T1CN
Control count

-c

T1ST = 0

T1ST = 1

T1CN = 0

T1CN = 1

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

11.2 16-bit Timer / Counter Mode

The Timer register is being run with all 16 bits. A 16-bit
timer/counter register T0, T1 are incremented from 0000

until it matches TDR0, TDR1 and then resets to 0000

The match output generates Timer 0 interrupt.

The clock source of the Timer 0 is selected either internal
or external clock by bit T0SL1, T0SL0.

Even if the Timer 0 (including the Timer 1) is used as a 16-
bit timer, the Timer 2 and Timer 3 can still be used as either
two 8-bit timer or one 16-bit timer by setting the TM2. Re-
versely, even if the Timer 2 (including the Timer 3) is used
as a 16-bit timer, the Timer 0 and Timer 1 can still be used
as 8-bit timer independently.

Figure 11-8 16-bit Timer/Counter

EC0 PIN

XIN PIN

MUX

Prescaler

T0IF

clear

0: Stop
1: Clear and start

T0ST

T0SL[1:0]

"00"

"01"

"10"

"11"

TIMER 0
INTERRUPT

T0CN

TDR1 + TDR0

Comparator

TIMER 0 + TIMER 1

TIMER 0 (16-bit)

Higher byte Lower byte

(16-bit)

COMPARE DATA

T1 + T0
(16-bit)

(Not Timer 1 interrupt)

EDGE DETECTOR

BTCL

T1ST

CAP0

T0SL1

INITIAL VALUE: 00

ADDRESS: 0E2

TM0

T0SL0

T0CN

T0ST

T1SL1 T1SL0

X means don't care

EC2 PIN

XIN PIN

MUX

Prescaler

T2IF

clear

0: Stop
1: Clear and start

T2ST

T2SL[1:0]

"00"

"01"

"10"

"11"

TIMER 2
INTERRUPT

T2CN

TDR3 + TDR2

Comparator

TIMER 2 + TIMER 3

TIMER 2 (16-bit)

Higher byte Lower byte

(16-bit)

COMPARE DATA

T3 + T2
(16-bit)

(Not Timer 3 interrupt)

EDGE DETECTOR

BTCL

T3ST

CAP2

T2SL1

INITIAL VALUE: 00

ADDRESS: 0E3

TM2

T2SL0

T2CN

T2ST

T3SL1 T3SL0

X means don't care

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

11.3 8-bit Capture Mode

The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP2 of timer mode register TM2
for Timer 2) as shown in Figure 21. In this mode, Timer 1
still operates as an 8-bit timer/counter.

As mentioned above, not only Timer 0 but Timer 2 can also
be used as a capture mode.

In 8-bit capture mode, Timer 1 and Timer 3 are can not be
used as a capture mode.

The Timer/Counter register is incremented in response in-
ternal or external input. This counting function is same
with normal timer mode, but Timer interrupt is not gener-
ated. Timer/Counter still does the above, but with the add-
ed feature that a edge transition at external input INTn pin

causes the current value in the Timer counter register
(T0,T2), to be captured into registers CDRn (CDR0,
CDR2), respectively. After captured, Timer counter regis-
ter is cleared and restarts by hardware.

Note: The CDRn and TDRn are in same address.In the
capture mode, reading operation is read the CDRn, not
TDRn because path is opened to the CDRn.

It has three transition modes: "falling edge", "rising edge",
"both edge" which are selected by interrupt edge selection
register IEDS. Refer to "16.4 External Interrupt" on page
64. In addition, the transition at INTn pin generate an inter-
rupt.

Figure 11-9 8-bit Capture Mode

EC0 PIN

XIN PIN

MUX

Prescaler

INT0IF

0: Stop
1: Clear and start

T0ST

T0SL[1:0]

"00"

"01"

"10"

"11"

INT0
INTERRUPT

T0CN

CDR0 (8-bit)

T0 (8-bit)

TIMER 0

BTCL

T1ST

CAP0

T0SL1

INITIAL VALUE: 00

ADDRESS: 0E2

TM0

T0SL0

T0CN

T0ST

T1SL1 T1SL0

X means don't care

01 or 10 or 11

"01"

"10"

"11"

INT0 PIN

Capture

To TIMER1

IEDS[1:0]

Edge Detector

This figure is a example of using the Timer0.
In the Timer2, operation is same like Timer0, each registers and
flags may be changed with for Timer2.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

11.4 16-bit Capture Mode

16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits.

Figure 11-10 16-bit Capture Mode

EC0 PIN

XIN PIN

MUX

Prescaler

INT0IF

0: Stop
1: Clear and start

T0ST

T0SL[1:0]

"00"

"01"

"10"

"11"

INT0
INTERRUPT

T0CN

BTCL

T1ST

CAP0

T0SL1

INITIAL VALUE: 00

ADDRESS: 0E2

TM0

T0SL0

T0CN

T0ST

T1SL1 T1SL0

X means don't care

"01"

"10"

"11"

INT0 PIN

Capture

IEDS[1:0]

Edge Detector

This figure is a example of using the Timer0, 1.
In the Timer2, 3, operation is same like Timer0,1, each registers and
flags may be changed with for Timer2,3.

CDR1 + CDR0

Higher byte Lower byte

(16-bit)

CAPTURE DATA

T1 + T0
(16-bit)

TIMER 0 + TIMER 1

TIMER 0 (16-bit)

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Example 1:

Timer0 = 16-bit timer mode, 0.5s at 8MHz
Timer2 = 2ms 8-bit timer mode at 8MHz
Timer3 = 250us 8-bit timer mode at 8MHz

LDM

TDR0,#23H

LDM

TDR1,#0F4H

LDM

TM0,#0FH

LDM

TDR2,#249

LDM

TDR3,#124

LDM

TM2,#0110_1111B

SET1

T0E

SET1

T2E

SET1

T3E

EI
:
:

Example 2:

Timer0 = 8-bit timer mode, 2ms interval at 8MHz
Timer2 = 16-bit event counter mode

LDM

TDR0,#249

LDM

TM0,#0111_1111B

LDM

TDR2,#3FH

LDM

TDR3,#2AH

LDM

TM2,#0100_1100B

SET1

T0E

SET1

T2E

EI
:
:

Example 3:

Timer0 = 8-bit timer mode, 2ms interval at 8MHz
Timer2 = 8-bit capture mode

LDM

TDR0,#250

LDM

TM0,#0111_1111B

SET1

T0E

LDM

TDR2,#40H

LDM

TDR3,#2AH

LDM

TM2,#1111_1111B

SET1

T2E

LDM

IEDS,#XX11_XXXXB

LDM

PMR4,#XXXX_X1XXB

SET1

INT2E

EI
:
:

X: don't care.

Example 4:

Timer0 = 8-bit timer mode, 2ms interval at 8MHz
Timer2 = 16-bit capture mode

LDM

TDR0,#249

LDM

TM0,#0111_1111B

SET1

T0E

LDM

TDR2,#40H

LDM

TDR3,#2AH

LDM

TM2,#1100_1111B

SET1

T2E

LDM

IEDS,#XX11_XXXXB

LDM

PMR4,#XXXX_X1XXB

SET1

INT2E

EI
:
:

X: don't care.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

12. ANALOG DIGITAL CONVERTER

The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has eight analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which gen-
erates the result via successive approximation. The analog
supply voltage is connected to AV

of ladder resistance

of A/D module.

The A/D module has two registers which are the control
register ADCM and A/D result register ADR. The register
ADCM, shown in Figure 12-2, controls the operation of
the A/D converter module. The port pins can be configured
as analog inputs or digital I/O. To use analog inputs, I/O is
selected input mode by R6DD direction register.

R60 ~ R63 are NOT served on GMS825xx.

How to Use A/D Converter

The processing of conversion is start when the start bit
ADST is set to "1". After one cycle, it is cleared by hard-
ware. The register ADR contains the results of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADR, the A/D conversion status bit
ADSF is set to "1", and the A/D interrupt flag AIF is set.
The block diagram of the A/D module is shown in Figure
12-1. The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conver-
sion is in process. The conversion time takes maximum 20
uS (at f

XIN

=8 MHz).

Figure 12-1 A/D Block Diagram

Note: On the MDS(Choice-Dr,Jr), when the MCU is RE-
SET, R60 port is selected as an analog input by ADCM reg-
ister. So it can not be used digital input port. To use this port
as a digital I/O port, change to except "0" the value of AD-
CM. Finally all eight ports can not be used as digital I/O port
simultaneously on the MDS. At least one port must be in an-
alog port.
But on the OTP and Main chip, R6 port, all eight pins can
be used as digital I/O port at the same time.

R60/AN0

R61/AN1

R62/AN2

R63/AN3

R64/AN4

R65/AN5

R66/AN6

R67/AN7

S/H

Sample & Hold

"0"

"1"

ADEN

8-bit DAC

LADDER RESISTOR

ADIF

A/D
INTERRUPT

SUCCESSIVE

APPROXIMATION

CIRCUIT

ADR

A/D result register

ADDRESS: E9

RESET VALUE: Undefined

000

001

010

011

100

101

110

111

ADS[2:0]

These ports are NOT served on the GMS825xx.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Figure 12-2 A/D Converter Control Register

BTCL

ADST

A/D status bit

Analog input channel select

INITIAL VALUE: --00 0001

ADDRESS: 0E8

ADCM

ADSF

A/D converter Enable bit

0: A/D converter module turn off and

current is not flow.

1: Enable A/D converter

R/W

000: Channel 0 (AN0)

001: Channel 1 (AN1)

010: Channel 2 (AN2)

011: Channel 3 (AN3)

100: Channel 4 (AN4)
101: Channel 5 (AN5)
110: Channel 6 (AN6)
111: Channel 7 (AN7)

0: A/D conversion is in progress
1: A/D conversion is completed

A/D start bit
Setting this bit starts an A/D conversion.
After one cycle, bit is cleared to "0" by hardware.

ADS1 ADS0

ADEN ADS2

INITIAL VALUE: Undefined

ADDRESS: 0E9

ADR

A/D Conversion Data

BTCL

These are NOT served on the GMS825xx.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

13. SERIAL COMMUNICATION
- This function is NOT served on the GMS825xx.

The serial iterface is used to transmit/receive 8-bit data se-
rially. This consists of serial I/O data register, serial I/O
mode register, clock selection circuit octal counter and
control circuit as illustrated in Figure 13-1.Pin R50/SIN,
R51/SOUT, R52/SCLK and R53/SRDY pins are con-

trolled by the Serial Mode Register. The contents of the Se-
rial I/O data register can be written into or read out by
software. The data in the Serial Data Register can be shift-
ed synchronously with the transfer clock signal.

Figure 13-1 SCI Block Diagram

SRDY PIN

XIN PIN

Prescaler

MUX

SCK[1:0]

SCLK PIN

Start

CONTROL CIRCUIT

SIN PIN

Shift

Input shift register

SIOR

Clock

Octal

Serial communication
Interrupt

SIOIF

SOUT PIN

SIOST

SIOSF

Complete

Counter

SCK[1:0]

"11"

overflow

not "11"

SRDY In

Complete

SRDY Out

[0EB

]

Internal bus line

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Serial I/O Mode Register(SIOM) controls serial I/O func-
tion. According to SCK1 and SCK0, the internal clock or
external clock can be selected.

Serial I/O Data Register(SIOR) is an 8-bit shift register.
First LSB is send or is received.

Figure 13-2 SCI Control Register

BTCL

SRDY

SIOST

Serial transmission status bit

Serial transmission Clock selection

INITIAL VALUE: -000 0001

ADDRESS: 0EA

SIOM

SIOSF

R53/SRDY Selection

0: R53
1: SRDY

R/W

00: f

XIN

01: f

XIN

10: f

XIN

11: External Clock

0: Serial transmission is in progress
1: Serial transmission is completed

Serial transmission start bit
Setting this bit starts an Serial transmission.
After one cycle, bit is cleared to "0" by hardware.

SCK1 SCK0

SM1

SM0

R/W

Serial transmission Operation Mode
00: Normal Port(R52,R51,R50)
01: Sending Mode(SCLK,SOUT,R50)
10: Receiving Mode(SCLK,R51,SIN)
11: Sending & Receiving Mode(SCLK,SOUT,SIN)

INITIAL VALUE: Undefined

ADDRESS: 0EB

SIOR

BTCL

R/W R/W R/W R/W

R/W R/W

R/W

Sending Data at Sending Mode
Receiving Data at Receiving Mode

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

13.1 Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 of
SIOM) to "1". After one cycle of SCK, SIOST is cleared
automatically to "0". The serial output data from 8-bit shift
register is output at falling edge of SCLK. And input data

is latched at rising edge of SCLK pin. When transmission
clock is counted 8 times, serial I/O counter is cleared as
`0". Transmission clock is halted in "H" state and serial I/
O interrupt(IFSIO) occurred.

Figure 13-3 Timing Diagram of Serial I/O

13.2 The Serial I/O operation by SRDY pin

Transmission clock = external clock

The SRDY pin becomes "L" by SIOST = "1". This signal
tells to the external system that this device is ready for se-

rial transmission. The external system detects the "L" sig-
nal and starts transmission. The SRDY pin becomes "H" at
the first rising edge of transmission clock.

Transmission clock = internal clock

The I/O of SRDY pin is input mode. When the external
system is ready for serial transmission, The "L" level is in-

putted at this pin. At this time this device starts serial trans-
mission.

D 1

D 0

SIOST FLAG

SOUT PIN

Input Clock

SCLK PIN

D 1

D 0

SIN PIN

SIOIF

Output

Latch

INTERRUPT SIGNAL

SRDY(Output)

SIOST

SRDY(Input)

SIOST

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

13.3 The method of Serial I/O

1. Select transmission/receiving mode.

2. In case of sending mode, write data to be send to SIOR.

3. Set SIOST to "1" to start serial transmission.

4. The SIO interrupt is generated at the completion of SIO

and SIOSF is set to "1". In SIO interrupt service routine,
correct transmission should be tested.

5. In case of receiving mode, the received data is acquired

by reading the SIOR.

Note: When external clock is used, the frequency should
be less than 1MHz and recommended duty is 50%. If both
transmission mode is selected and transmission is per-
formed simultaneously it would be made error.

13.4 The Method to Test Correct Transmission

Figure 13-4 Serial Method to Test Transmission

Serial I/O Interrupt
Service Routine

SE = 0

Write SIOM

Normal Operation

Overrun Error

Abnormal

SIOSF

- SE: Interrupt Enable Register Low IENL(Bit3)

- SR: Interrupt Request Flag Register Low IRQL(Bit3)

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

14. PWM OUTPUT
- This function is NOT served on the GMS825xx.

The GMS815xxB have two channels of built-in pulse
width modulation outputs. PWM outputs data are multi-
plex to the R56 and R57 port. Bit 6 and bit 7 of R5DD
should be set to "1" when PWM is used as an output port.

The input clock is selected by PWM Control Register
(PWMCR, address F2

) and the width of pulse is deter-

mined by the PWM Register (PWMR, address F0

and

Figure 14-1 PWM block diagram

The pulse period according to input clock are shown as be-
low.

Bit 2 (EN0) and bit 3 (EN1) of PWMCR determine the op-
eration channel of PWM. When EN0=0 and EN1=0, PWM
does not execute

It is a PWM output controlled by PWMCR, PWMR0 and
PWMR1.

XIN

256

MUX

P0CK[1:0]

PWM0

Comparator

8-bit Counter

XIN

512

XIN

1024

XIN

2048

PWMR0

Overflow

XIN

2048

MUX

P1CK[1:0]

Comparator

8-bit Counter

XIN

1024

XIN

512

XIN

256

PWMR1

Overflow

POL0

PWM1

POL1

EN0

EN1

F/F

[0F0

]

[0F1

]

Input clock

Period of PWM

XIN

256

XIN

512

XIN

1024

XIN

2048

8.19 ms

16.38 ms
32.77 ms
65.54 ms

Duty ratio

PWMR

256

----------------------------

100%

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Figure 14-2 PWM Duty Register

Figure 14-3 PWM Control Register

Example:

PWM0: Period = 16.384ms, Duty = 20%
PWM1: Period = 8.192ms, Duty = 70%

LDM

PWMCR,#0100_1111B

LDM

PWMR0,#0B3H

LDM

PWMR1,#33H

PWMR0

ADDRESS: 0F0

RESET VALUE: Undefined

Duty data

PWMR1

ADDRESS: 0F1

RESET VALUE: Undefined

Duty data

BTCL

P1CK0

P1CK1

POL1

PWM0 output polarity

PWM enable flag

INITIAL VALUE: 0000 0000

ADDRESS: 0F2

PWMCR

POL0

PWM0 clock selection

00: f

XIN

256

00: Disable(R56,R57)
01: PWM0(PWM0,R57)
10: PWM1(R56,PWM1)
11: Both (PWM0, PWM1)

0: Active low
1: Active high

EN1

EN0

P0CK1 P0CK0

PWM1 output polarity
0: Active low
1: Active high

01: f

XIN

512

10: f

XIN

1024

11: f

XIN

2048

PWM1 clock selection

00: f

XIN

256

01: f

XIN

512

10: f

XIN

1024

11: f

XIN

2048

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

15. BUZZER FUNCTION

The buzzer driver block consists of 6-bit binary counter,
buzzer register, and clock source selector. It generates
square-wave which has very wide range frequency (500Hz
~ 250kHz at f

XIN

= 8MHz) by user software.

A 50% duty pulse can be output to R55/BUZ pin to use for
piezo-electric buzzer drive

. Pin R55 is assigned for output port

of Buzzer driver by setting the bit 5 of PMR5 (address D1

) to

"1".

At this time, the pin R55 must be defined as output

mode (the bit 5 of R5DD=1).

Example: 2.4kHz output at 8MHz.

LDM

R5DD,#XX1X_XXXXB

LDM

BUR,#9AH

LDM

PMR5,#XX1X_XXXXB

X means don't care

The bit 0 to 5 of BUR determines output frequency for
buzzer driving.

Equation of frequency calculation is shown below.

BUZ

: Buzzer frequency

XIN

: Oscillator frequency

Divide Ratio: Prescaler divide ratio by BUCK[1:0]

BUR: Lower 6-bit value of BUR. Buzzer period value.

The frequency of output signal is controlled by the buzzer
control register BUR.The bit 0 to bit 5 of BUR determine
output frequency for buzzer driving.

Figure 15-1 Block Diagram of Buzzer Driver

Figure 15-2 PMR5 and Buzzer Register

BUZ

XIN

DivideRatio

BUR

-------------------------------------------------------------

Prescaler

128

BUR

R55/BUZ PIN

PMR5

Internal bus line

R55 port data

XIN PIN

6-bit binary

[0EC

]

[0D1

]

F/F

Comparator

Compare data

6-BIT COUNTER

MUX

Port selection

BUR[5:0]

BUR

ADDRESS: 0EC

RESET VALUE: Undefined

Source clock select

00:

01:

10:

11:

128

Buzzer Period Data

R55/BUZ Selection

PMR5

ADDRESS: 0D1

RESET VALUE: --00 ----

0: R55 port (Turn off buzzer)
1: BUZ port (Turn on buzzer)

R54/WDTO Selection
0: R54
1: WDTO (Output)

BUCK1 BUCK0

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Note: BUR is undefined after reset, so it must be initialized
to between 1

and 3F

by software.

Note that BUR is a write-only register.

The 6-bit counter is cleared and starts the counting by writ-
ing signal at BUR register. It is incremental from 00

until

it matches 6-bit BUR value.

When main-frequency is 8MHz, buzzer frequency is
shown as below table.

[kHz]

BUR
[5:0]

BUR[7:6]

BUR

[5:0]

BUR[7:6]

00
01
02
03
04
05
06
07

250.000
125.000

83.333
62.500
50.000
41.667
35.714

125.000

62.500
41.667
31.250
25.000
20.833
17.857

62.500
31.250
20.833
15.625
12.500
10.417

8.929

31.250
15.625
10.417

7.813
6.250
5.208
4.464

20
21
22
23
24
25
26
27

7.813
7.576
7.353
7.143
6.944
6.757
6.579
6.410

3.906
3.788
3.676
3.571
3.472
3.378
3.289
3.205

1.953
1.894
1.838
1.786
1.736
1.689
1.645
1.603

0.977
0.947
0.919
0.893
0.868
0.845
0.822
0.801

08
09

0A
0B
0C
0D
0E

31.250
27.778
25.000
22.727
20.833
19.231
17.857
16.667

15.625
13.889
12.500
11.364
10.417

9.615
8.929
8.333

7.813
6.944
6.250
5.682
5.208
4.808
4.464
4.167

3.906
3.472
3.125
2.841
2.604
2.404
2.232
2.083

28
29

2A
2B

2C
2D

2E
2F

6.250
6.098
5.952
5.814
5.682
5.556
5.435
5.319

3.125
3.049
2.976
2.907
2.841
2.778
2.717
2.660

1.563
1.524
1.488
1.453
1.420
1.389
1.359
1.330

0.781
0.762
0.744
0.727
0.710
0.694
0.679
0.665

10
11
12
13
14
15
16
17

15.625
14.706
13.889
13.158
12.500
11.905
11.364
10.870

7.813
7.353
6.944
6.579
6.250
5.952
5.682
5.435

3.906
3.676
3.472
3.289
3.125
2.976
2.841
2.717

1.953
1.838
1.736
1.645
1.563
1.488
1.420
1.359

30
31
32
33
34
35
36
37

5.208
5.102
5.000
4.902
4.808
4.717
4.630
4.545

2.604
2.551
2.500
2.451
2.404
2.358
2.315
2.273

1.302
1.276
1.250
1.225
1.202
1.179
1.157
1.136

0.651
0.638
0.625
0.613
0.601
0.590
0.579
0.568

18
19

1A
1B
1C
1D
1E

10.417
10.000

9.615
9.259
8.929
8.621
8.333
8.065

5.208
5.000
4.808
4.630
4.464
4.310
4.167
4.032

2.604
2.500
2.404
2.315
2.232
2.155
2.083
2.016

1.302
1.250
1.202
1.157
1.116
1.078
1.042
1.008

38
39

3A
3B

3C
3D

3E
3F

4.464
4.386
4.310
4.237
4.167
4.098
4.032
3.968

2.232
2.193
2.155
2.119
2.083
2.049
2.016
1.984

1.116
1.096
1.078
1.059
1.042
1.025
1.008
0.992

0.558
0.548
0.539
0.530
0.521
0.512
0.504
0.496

Table 15-1 Buzzer Frequency

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

16. INTERRUPTS

The GMS815xxB and GMS825xx interrupt circuits con-
sist of Interrupt enable register (IENH, IENL), Interrupt re-
quest flags of IRQH, IRQL, Priority circuit, and Master
enable flag ("I" flag of PSW). Thirteen interrupt(twelve
interrupt in case of GMS825xx) sources are provided. The
configuration of interrupt circuit is shown in Figure 16-2.

The External Interrupts INT0 ~ INT3 each can be transi-
tion-activated (1-to-0 or 0-to-1 transition) by selection
IEDS.
The flags that actually generate these interrupts are bit
INT0F, INT1F, INT2F and INT3F in register IRQH. When
an external interrupt is generated, the flag that generated it
is cleared by the hardware when the service routine is vec-
tored to only if the interrupt was transition-activated.

The Timer 0 ~ Timer 3 Interrupts are generated by TxIF
which is set by a match in their respective timer/counter
register. The Basic Interval Timer Interrupt is generated by
BITIF which is set by an overflow in the timer register.

The AD converter Interrupt is generated by ADIF which is
set by finishing the analog to digital conversion.
The Watchdog timer Interrupt is generated by WDTIF
which set by a match in Watchdog timer register.
The Basic Interval Timer Interrupt is generated by BITIF
which are set by a overflow in the timer counter register.

The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW on page 22), the interrupt enable
register (IENH, IENL), and the interrupt request flags (in

IRQH and IRQL) except Power-on reset and software
BRK interrupt. Below table shows the Interrupt priority.

This interrupt is NOT served on GMS825xx.

Vector addresses are shown in Figure 8-6 on page 24. In-
terrupt enable registers are shown in Figure 16-3. These
registers are composed of interrupt enable flags of each in-
terrupt source and these flags determines whether an inter-
rupt will be accepted or not. When enable flag is "0", a
corresponding interrupt source is prohibited. Note that
PSW contains also a master enable bit, I-flag, which dis-
ables all interrupts at once.

Figure 16-1 Interrupt Request Flag

Reset/Interrupt

Symbol

Priority

Hardware Reset
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
ADC Interrupt
Basic Interval Timer
Watchdog Timer

Serial Communication

RESET

INT0
INT1
INT2
INT3

Timer 0
Timer 1
Timer 2
Timer 3

ADC

BIT

WDT

SCI

1
2
3
4
5
6
7
8
9

10
11
12
13

INT3IF

R/W

INT0IF

Timer/Counter 3 interrupt request flag

INITIAL VALUE: 0000 0000

ADDRESS: 0F7

IRQH

INT1IF

MSB

LSB

T2IF

T3IF

T0IF

T1IF

INT2IF

R/W

Timer/Counter 2 interrupt request flag

Timer/Counter 1 interrupt request flag

External interrupt 3 request flag

SIOIF

R/W

ADIF

Serial Communication interrupt request flag

INITIAL VALUE: 0000 ----

ADDRESS: 0F5

IRQL

WDTIF

MSB

LSB

BITIF

R/W

Timer/Counter 0 interrupt request flag

R/W

Basic Interval Timer interrupt request flag

Watchdog timer interrupt request flag

A/D Converter interrupt request flag

External interrupt 3 request flag

This is NOT served on GMS825xx.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Figure 16-2 Block Diagram of Interrupt

Figure 16-3 Interrupt Enable Flag

Timer 0

INT2

INT1

INT0

INT0IF

IENH

Interrupt Enable

IRQH

IRQL

Interrupt

Vector

Address

Generator

Internal bus line

Release STOP

To CPU

Interrupt Master
Enable Flag

I-flag

IENL

Priority Control

I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.

[0F6

]

[0F4

]

[0F7

]

[0F5

]

INT1IF

INT2IF

INT3IF

T0IF

T3IF

T2IF

INT3

Timer 1

Timer 3

Timer 2

T1IF

A/D Converter

ADIF

SIOIF

BITIF

Watchdog Timer

Serial

BIT

WDTIF

Communication

This is NOT served on GMS825xx.

INT3E

R/W

INT0E

Timer/Counter 3 interrupt enable flag

INITIAL VALUE: 0000 0000

ADDRESS: 0F6

IENH

INT1E

MSB

LSB

T2E

T3E

T0E

T1E

INT2E

R/W

Timer/Counter 2 interrupt enable flag

Timer/Counter 1 interrupt enable flag

External interrupt 3 enable flag

SIOE

R/W

ADE

Serial Communication interrupt enable flag

INITIAL VALUE: 0000 ----

ADDRESS: 0F4

IENL

WDTE

MSB

LSB

BITE

R/W

Timer/Counter 0 interrupt enable flag

R/W

Basic Interval Timer interrupt enable flag

Watchdog timer interrupt enable flag

A/D Converter interrupt enable flag

External interrupt 2 enable flag

External interrupt 1 enable flag

External interrupt 0 enable flag

0: Disable
1: Enable

VALUE

This is NOT served on GMS825xx.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

16.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an in-
struction. Interrupt acceptance sequence requires 8

XIN

s at f

MAIN

=4.19MHz) after the completion of the current

instruction execution. The interrupt service task is termi-
nated upon execution of an interrupt return instruction
[RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

"0" to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following
interrupts is temporarily disabled.

2. Interrupt request flag for the interrupt source accepted is

cleared to "0".

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is

read from the vector table address and the entry address
is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

Figure 16-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

A interrupt request is not accepted until the I-flag is set to
"1" even if a requested interrupt has higher priority than
that of the current interrupt being serviced.

When nested interrupt service is required, the I-flag should
be set to "1" by "EI" instruction in the interrupt service
program. In this case, acceptable interrupt sources are se-
lectively enabled by the individual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. These registers are saved by the software
if necessary. Also, when multiple interrupt services are
nested, it is necessary to avoid using the same data memory

V.L.

System clock

Address Bus

SP-1

SP-2

V.H.

New PC

V.L.

Data Bus

Not used

PCH

PCL

PSW

ADL

OP code

ADH

Instruction Fetch

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.

Basic Interval Timer

012

0E3

0FFE6

0FFE7

0E312

0E313

Entry Address

Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.

Vector Table Address

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

area for saving registers.

The following method is used to save/restore the general-
purpose registers.

Example: Register save using push and pop instructions

General-purpose register save/restore using push and pop
instructions;

16.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.

Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin-
guish BRK from TCALL 0.

Each processing step is determined by B-flag as shown in
Figure 16-5.

Figure 16-5 Execution of BRK/TCALL0

INTxx:

PUSH

;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.

interrupt processing

POP

RETI

;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN

main task

interrupt
service task

saving
registers

restoring
registers

acceptance of

interrupt

interrupt return

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

TCALL0

ROUTINE

RET

BRK or

TCALL0

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

16.3 Multi Interrupt

If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.

Figure 16-6 Execution of Multi Interrupt

However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.

Example: During Timer1 interrupt is in progress, INT0 in-
terrupt serviced without any suspend.

TIMER1:

PUSH

LDM

IENH,#80H

;

Enable INT0 only

LDM

IENL,#0

;

Disable other

;

Enable Interrupt

:
:
:

:
:
:
LDM

IENH,#0FFH

;

Enable all interrupts

LDM

IENL,#0F0H

POP

RETI

16.4 External Interrupt

The external interrupt on INT0, INT1, INT2 and INT3 pins
are edge triggered depending on the edge selection register
IEDS (address 0F8

) as shown in Figure 16-7.

The edge detection of external interrupt has three transition

enable INT0

TIMER 1
service

INT0
service

Main Program
service

Occur
TIMER1 interrupt

Occur
INT0

disable other

enable INT0
enable other

In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

activated mode: rising edge, falling edge, and both edge.

Figure 16-7 External Interrupt Block Diagram

INT0 ~ INT3 are multiplexed with general I/O ports
(R40~R43). To use as an external interrupt pin, the bit of
R4 port mode register PMR4 should be set to "1" corre-

spondingly.

Example: To use as an INT0 and INT2

:
:

;

**** Set port as an input port R40,R42

LDM

R4DD,#1111_1010B

;

**** Set port as an external interrupt port

LDM

PMR4,#05H

;

**** Set Falling-edge Detection

LDM

IEDS,#0001_0001B

:
:
:

Response Time

The INT0 ~ INT3 edge are latched into INT1IF ~ INT3IF
at every machine cycle. The values are not actually polled
by the circuitry until the next machine cycle. If a request is
active and conditions are right for it to be acknowledged, a
hardware subroutine call to the requested service routine
will be the next instruction to be executed. The DIV itself
takes twelve cycles. Thus, a minimum of twelve complete
machine cycles elapse between activation of an external
interrupt request and the beginning of execution of the first
instruction of the service routine.

Figure 16-8shows interrupt response timings.

Figure 16-8 Interrupt Response Timing Diagram

INT0IF

INT0 pin

INT0 INTERRUPT

INT1IF

INT1 pin

INT1 INTERRUPT

INT2IF

INT2 pin

INT2 INTERRUPT

IEDS

[0F8H]

INT3IF

INT3 pin

INT3 INTERRUPT

Edge selection
Register

Interrupt
goes
active

Interrupt
latched

Interrupt
processing

Interrupt
routine

8 f

XIN

max. 12 f

XIN

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

17. WATCHDOG TIMER

The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re-
sumes the CPU to the normal state.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.

When the watchdog timer is not being used for malfunc-
tion detection, it can be used as a timer to generate an in-
terrupt at fixed intervals.

Figure 17-1 Block Diagram of Watchdog Timer

Watchdog Timer Control

Figure 17-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.

The CPU malfunction is detected during setting of the de-
tection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.

If the malfunction occurs for any cause, the watchdog tim-

er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated.

The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it au-
tomatically restarts (continues counting).

Figure 17-2 WDTR: Watchdog Timer Data Register

to reset CPU

BASIC INTERVAL TIMER

Count source

enable

Watchdog

6-bit compare data

comparator

Watchdog Timer interrupt

clear

WDTIF

Counter (8-bit)

WDTCL

"0"

"1"

WDTON in CKCTLR [0D3

]

OVERFLOW

Watchdog Timer
Register

WDTR

Internal bus line

[0E0

]

W D TC L

Clear count flag
0: Free-run count

INITIAL VALUE: -011_1111

ADDRESS: 0E0

WDTR

1: When the WDTCL is set to "1", binary counter

is cleared to "0". And the WDTCL becomes "0" automatically
after one machine cycle. Counter count up again.

6-bit compare data

NOTE:
The WDTON bit is in register CKCTLR.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz

Enable and Disable Watchdog

Watchdog timer is enabled by setting WDTON (bit 5 in
CKCTLR) to "1". WDTON is initialized to "0" during re-
set and it should be set to "1" to operate after reset is re-
leased.

Example: Enables watchdog timer for Reset

:
LDM

CKCTLR,#xx1x_xxxxB;

WDTON

:
:

The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKCTLR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is re-
leased.

Watchdog Timer Interrupt

The watchdog timer can be also used as a simple 6-bit tim-
er by clearing bit5 of CKCTLR to "0". The interval of
watchdog timer interrupt is decided by Basic Interval Tim-
er. Interval equation is shown as below.

The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.

Example: 6-bit timer interrupt set up.

LDM

CKCTLR,#xx0xxxxxB;

WDTON

LDM

WDTR,#7FH

;

WDTCL

Figure 17-3 Watchdog timer Timing

If the watchdog timer output becomes active, a reset is gen-
erated, which drives the RESET pin low to reset the inter-
nal hardware.

The main clock oscillator also turns on when a watchdog
timer reset is generated in sub clock mode.

LDM

CKCTLR,#3FH

;

Select 1/2048 clock source

WDTON

1, Clear Counter

LDM

WDTR,#04FH

LDM

WDTR,#04FH

;

Clear counter

:
:
:
:
LDM

WDTR,#04FH

;

Clear counter

:
:
:
:
LDM

WDTR,#04FH

;

Clear counter

Within WDT
detection time

WDTR

Interval of BIT

Source clock

Binary-counter

WDTR

WDTIF interrupt

WDTR

"0100_0011

Match
Detect

Counter
Clear

BIT overflow

WDT reset

reset

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

18. POWER DOWN OPERATION

GMS815xxB has a power-down mode. In power-down
mode, power consumption is reduced considerably that in
battery operation. Battery life can be extended a lot.

STOP Mode is entered by STOP instruction.

18.1 STOP Mode

For applications where power consumption is a critical
factor, device provides reduced power of STOP.

Start The Stop Operation

An instruction that STOP causes to be the last instruction
is executed before going into the STOP mode. In the Stop
mode, the on-chip main-frequency oscillator is stopped.
With the clock frozen, all functions are stopped, but the on-
chip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.

Note: Since the X

pin is connected internally to GND to

avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.

In the Stop mode of operation, V

can be reduced to min-

imize power consumption. Be careful, however, that V

is not reduced before the Stop mode is invoked, and that
V

is restored to its normal operating level before the

Stop mode is terminated.

The reset should not be activated before V

is restored to

its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP in-
struction should be written as shown in example below.

Example:

LDM

CKCTLR,#0000_1110B

STOP
NOP
NOP
:

The Interval Timer Register CKCTLR should be initial-
ized (0F

or 0E

) by software in order that oscillation sta-

bilization time should be longer than 20ms before STOP
mode.

Figure 18-1 STOP Mode Release Timing by External Interrupt

Peripheral

STOP Mode

CPU

All CPU operations are disabled

RAM

Retain

Low

OUT

High

Oscillation

Stop

I/O ports

Retain

Control Registers

Retain

Release method

by RESET, by External interrupt

Before executing Stop instruction, Basic Interval Timer must be set

Oscillator

pin)

BIT Counter

n+1

n+2

n+3

Normal Operation

Stop Operation

Normal Operation

20ms

External Interrupt

Internal Clock

Clear

STOP Instruction
Executed

properly by software to get stabilization time which is longer than 20ms.

by software

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Release the STOP mode

The exit from STOP mode is using hardware reset or exter-
nal interrupt.

To release STOP mode, corresponding interrupt should be
enabled before STOP mode.
Reset redefines all the control registers but does not change

the on-chip RAM. External interrupts allow both on-chip
RAM and Control registers to retain their values.

Start-up is performed to acquire the time for stabilizing os-
cillation. During the start-up, the internal operations are all
stopped.

18.2 Minimizing Current Consumption

The Stop mode is designed to reduce power consumption.
To minimize current drawn during Stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.

Note: In the STOP operation, the power dissipation asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
of the STOP feature. This point should be little current flows
when the input level is stable at the power voltage level
(V

); however, when the input level becomes higher

than the power voltage level (by approximately 0.3V), a cur-
rent begins to flow. Therefore, if cutting off the output tran-
sistor at an I/O port puts the pin signal into the high-
impedance state, a current flow across the ports input tran-
sistor, requiring it to fix the level by pull-up or other means.

It should be set properly in order that current flow through
port doesn't exist.

First conseider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn't
flow.

But input voltage level should be V

or V

. Be careful

that if unspecified voltage, i.e. if unfirmed voltage level
(not V

or V

) is applied to input pin, there can be little

current (max. 1mA at around 2V) flow.

If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up re-
sistor then it is set to output mode, i.e. to High, and if there

Event

MCU Status before event

Chip function after event

Oscillator Circuit

RESET

Don't care

Vector

STOP instruction

Normal operation

N +1

off

External Interrupt

Normal operation

Vector

External Interrupt Wake up

STOP, I flag = 1
STOP, I flag = 0

Vector

N + 1

on
on

Table 18-1 Wake-up and Reset Function Table

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

is external pull-down register, it is set to low.

Figure 18-2 Application Example of Unused Input Port

Figure 18-3 Application Example of Unused Output Port

INPUT PIN

GND

Weak pull-up current flows

internal
pull-up

INPUT PIN

Very weak current flows

OPEN

i=0

GND

When port is configure as an input, input level should
be closed to 0V or 5V to avoid power consumption.

OUTPUT PIN

GND

In the left case, much current flows from port to GND.

OFF

OUTPUT PIN

GND

In the left case, Tr. base current flows from port to GND.

i=0

OFF

OPEN

GND

OFF

To avoid power consumption, there should be low output

OFF

to the port.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

19. OSCILLATOR CIRCUIT

The GMS815xxB has two oscillation circuits internally.
X

and X

OUT

are input and output for frequency, respec-

tively, inverting amplifier which can be configured for be-
ing used as an on-chip oscillator, as shown in Figure 19-1.

Figure 19-1 Oscillation Circuit

Oscillation circuit is designed to be used either with a ce-
ramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components.

In addition, see Figure 19-2 for the layout of the crystal.

Note: Minimize the wiring length. Do not allow the wiring to
intersect with other signal conductors. Do not allow the wir-
ing to come near changing high current. Set the potential of
the grounding position of the oscillator capacitor to that of
V

. Do not ground it to any ground pattern where high cur-

rent is present. Do not fetch signals from the oscillator.

Figure 19-2 Layout of Oscillator PCB circuit

OUT

Recommend

C1,C2 = 30pF±10pF

OUT

External Clock

Open

External Oscillator

Crystal or Ceramic Oscillator

8MHz

Crystal Oscillator

OUT

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

20. RESET

The GMS815xxB have two types of reset generation pro-
cedures; one is an external reset input, the other is a watch-

dog timer reset. Table 20-1 shows on-chip hardware ini-
tialization by reset action.

Table 20-1 Initializing Internal Status by Reset Action

20.1 External Reset Input

The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, it is applied,
and the internal state is initialized. After reset, 64ms (at 4
MHz) add with 7 oscillator periods are required to start ex-
ecution as shown in Figure 20-2.

Internal RAM is not affected by reset. When V

is turned

on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.

When the RESET pin input goes to high, the reset opera-
tion is released and the program execution starts at the vec-
tor address stored at addresses FFFE

- FFFF

A connection for simple power-on-reset is shown in Figure
20-1.

Figure 20-1 Simple Power-on-Reset Circuit

Figure 20-2 Timing Diagram after RESET

20.2 Watchdog Timer Reset

Refer to "17. WATCHDOG TIMER" on page 67.

On-chip Hardware

Initial Value

On-chip Hardware

Initial Value

Program counter

(PC)

(FFFF

) - (FFFE

)

Watchdog timer

Disable

G-flag

(G)

Control registers

Refer to Table 8-1 on page 28

Peripheral clock

Off

Power fail detector

Disable

7036P

10uF

10k

to the RESET pin

MAIN PROGRAM

Oscillator

pin)

FFFE FFFF

Stabilization Time

= 62.5mS at 4.19MHz

RESET

ADDRESS

DATA

Start

ADL

ADH

BUS

RESET Process Step

x 256

MAIN

1024

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

21. POWER FAIL PROCESSOR

The GMS815xxB and GMS825xx have an on-chip power
fail detection circuitry to immunize against power noise. A
configuration register, PFDR, can enable or disable the
power fail detect circuitry. Whenever V

falls close to or

below power fail voltage for 100ns, the power fail situation
may reset or freeze MCU according to PFR bit of PFDR.
Refer to "7.4 DC Electrical Characteristics" on page 16.

In the in-circuit emulator, power fail function is not imple-
mented and user can not experiment with it. Therefore, af-
ter final development of user program, this function may
be experimented or evaluated.

Note: User can select power fail voltage level according to
PFV bit of PFDR at the OTP(GMS815xxBT/GMS825xxT)
but must select the power fail voltage level to define PFD
option of "Mask Order & Verification Sheet" at the mask
chip(GMS815xxB/GMS825xx).
Because the power fail voltage level of mask chip
(GMS815xxB/GMS825xx) is determined according to mask
option regardless of PFV bit of PFDR

Note: If power fail voltage is selected to 3.0V on 3V oper-
ation, MCU is freezed at all the times.

Table 21-1 Power fail processor

Figure 21-1 Power Fail Voltage Detector Register

Power FailFunction

OTP

MASK

Enable/Disable

by PFD flag

Level Selection

by PFV flag

by mask option

PFS

INITIAL VALUE: ---- 1100

ADDRESS: 0F9

PFDR

R/W

PFD

Operation Mode
0: Normal operation regardless of power fail
1: MCU will be reset by power fail detection

Disable Flag
0: Power fail detection enable
1: Power fail detection disable

Power Fail Status
0: Normal operate
1: Set to "1" if power fail is detected

PFR

PFV

Power Fail Voltage Selection Flag
0: 2.4V
1: 3.0V

R/W

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

22. OTP PROGRAMMING

The GMS81516BT/24BT and GMS82524T are OTP (One
Time Programmable) microcontrollers. Its internal user
memory is constructed with EPROM (Electrically Pro-
grammable Read Only Memory).

The OTP micorcontroller is generally used for chip evalu-
ation, first production, small amount production, fast mass
production, etc.

Blank OTP's internal EPROM is filled by 00

, not FF

Note: In any case, you have to use *.OTP file, not *.HEX
file. After assemble, both OTP and HEX file are generated
by automatically. The HEX file is used during porgram em-
ulation on emulator.

22.1 How to Program

To program the OTP devices, user can use Hynix own pro-
grammer or third party universal programmer shown as
listed below.

Hynix own programmer list

Manufacturer:

Hynix Semiconductor Inc.

Programmer: Choice-Sigma,
Stand-alone

Gang4

Choice-Sigma is a Hynix universal single programmer for
any Hynix OTP devices, and the Stand-alone Gang4 can
program four OTPs at once.

Ask to Hynix sales part which is listed on appendix of this
manual for purchasing or more detail.

Third party programmer list

Manufacturer: Hi-Lo Systems
Programmer: ALL-11
Website : http: //www.hilosystems.com.tw

ALL-07

: Even though Hilo System does not support

ALL07 any longer, User can get the specific program algo-
rithm and socket adapter for ALL-07 from Hynix sales
part. ( File name : AMPU7.EXE )

Programming Procedure

1. Select device GMS81516BT or GMS81524BT or

GMS82524T as you want.

2. Load the *.OTP file to the programmer. The file is com-

posed of Motorola-S1 format.

3. Set the programming address range as below table.

4. Mount the socket adapter on the programmer.

5. Start program/verify.

22.2 Pin Function

(Program Voltage)

is the input for the program voltage for programming

the EPROM.

CE (Chip Enable)
CE is the input for programming and verifying internal
EPROM.

OE (Output Enable)
OE is the input of data output control signal for verify.

A0~A15 (Address Bus)
A0~A15 are address input pins for internal EPROM.

O0~O7 (EPROM Data Bus)
These are data bus for internal EPROM.

GMS81516BT

Address

Set Value

Bufferstart address

4000H

Buffer end address

7FFFH

Device start address

C000H

GMS81524BT, GMS82524T

Address

Set Value

Bufferstart address

2000H

Buffer end address

7FFFH

Device start address

A000H

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Table 22-1 Socket Adapter Pin Assignment for GMS81516BT/24BT

O0
O1
O2
O3
O4
O5
O6
O7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

64SDIP

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

GMS81516BT/24BT

OPEN

GND

32
31
30
29
28
27
26
25
24
23
22
21
20

52
53
54
55
56
57
58
59
60
61
62
63
64

64MQFP

GMS815016BT/24BT

A10
A11
A12
A13

A14
A15

OPEN

GND

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Table 22-3 Socket Adapter Pin Assignment for GMS82524T

A1
A2
A3
A4
A5
A6
A7
O0
O1
O2
O3
O4
O5
O6
O7
A8
A9
A10
A11
A12
A13

42SDIP

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

GMS82524T

(Top View)

GND

N.C.

A15
A14

(Top View)

A9
A10
A11
A12
A13
A14
A15

A6
A5
A4
A3
A2
A1
A0

17
16
15
14
13
12

34
35
36
37
38
39
40
41
42
43
44

GMS82524T

44QFP

N.C.

: No Connection

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

22.3 Programming Specification

DEVICE OPERATION MODE

= 25

C ± 5

DEVICE CHARACTERISTICS

=0V, T

= 25

C ± 5

Mode

A0~A15

O0~O7

Read Mode

5.0V

DOUT

Output Disable Mode

5.0V

Hi-Z

Programming Mode

DIN

Program Verify

DOUT

1. X = Either V

or V

2. See DC Characteristics Table for V

and V

voltage during programming.

Symbol

Item

Min

Typ

Max

Unit

Test condition

Quick Pulse Programming

11.50

11.75

12.0

Quick Pulse Programming

5.75

6.0

6.25

supply current

CE=V

supply current

Input high voltage

0.8V

Input low voltage

0.2V

Output high voltage

-0.1

= -2.5mA

Output low voltage

0.4

= 2.1mA

Input leakage current

1. V

must be applied simultaneously or before V

and removed simultaneously or after V

2. The maximum current value is with outputs O0 to O7 unloaded.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

SWITCHING WAVEFORMS

READING WAVEFORMS

1. The input timing reference level is 1.0V for a V

and 4.0V for a V

at V

=5.0V.

2. To read the output data, transition requires on the OE form the high to the low after address setup time t

WAVEFORM

Must be steady

INPUTS

OUTPUTS

Will be steady

May change

Will be changing

from H to L

May change

Will be changing

from L to H

Do not care any

Changing state

change permitted

unknown

Does not apply

Center line is
high impedance "Off" state

Addresses Valid

Addresses

Valid Output

Output

High-Z

See note (2)

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

AC READING CHARACTERISTICS

=0V, T

= 25

C ± 5

Note: V

must be applied simultaneously or before V

and removed simultaneously or after V

AC PROGRAMMING CHARACTERISTICS

=0V, T

= 25

C ± 5

* AC CONDITION OF TEST
Input Rise and Fall Times (10% to 90%) ........................... 20ns
Input Pulse Levels ............................................................. 0.45V to 4.55V
Input Timing Reference Level............................................ 1.0V to 4.0V
Output Timing Reference Level ......................................... 1.0V to 4.0V

must be applied simultaneously or before V

and removed simultaneously or after V

Symbol

Item

Min

Typ

Max

Unit

Test condition

Address setup time

Quick Pulse Programming

200

supply current

Symbol

Item

Min

Typ

Max

Unit

Test condition*

Address setup time

OES

OE setup time

Data setup time

Address hold time

Data hold time

DFP

Output delay disable time

130

VPS

setup time

VDS

setup time

Program pulse width

100

105

Data output delay time

150

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

A. CONTROL REGISTER LIST

Address

Register Name

Symbol

R/W

Initial Value

Page

7 6 5 4 3 2 1 0

00C0

R0 port data register

R/W

Undefined

00C1

R0 port I/O direction register

R0DD

0 0 0 0 0 0 0 0

00C2

R1 port data register

R/W

Undefined

00C3

R1 port I/O direction register

R1DD

0 0 0 0 0 0 0 0

00C4

R2 port data register

R/W

Undefined

00C5

R2 port I/O direction register

R2DD

0 0 0 0 0 0 0 0

00C6

R3 port data register

R/W

Undefined

00C7

R3 port I/O direction register

R3DD

0 0 0 0 0 0 0 0

00C8

R4 port data register

R/W

Undefined

00C9

R4 port I/O direction register

R4DD

0 0 0 0 0 0 0 0

00CA

R5 port data register

R/W

Undefined

00CB

R5 port I/O direction register

R5DD

0 0 0 0 0 0 0 0

00CC

R6 port data register

R/W

Undefined

00CD

R6 port I/O direction register

R6DD

0 0 0 0 - - - -

00D0

R4 port mode register

PMR4

0 0 0 0 0 0 0 0

34, 66

00D1

R5 port mode register

PMR5

- - 0 0 - - - -

34, 58

00D3

Basic interval timer mode register

BITR

Undefined

Clock control register

CKCTLR

- - 0 1 0 1 1 1

00E0

Watchdog Timer Register

WDTR

- 0 1 1 1 1 1 1

00E2

Timer mode register 0

TM0

R/W

0 0 0 0 0 0 0 0

00E3

Timer mode register 2

TM2

R/W

0 0 0 0 0 0 0 0

00E4

Timer 0 data register

TDR0

Undefined

Timer 0 counter register

Undefined

00E5

Timer 1 data register

TDR1

Undefined

Timer 1 counter register

Undefined

00E6

Timer 2 data register

TDR2

Undefined

Timer 2 counter register

Undefined

00E7

Timer 3 data register

TDR3

Undefined

Timer 3 counter register

Undefined

00E8

A/D converter mode register

ADCM

R/W

- - 0 0 0 0 0 1

00E9

A/D converter data register

ADR

Undefined

00EA

Serial I/O mode register

SIOM

R/W

- 0 0 0 0 0 0 1

00EB

Serial I/O register

SIOR

R/W

Undefined

00EC

Buzzer driver register

BUR

Undefined

00F0

PWM0 duty register

PWMR0

Undefined

00F1

PWM1 duty register

PWMR1

Undefined

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

00F2

PWM control register

PWMCR

0 0 0 0 0 0 0 0

00F4

Interrupt enable register low

IENL

R/W

0 0 0 0 - - - -

00F5

Interrupt request flag register low

IRQL

R/W

0 0 0 0 - - - -

00F6

Interrupt enable register high

IENH

R/W

0 0 0 0 0 0 0 0

00F7

Interrupt request flag register high

IRQH

R/W

0 0 0 0 0 0 0 0

00F8

External interrupt edge selection register

IEDS

0 0 0 0 0 0 0 0

00F9

Power fail detection register

PFDR

R/W

- - - - 1 1 0 0

Address

Register Name

Symbol

R/W

Initial Value

Page

7 6 5 4 3 2 1 0

Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation

Registers are controlled by both bit and byte manipulation instruction.

R/W

instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.

- : this bit location is reserved.

: this bit is NOT served on GMS825xx.

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

iii

B. SOFTWARE EXAMPLE

B.1 7-segment LED display

;*****************************************************************************
; Title: GMS81516BT (GMS800 Series) Demonstration Program *
; Company: Hynix Semiconductor *
; Contents: Decimal Up/Down Counter *
; Programmer: Hynix MCU application team *
;*****************************************************************************
;
;******** DEFINE I/O PORT & FUNCTION REGISTER ADDRESS *********
;
R0 EQU 0C0H ;port R0 register
R0DD EQU 0C1H ;port R0 data I/O direction register
;
R1 EQU 0C2H ;port R1 register
R1DD EQU 0C3H ;port R1 data I/O direction register
;
R2 EQU 0C4H ;port R2 register
R2DD EQU 0C5H ;port R2 data I/O direction register
;
R3 EQU 0C6H ;port R3 register
R3DD EQU 0C7H ;port R3 data I/O direction register
;
R4 EQU 0C8H ;port R4 register
R4DD EQU 0C9H ;port R4 data I/O direction register
;
R5 EQU 0CAH ;port R5 register
R5DD EQU 0CBH ;port R5 data I/O direction register
;
R6 EQU 0CCH ;port R6 register
R6DD EQU 0CDH ;port R6 data I/O direction register
;
PMR4 EQU 0D0H ;port R4 mode register
T3S EQU 7,0D0H ;timer3 selection

GMS81516BT

LED Display

GND

R00
R01
R02
R03
R04
R05
R06

a
b
c
d
e

330

4.7k

R23

R22

R20/INT0

R21/INT1

UP/DOWN S/W

CLEAR S/W

2N2222

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

T1S EQU 6,0D0H ;timer1 selection
EC2S EQU 5,0D0H ;event counter 2 selection
EC0S EQU 4,0D0H ;event counter 0 selection
INT3S EQU 3,0D0H ;external int.3 selection
INT2S EQU 2,0D0H ;external int.2 selection
INT1S EQU 1,0D0H ;external int.1 selection
INT0S EQU 0,0D0H ;external int.0 selection
;
PMR5 EQU 0D1H ;port R5 mode register
BUZS EQU 5,0D1H ;buzzer selection
WDTS EQU 4,0D1H ;watch dog timer selection
;
TMR EQU 0D2H ;test mode register
;
CKCTLR EQU 0D3H ;clock control register
BITR EQU 0D3H ;basic interval timer register
;
;WDTR EQU 0E0H ;watch dog timer register
;
TM0 EQU 0E2H ;timer0 mode register
TM2 EQU 0E3H ;timer2 mode register
;
TDR0 EQU 0E4H ;tomer0 data register
TDR1 EQU 0E5H ;tomer1 data register
TDR2 EQU 0E6H ;tomer2 data register
TDR3 EQU 0E7H ;tomer3 data register
;
ADCM EQU 0E8H ;A/D Converter mode register
ADR EQU 0E9H ;A/D con. register
;
SIOM EQU 0EAH ;serial I/O mode register
;SIOR EQU 0EBH ;serial I/O register
;
BUR EQU 0ECH ;buzzer data register
;
PWMR0 EQU 0F0H ;PWM0 data register
PWMR1 EQU 0F1H ;PWM1 data register
;
PWMCR EQU 0F2H ;PWM control register
;
IMOD EQU 0F3H ;interrupt mode register
IENL EQU 0F4H ;int. enable register low
AE EQU 7,0F4H ;A/D con. int. enable
WDTE EQU 6,0F4H ;W.D.T. int. enable
BITE EQU 5,0F4H ;B.I.T. int. enable
SE EQU 4,0F4H ;serial I/O int. enable
;
IRQL EQU 0F5H ;int. request flag register low
AR EQU 7,0F5H ;A/D con. int. request flag
WDTRF EQU 6,0F5H ;W.D.T. int. request flag
BITRF EQU 5,0F5H ;B.I.T. int. request flag
SR EQU 4,0F5H ;serial I/O int. request flag
;
IENH EQU 0F6H ;int. enable register high
INT0E EQU 7,0F6H ;external int.0 enable
INT1E EQU 6,0F6H ;external int.1 enable
INT2E EQU 5,0F6H ;external int.2 enable
INT3E EQU 4,0F6H ;external int.3 enable
T0E EQU 3,0F6H ;timer0 int. enable
T1E EQU 2,0F6H ;timer1 int. enable
T2E EQU 1,0F6H ;timer2 int. enable
T3E EQU 0,0F6H ;timer3 int. enable
;
IRQH EQU 0F7H ;int. request flag register high
INT0R EQU 7,0F7H ;external int.0 request flag
INT1R EQU 6,0F7H ;external int.1 request flag
INT2R EQU 5,0F7H ;external int.2 request flag
INT3R EQU 4,0F7H ;external int.3 request flag
T0R EQU 3,0F7H ;timer0 int. request flag
T1R EQU 2,0F7H ;timer1 int. request flag
T2R EQU 1,0F7H ;timer2 int. request flag
T3R EQU 0,0F7H ;timer3 int. request flag
;
IEDS EQU 0F8H ;external int. edge selection
;
;*********** MACRO DEFINITION ************
;
REG_SAVE MACRO ;Save Registers to Stacks
PUSH A
PUSH X

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

PUSH Y
ENDM
;
REG_RESTORE MACRO ;Restore Register from Stacks
POP Y
POP X
POP A
ENDM

;
;*********** CONSTANT DEFINITION ***********
;
SEG_PORT EQU R0 ;7-Segment Output Port
STROBE_PORT EQU R2 ;Strobe Signal Port
;
;**************************************************************************
; RAM ALLOCATION *
;**************************************************************************

DIGIT10 DS 1 ;DIG10 Display Data
DIGIT1 DS 1 ;Seg1 Display Data
STROBE DS 1 ;Strobe Signal Data
TMR_500mS DS 1 ;500ms Time Counter
FLAGS DS 1 ;Function Flags
UP_F EQU 0,FLAGS ;1=Down,0=Up
F_500ms EQU 1,FLAGS ;
;
;**************************************************************************
; INTERRUPT VECTOR TABLE *
;**************************************************************************
;
ORG0FFE4H
DW NOT_USED ; Serial I/O
DW NOT_USED ; Basic Interval Timer
DW NOT_USED ; Watch Dog Timer
DW NOT_USED ; A/D CON.
DW NOT_USED ; Timer-3
DW NOT_USED ; Timer-2
DW NOT_USED ; Timer-1
DW TMR0_INT ; Timer-0
DW NOT_USED ; Int.3
DW NOT_USED ; Int.2
DW INT_1 ; Int.1
DW INT_0 ; Int.0
DW NOT_USED ;
DW RESET ; Reset
;
;**************************************************************************
; MAIN PROGRAM *
;**************************************************************************
;
ORG 0C000H ;Program Start Address
;
RESET: DI ;Disable All Interrupts
LDX #0
RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH)
STA {X}+ ;M(X) <- A, then X <- X+1
CMPX #0C0H ;X = #0C0H ?
BNE RAM_CLR
;
LDX #0FEH ;Stack Pointer Initial
TXSP ;SP. <- #0FEH

LDM R0,#0 ;I/O Port Data Clear
LDM R2,#0

LDM R0DD,#0FFH ;7-Seg. Data Output Mode
LDM R2DD,#00FH ;7-Seg. Strobe Output Mode

LDM STROBE,#0000_1011B
LDM TDR0,#250 ;8us x 250 = 2000us
LDM TM0,#0001_1111B ;Timer0(8bit),8us,Start Count-up
LDM IRQH,#0 ;Clear All Interrupts Requeat Flags
LDM IRQL,#0
LDM IENH,#1100_1000B ;EnableT0,Int0,Int1,Interrupt
LDM IENL,#00H
LDM IEDS,#0101_0101B ;External Int. Falling edge select
LDM PMR4,#03H ;General port OR Int?
SET1 UP_F
EI ;Enable Interrupts

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

;
Loop: nop
IF F_500ms == 1
clr1 F_500ms
call INC_DEC
ENDIF
jmp Loop
;
;***********************************************
; Subject: Inc. or Dec. two digits *
;***********************************************
; Entry: UP_F *
; Return: UP_F=1, Increment two digits *
; UP_F=0, Decrement two digits *
;***********************************************
;
INC_DEC: BBC UP_F,DOWN ;Check Down mode or Up mode
;
;**************************
;* Up Count *
;**************************
;
SETC
LDA #0 ; DIGIT1 <- DIGIT1 + 1
ADC DIGIT1
IF A == #0AH
setc
lda #0
ENDIF
STA DIGIT1 ; Store result into DIGIT1
;
LDA #0 ; When Overflow is set,
ADC DIGIT10 ; DIGIT10 <- DIGIT10 + 1
IF A == #10
lda #0
ENDIF
STA DIGIT10
RET
;
;**************************
;* Down Count *
;**************************
;
DOWN: clrc
lda DIGIT1 ; DIGIT1 <- DIGIT1 - 1
sbc #0
IF A == #0FFH
lda #9
clrc
ELSE
setc
ENDIF
sta DIGIT1 ; Store result into DIGIT1
;
lda DIGIT10 ; When Overflow is set,
sbc #0 ; DIGIT10 <- DIGIT10 - 1
IF A == #0FFH
lda #9
ENDIF
STA DIGIT10
RET
;
;**************************************************************************
; TIMER0,INTERRUPT ROUTINE(2ms)& INT0,INT1 *
;**************************************************************************
;
TMR0_INT:
REG_SAVE ;Save Registers to Stacks
CALL DSPLY ;Segments Data Port Output
CALL Make_500msFalg ;250ms mesurement
REG_RESTORE ;Restore Registers from Stacks
RETI
;
;**************************************************************************
; EXTERNAL INTERRUPT 0 (UP/DOWN KEY) *
;**************************************************************************
;
INT_0: NOT1 UP_F ;INT0 Service routine
RETI ;Toggle the Up/Down mode
;

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

vii

;**************************************************************************
; EXTERNAL INTERRUPT 1 (CLEAR KEY) *
;**************************************************************************
;
INT_1: LDM DIGIT1,#0 ;INT1 Service routine
LDM DIGIT10,#0
LDM TMR_500MS,#0 ;0.5Sec Restart
RETI
;
;***********************************************************************
; Subject: Seven Segment Display (DSPLY) *
;***********************************************************************
; Entry: DIGIT10 or DIGIT1 *
; Return: Output SEG_PORT (R00~R07), *
; Strobe_port (R22,R23) *
; Scratch: STROBE *
;***********************************************************************
; Description: After read internal RAM data, output data to the port *
;***********************************************************************
;
DSPLY: LDM STROBE_PORT,#03H ;Segment All Turn Off
NOT1 STROBE.2 ;Toggle strobe0
NOT1 STROBE.3 ;Toggle strobe1

IF STROBE.3 = 1 ;Test if R23 is high.
ldy DIGIT1
ELSE
ldy DIGIT10
ENDIF

LDA !FONT+Y
STA SEG_PORT ;Segment Data output
LDA STROBE
STA STROBE_PORT ;Current Digit Turn On
RET ;Quit
;
;***********************************************
; Subject: Set falg at every 500ms *
;***********************************************
; Entry: None *
; Return: 500ms flag (F_500ms) *
;***********************************************
;
Make_500msFalg:
INC TMR_500MS ;count up every 2ms
LDA TMR_500MS
IF A == #250 ;Compare 0.5S
ldm TMR_500MS,#0 ;clear 0.5sec. counter
set1 F_500ms ;set 0.5sec. flag
ENDIF
RET
;
;**************************************************************************
; 7-SEGMENT PATTERN DATA *
; _a_ *
; f | g |b *
; |---| *
; e |___|c *
; d .h *
;**************************************************************************

; Segment: hgfe dcba To be displayed Digit Number

FONT DB 0011_1111B ; 0
DB 0000_0110B ; 1
DB 0101_1011B ; 2
DB 0100_1111B ; 3
DB 0110_0110B ; 4
DB 0110_1101B ; 5
DB 0111_1100B ; 6
DB 0000_0111B ; 7
DB 0111_1111B ; 8
DB 0110_0111B ; 9
;
;**************************************************************************
;
NOT_USED: nop ;Discard Unexpected Interrupts
reti
;
END ;Notice Program End

GMS81508B/16B/24B, GMS82512/16/24

viii

MAY. 2001 Ver 2.0

C. INSTRUCTION

C.1 Terminology List

Terminology

Description

A - Register

X - Register

Y - Register

PSW

Program Status Word

Carry Flag of PSW

Overflow Flag of PSW

Negative Flag of PSW

Master Interrupt Enable Flag of PSW

Zero Flag of PSW

Half Carry Flag of PSW

Break Flag of PSW (software interrupt)

G flag of PSW(Direct Page)

Program Counter

Stack Pointer

#imm

8-Bit Immediate Data

Direct Page Offset Address

!abs

Absolute Address

[ ]

Indirect Address

{ }

{ }+

.bit

Bit Position

A.bit

Bit Position of A-Register

dp.bit

Bit Position of Direct Page Memory

M.bit

Bit Position of Memory (000

~ 0FFF

)

rel

Relative Addressing Data

upage

U - Page(0FF00

~ 0FFFF

) Offset Address

Table CALL Number (0 ~ 15)

Indicate Upper Nibble of OP code

Assignment / Transfer / Shift Left

Shift Right

Exchange

H,h

Hexadecimal

B,b

Binary

Addition

Multiplication

Equal

Logical AND

Exclusive OR

D,d

Decimal

( )

Contents of

Subtraction

Division

Not Equal

Logical OR

(overline)

Logical NOT

Bit Position

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

C.2 Instruction Map

/2:

33333

33334

33343

33344

33433

33434

33443

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34333

34334

34343

34344

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1. STOP instruction is expressed to "00

" to HEX file(filename.hex) which is loaded into MDS with EVA815/816/825xx board.

/2:

43333

43334

43343

43344

43433

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GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

C.3 Alphabetic order table of instruction

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

ADC #imm

Add with carry.

NV - - H - ZC

ADC dp

A + (M) + C

ADC dp + X

ADC !abs

ADC !abs+Y

ADC [dp+X]

ADC [dp]+Y

ADC {X}

ADDW dp

16-bits add without carry : YA

YA + (dp+1)(dp)

NV - - H - ZC

AND #imm

Logical AND

N - - - - - Z -

AND dp

(M)

AND dp + X

AND !abs

AND !abs+Y

AND [dp+X]

AND [dp] + Y

AND {X}

AND1 M.bit

Bit AND C-flag : C

(M.bit)

- - - - - - - C

AND1B M.bit

Bit AND C-flag and NOT : C

(M.bit)

- - - - - - - C

ASL A

Arithmetic shift left

N - - - - - ZC

ASL dp

ASL dp + X

ASL !abs

BBC A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBC dp.bit,rel

5/7

if(bit) = 0, then PC

PC + rel

BBS A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBS dp.bit,rel

5/7

if(bit) = 1, then PC

PC + rel

BCC rel

2/4

Branch if carry bit clear :
if(C) = 0, then PC

PC + rel

MM - - - - Z -

BCS rel

2/4

Branch if carry bit set : If (C) =1, then PC

PC + rel

- - - - - - - -

BEQ rel

2/4

Branch if equal : if (Z) = 1, then PC

PC + rel

- - - - - - - -

BIT dp

Bit test A with memory :

MM - - - - Z -

BIT !abs

M, N

), V

)

BMI rel

2/4

Branch if munus : if (N) = 1, then PC

PC + rel

- - - - - - - -

BNE rel

2/4

Branch if not equal : if (Z) = 0, then PC

PC + rel

- - - - - - - -

BPL rel

2/4

Branch if not minus : if (N) = 0, then PC

PC + rel

- - - - - - - -

BRA rel

Branch always : PC

PC + rel

- - - - - - - -

BRK

Software interrupt:

- - - 1 - 0 - -

"1", M(SP)

(PC

), SP

SP - 1,

M(s)

(PC

), SP

S - 1, M(SP)

PSW,

SP - 1, PC

(0FFDE

), PC

(0FFDF

)

BVC rel

2/4

Branch if overflow bit clear :

- - - - - - - -

If (V) = 0, then PC

PC + rel

BVS rel

2/4

Branch if overflow bit set :

- - - - - - - -

If (V) = 1, then PC

PC + rel

CALL !abs

Subroutine call

- - - - - - - -

CALL [dp]

M(SP)

(PC

), SP

SP-1, M(SP)

(PC

), SP

SP-1

if !abs, PC

abs ; if [dp], PC

(dp), PC

(dp+1)

C 7 6 5 4 3 2 1 0

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

CBNE dp,rel

5/7

Compare and branch if not equal ;

- - - - - - - -

CBNE dp + X,
rel

6/8

If A

(M), then PC

PC + rel.

CLR1 dp.bit

Clear bit : (M.bit)

"0"

- - - - - - - -

CLR1A A.bit

Clear A.bit : (A.bit)

"0"

- - - - - - - -

CLRC

Clear C-flag : C

"0"

- - - - - - - 0

CLRG

Clear G-flag : G

"0"

- - 0 - - - - -

CLRV

Clear V-flag : V

"0"

- 0 - - 0 - - -

CMP #imm

Compare accumulator contents with memory contents

N - - - - - ZC

CMP dp

A - (M)

CMP dp + X

CMP !abs

CMP !abs + Y

CMP [dp + X]

CMP [dp] + Y

CMP {X}

CMPW dp

Compare YA contents with memory pair contents :

N - - - - - ZC

YA - (dp+1)(dp)

CMPX #imm

Compare X contents with memory contents

N - - - - - ZC

CMPX dp

X - (M)

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

N - - - - - ZC

CMPY dp

Y - (M)

CMPY !abs

COM dp

1's complement : (dp)

(dp)

N - - - - - Z -

DAA

Decimal adjust for addition

N - - - - - ZC

DAS

Decimal adjust for substraction

N - - - - - ZC

DBNE dp,rel

5/7

Decrement and branch if not equal :

- - - - - - - -

DBNE Y,rel

4/6

if (M)

0, then PC

PC + rel.

DEC A

Decrement

N - - - - - Z -

DEC dp

M - 1

DEC dp + X

DEC !abs

DEC X

DEC Y

DECW dp

Decrement memory pair : (dp+1)(dp)

{(dp+1)(dp)} - 1

N - - - - - Z -

Disable interrupts : I

"0"

- - - - - 0 - -

DIV

Divide : YA

Q:A, R:Y

NV - - H - Z -

Enable interrupts : I

"1"

- - - - - 1 - -

EOR #imm

Exclusive OR

N - - - - - Z -

EOR dp

(M)

EOR dp + X

EOR !abs

EOR !abs + Y

EOR [ dp + X]

EOR [dp] + Y

EOR {X}

EOR1 M.bit

Bit exclusive-OR C-flag : C

(M.bit)

- - - - - - - C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

(M.bit)

- - - - - - - C

INC A

Increment

N - - - - - ZC

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

GMS81508B/16B/24B, GMS82512/16/24

xii

MAY. 2001 Ver 2.0

INC dp

(M)

(M) + 1

N - - - - - Z -

INC dp + X

INC !abs

INC X

INC Y

INCW dp

Increment memory pair : (dp+1)(dp)

{(dp+1)(dp)} + 1

N - - - - - Z -

JMP !abs

Unconditional jump

- - - - - - - -

JMP [!abs]

jump address

JMP [dp]

LDA #imm

Load accumulator

N - - - - - Z -

100 LDA dp

(M)

101 LDA dp + X

102 LDA !abs

103 LDA !abs + Y

104 LDA [dp + X]

105 LDA [dp]+Y

106 LDA {X}

107 LDA {X}+

X-register auto-increment : A

(M), X

X + 1

108 LDC M.bit

Load C-flag : C

(M.bit)

- - - - - - - C

109 LDCB M.bit

Load C-flag with NOT : C

(M.bit)

- - - - - - - C

110 LDM dp,#imm

Load memory with immediate data : (M)

imm

- - - - - - - -

111 LDX #imm

Load X-register

N - - - - - Z -

112 LDX dp

(M)

113 LDX dp + Y

114 LDX !abs

115 LDY #imm

Load X-register

N - - - - - Z -

116 LDY dp

(M)

117 LDY dp + Y

118 LDY !abs

119 LDYA dp

Load YA : YA

(dp+1)(dp)

N - - - - - Z -

120 LSR A

Logical shift right

N - - - - - ZC

121 LSR dp

122 LSR dp + X

123 LSR !abs

124 MUL

Multiply : YA

Y x A

N - - - - - Z -

125 NOP

No operation

- - - - - - - -

126 NOT1 M.bit

Bit complement : (M.bit)

(M.bit)

- - - - - - - -

127 OR #imm

Logical OR

N - - - - - Z -

128 OR dp

A V (M)

129 OR dp + X

130 OR !abs

131 OR !abs + Y

132 OR [dp +X}

133 OR [dp] + Y

134 OR {X}

135 OR1 M.bit

Bit OR C-flag : C

C V (M.bit)

- - - - - - - C

136 OR1B M.bit

Bit OR C-flag and NOT : C

C V (M.bit)

- - - - - - - C

137 PCALL

U-page call : M(SP)

(PC

), SP

SP -1,

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

(upage), PC

"OFF

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

7 6 5 4 3 2 1 0

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

xiii

138 POP A

Pop from stack

- - - - - - - -

139 POP X

SP + 1, Reg.

M(SP)

140 POP Y

141 POP PSW

(restored)

142 PUSH A

Push to stack

- - - - - - - -

143 PUSH X

M(SP)

Reg. SP

SP - 1

144 PUSH Y

145 PUSH PSW

146 RET

Return from subroutine :

- - - - - - - -

SP+1, PC

M(SP), SP

SP+1, PC

M(SP)

147 RETI

Return from interrupt :

(restored)

SP+1, PSW

M(SP), SP

SP+1,PC

M(SP),

SP+1, PC

M(SP)

148 ROL A

Rotate left through carry

N - - - - - ZC

149 ROL dp

150 ROL dp + X

151 ROL !abs

152 ROR A

Rotate right through carry

N - - - - - ZC

153 ROR dp

154 ROR dp + X

155 ROR !abs

156 SBC #imm

Subtract with carry

NV - - HZC

157 SBC dp

A - (M) - (C)

158 SBC dp + X

159 SBC !abs

160 SBC !abs + Y

161 SBC [dp + X]

162 SBC [dp] + Y

163 SBC {X}

164 SET1 dp.bit

Set bit : (M.bit)

"1"

- - - - - - - -

165 SETA1 A.bit

Set A.bit : (A.bit)

"1"

- - - - - - - -

166 SETC

Set C-flag : C

"1"

- - - - - - - 1

167 SETG

Set G-flag : G

"1"

- - 1 - - - - -

168 STA dp

Store accumulator contents in memory

- - - - - - - -

169 STA dp + X

(M)

170 STA !abs

171 STA !abs + Y

172 STA [dp + X]

173 STA [dp] + Y

174 STA {X}

175 STA {X}+

X-register auto-increment : (M)

A, X

X + 1

176 STC M.bit

Store C-flag : (M.bit)

- - - - - - - -

177 STOP

Stop mode (halt CPU, stop oscillator)

- - - - - - - -

178 STX dp

Store X-register contents in memory

- - - - - - - -

179 STX dp + Y

(M)

180 STX !abs

181 STY dp

Store Y-register contents in memory

- - - - - - - -

182 STY dp + X

(M)

183 STY !abs

184 STYA dp

Store YA : (dp+1)(dp)

- - - - - - - -

185 SUBW dp

16-bits subtract without carry : YA

YA - (dp+1)(dp)

NV - - H - ZC

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

C 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 C

GMS81508B/16B/24B, GMS82512/16/24

xiv

MAY. 2001 Ver 2.0

186 TAX

Transfer accumulator contents to X-register : X

N - - - - - Z -

187 TAY

Transfer accumulator contents to Y-register : Y

N - - - - - Z -

188 TCALL n

Table call :

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

M(SP)

(PC

), SP

SP -1

(Table vector L), PC

(Table vector H)

189 TCLR1 !abs

Test and clear bits with A :

A - (M), (M)

(M)

(A)

N - - - - - Z -

190 TSET1 !abs

Test and set bits with A :

A - (M), (M)

(M) V (A)

N - - - - - Z -

191 TSPX

Transfer stack-pointer contents to X-register : X

N - - - - - Z -

192 TST dp

Test memory contents for negative or zero : (dp) - 00

N - - - - - Z -

193 TXA

Transfer X-register contents to accumulator : A

N - - - - - Z -

194 TXSP

Transfer X-register contents to stack-pointer : SP

N - - - - - Z -

195 TYA

Transfer Y-register contents to accumulator : A

N - - - - - Z -

196 XAX

Exchange X-register contents with accumulator : X

- - - - - - - -

197 XAY

Exchange Y-register contents with accumulator : Y

- - - - - - - -

198 XCN

Exchange nibbles within the accumulator:

N - - - - - Z -

~ A

199 XMA dp

Exchange memory contents with accumulator

N - - - - - Z -

200 XMA dp + X

(M)

201 XMA {X}

202 XYX

Exchange X-register contents with Y-register : X

- - - - - - - -

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

C.4 Instruction Table by Function

Arithmetic/Logic Operation

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

ADC #imm

Add with carry.

NV - - H - ZC

ADC dp

A + (M) + C

ADC dp + X

ADC !abs

ADC !abs+Y

ADC [dp+X]

ADC [dp]+Y

ADC {X}

AND #imm

Logical AND

N - - - - - Z -

AND dp

(M)

AND dp + X

AND !abs

AND !abs+Y

AND [dp+X]

AND [dp] + Y

AND {X}

ASL A

Arithmetic shift left

N - - - - - ZC

ASL dp

ASL dp + X

ASL !abs

CMP #imm

Compare accumulator contents with memory contents

N - - - - - ZC

CMP dp

A - (M)

CMP dp + X

CMP !abs

CMP !abs + Y

CMP [dp + X]

CMP [dp] + Y

CMP {X}

CMPX #imm

Compare X contents with memory contents

N - - - - - ZC

CMPX dp

X - (M)

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

N - - - - - ZC

CMPY dp

Y - (M)

CMPY !abs

COM dp

1's complement : (dp)

(dp)

N - - - - - Z -

DAA

Decimal adjust for addition

N - - - - - ZC

DAS

Decimal adjust for subtraction

N - - - - - ZC

DEC A

Decrement

N - - - - - Z -

DEC dp

M - 1

DEC dp + X

DEC !abs

DEC X

DEC Y

DIV

Divide : YA

Q:A, R:Y

NV - - H - Z -

C 7 6 5 4 3 2 1 0

GMS81508B/16B/24B, GMS82512/16/24

xvi

MAY. 2001 Ver 2.0

EOR #imm

Exclusive OR

N - - - - - Z -

EOR dp

(M)

EOR dp + X

EOR !abs

EOR !abs + Y

EOR [ dp + X]

EOR [dp] + Y

EOR {X}

INC A

Increment

N - - - - - ZC

INC dp

(M)

(M) + 1

N - - - - - Z -

INC dp + X

INC !abs

INC X

INC Y

LSR A

Logical shift right

N - - - - - ZC

LSR dp

LSR dp + X

LSR !abs

MUL

Multiply : YA

Y x A

N - - - - - Z -

OR #imm

Logical OR

N - - - - - Z -

OR dp

A V (M)

OR dp + X

OR !abs

OR !abs + Y

OR [dp +X}

OR [dp] + Y

OR {X}

ROL A

Rotate left through carry

N - - - - - ZC

ROL dp

ROL dp + X

ROL !abs

ROR A

Rotate right through carry

N - - - - - ZC

ROR dp

ROR dp + X

ROR !abs

SBC #imm

Subtract with carry

NV - - HZC

SBC dp

A - (M) - (C)

SBC dp + X

SBC !abs

SBC !abs + Y

SBC [dp + X]

SBC [dp] + Y

SBC {X}

TST dp

Test memory contents for negative or zero : (dp) - 00

N - - - - - Z -

XCN

Exchange nibbles within the accumulator:

N - - - - - Z -

~ A

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

7 6 5 4 3 2 1 0

C 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 C

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

xvii

Register / Memory Operation

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

LDA #imm

Load accumulator

N - - - - - Z -

LDA dp

(M)

LDA dp + X

LDA !abs

LDA !abs + Y

LDA [dp + X]

LDA [dp]+Y

LDA {X}

LDA {X}+

X-register auto-increment : A

(M), X

X + 1

LDM dp,#imm

Load memory with immediate data : (M)

imm

- - - - - - - -

LDX #imm

Load X-register

N - - - - - Z -

LDX dp

(M)

LDX dp + Y

LDX !abs

LDY #imm

Load X-register

N - - - - - Z -

LDY dp

(M)

LDY dp + Y

LDY !abs

STA dp

Store accumulator contents in memory

- - - - - - - -

STA dp + X

(M)

STA !abs

STA !abs + Y

STA [dp + X]

STA [dp] + Y

STA {X}

STA {X}+

X-register auto-increment : (M)

A, X

X + 1

STX dp

Store X-register contents in memory

- - - - - - - -

STX dp + Y

(M)

STX !abs

STY dp

Store Y-register contents in memory

- - - - - - - -

STY dp + X

(M)

STY !abs

TAX

Transfer accumulator contents to X-register : X

N - - - - - Z -

TAY

Transfer accumulator contents to Y-register : Y

N - - - - - Z -

TSPX

Transfer stack-pointer contents to X-register : X

N - - - - - Z -

TXA

Transfer X-register contents to accumulator : A

N - - - - - Z -

TXSP

Transfer X-register contents to stack-pointer : SP

N - - - - - Z -

TYA

Transfer Y-register contents to accumulator : A

N - - - - - Z -

XAX

Exchange X-register contents with accumulator : X

- - - - - - - -

XAY

Exchange Y-register contents with accumulator : Y

- - - - - - - -

XMA dp

Exchange memory contents with accumulator

N - - - - - Z -

XMA dp + X

(M)

XMA {X}

XYX

Exchange X-register contents with Y-register : X

- - - - - - - -

GMS81508B/16B/24B, GMS82512/16/24

xviii

MAY. 2001 Ver 2.0

16-Bit Operation

Bit Manipulation

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

ADDW dp

16-bits add without carry : YA

YA + (dp+1)(dp)

NV - - H - ZC

CMPW dp

Compare YA contents with memory pair contents :

N - - - - - ZC

YA - (dp+1)(dp)

DECW dp

Decrement memory pair : (dp+1)(dp)

{(dp+1)(dp)} - 1

N - - - - - Z -

INCW dp

Increment memory pair : (dp+1)(dp)

{(dp+1)(dp)} + 1

N - - - - - Z -

LDYA dp

Load YA : YA

(dp+1)(dp)

N - - - - - Z -

STYA dp

Store YA : (dp+1)(dp)

- - - - - - - -

SUBW dp

16-bits subtract without carry : YA

YA - (dp+1)(dp)

NV - - H - ZC

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

AND1 M.bit

Bit AND C-flag : C

(M.bit)

- - - - - - - C

AND1B M.bit

Bit AND C-flag and NOT : C

(M.bit)

- - - - - - - C

BIT dp

Bit test A with memory :

MM - - - - Z -

BIT !abs

M, N

), V

)

CLR1 dp.bit

Clear bit : (M.bit)

"0"

- - - - - - - -

CLR1A A.bit

Clear A.bit : (A.bit)

"0"

- - - - - - - -

CLRC

Clear C-flag : C

"0"

- - - - - - - 0

CLRG

Clear G-flag : G

"0"

- - 0 - - - - -

CLRV

Clear V-flag : V

"0"

- 0 - - 0 - - -

EOR1 M.bit

Bit exclusive-OR C-flag : C

(M.bit)

- - - - - - - C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

(M.bit)

- - - - - - - C

LDC M.bit

Load C-flag : C

(M.bit)

- - - - - - - C

LDCB M.bit

Load C-flag with NOT : C

(M.bit)

- - - - - - - C

NOT1 M.bit

Bit complement : (M.bit)

(M.bit)

- - - - - - - -

OR1 M.bit

Bit OR C-flag : C

C V (M.bit)

- - - - - - - C

OR1B M.bit

Bit OR C-flag and NOT : C

C V (M.bit)

- - - - - - - C

SET1 dp.bit

Set bit : (M.bit)

"1"

- - - - - - - -

SETA1 A.bit

Set A.bit : (A.bit)

"1"

- - - - - - - -

SETC

Set C-flag : C

"1"

- - - - - - - 1

SETG

Set G-flag : G

"1"

- - 1 - - - - -

STC M.bit

Store C-flag : (M.bit)

- - - - - - - -

TCLR1 !abs

Test and clear bits with A :

A - (M), (M)

(M)

(A)

N - - - - - Z -

TSET1 !abs

Test and set bits with A :

A - (M), (M)

(M) V (A)

N - - - - - Z -

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

xix

Branch / Jump Operation

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

BBC A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBC dp.bit,rel

5/7

if(bit) = 0, then PC

PC + rel

BBS A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBS dp.bit,rel

5/7

if(bit) = 1, then PC

PC + rel

BCC rel

2/4

Branch if carry bit clear :
if(C) = 0, then PC

PC + rel

MM - - - - Z -

BCS rel

2/4

Branch if carry bit set : If (C) =1, then PC

PC + rel

- - - - - - - -

BEQ rel

2/4

Branch if equal : if (Z) = 1, then PC

PC + rel

- - - - - - - -

BMI rel

2/4

Branch if minus : if (N) = 1, then PC

PC + rel

- - - - - - - -

BNE rel

2/4

Branch if not equal : if (Z) = 0, then PC

PC + rel

- - - - - - - -

BPL rel

2/4

Branch if not minus : if (N) = 0, then PC

PC + rel

- - - - - - - -

BRA rel

Branch always : PC

PC + rel

- - - - - - - -

BVC rel

2/4

Branch if overflow bit clear :

- - - - - - - -

If (V) = 0, then PC

PC + rel

BVS rel

2/4

Branch if overflow bit set :

- - - - - - - -

If (V) = 1, then PC

PC + rel

CALL !abs

Subroutine call

- - - - - - - -

CALL [dp]

M(SP)

(PC

), SP

SP-1, M(SP)

(PC

), SP

SP-1

if !abs, PC

abs ; if [dp], PC

(dp), PC

(dp+1)

CBNE dp,rel

5/7

Compare and branch if not equal ;

- - - - - - - -

CBNE dp + X,
rel

6/8

If A

(M), then PC

PC + rel.

DBNE dp,rel

5/7

Decrement and branch if not equal :

- - - - - - - -

DBNE Y,rel

4/6

if (M)

0, then PC

PC + rel.

JMP !abs

Unconditional jump

- - - - - - - -

JMP [!abs]

jump address

JMP [dp]

PCALL

U-page call : M(SP)

(PC

), SP

SP -1,

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

(upage), PC

"OFF

TCALL n

Table call :

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

M(SP)

(PC

), SP

SP -1

(Table vector L), PC

(Table vector H)

GMS81508B/16B/24B, GMS82512/16/24

MAY. 2001 Ver 2.0

Control Operation & etc.

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

BRK

Software interrupt:

- - - 1 - 0 - -

"1", M(SP)

(PC

), SP

SP - 1,

M(s)

(PC

), SP

S - 1, M(SP)

PSW,

SP - 1, PC

(0FFDE

), PC

(0FFDF

)

Disable interrupts : I

"0"

- - - - - 0 - -

Enable interrupts : I

"1"

- - - - - 1 - -

NOP

No operation

- - - - - - - -

POP A

Pop from stack

- - - - - - - -

POP X

SP + 1, Reg.

M(SP)

POP Y

POP PSW

(restored)

PUSH A

Push to stack

- - - - - - - -

PUSH X

M(SP)

Reg. SP

SP - 1

PUSH Y

PUSH PSW

RET

Return from subroutine :

- - - - - - - -

SP+1, PC

M(SP), SP

SP+1, PC

M(SP)

RETI

Return from interrupt :

(restored)

SP+1, PSW

M(SP), SP

SP+1,PC

M(SP),

SP+1, PC

M(SP)

STOP

Stop mode (halt CPU, stop oscillator)

- - - - - - - -

D. MASK ORDER SHEET

MASK ORDER & VERIFICATION SHEET

GMS81508B

1. Customer Information

Company Name

Application

Order Date

YYYY

Tel:

Fax:

Name &
Signature:

.O T P file d a ta

File Name

(Please check mark

into )

Customer should write inside thick line box.

64LQFP

64SDIP

64MQFP

( ) .OTP

3.0V

YYWW

KOREA

GMS815XXB-HF

Customer's logo

Chollian

Internet

Hitel

Package

24K

16K

ROM Size (bytes)

Mask Data

Check Sum ( )

2. Device Information

PFD Option

2.4V

Not use

2 0 0 0

(2 4 K )

4 0 0 0

(1 6 K )

6 0 0 0

(8 K )

7 F F F

3. Marking Specification

Customer logo is not required.

YYWW

KOREA

GMS815XXB-HF

Hynix

Customer's part number

If the customer logo must be used in the special mark, please submit a clean original of the logo.

4. Delivery Schedule

Date

Quantity

Hynix Confirmation

YYYY

Customer sample

Risk order

pcs

E-mail address:

5. ROM Code Verification

YYYY

Verification date:

Please confirm out verification data.

Check sum:

Tel:

Fax:

Name &
Signature:

E-mail address:

YYYY

Approval date:

I agree with your verification data and confirm you to
make mask set.

Tel:

Fax:

Name &
Signature:

E-mail address:

08 or 16 or 24

S e t "F F

" in b la n ke d a re a

-HF

GMS81516B
GMS81524B

MAY, 01. 2001

MASK ORDER & VERIFICATION SHEET

GMS82512

1. Customer Information

Company Name

Application

Order Date

YYYY

Tel:

Fax:

Name &
Signature:

.O T P file d a ta

File Name

(Please check mark

into )

Customer should write inside thick line box.

42SDIP

44MQFP

( ) .OTP

3.0V

YYWW

KOREA

GMS825XX-HH

Customer's logo

Chollian

Internet

Hitel

Package

24K

12K

16K

ROM Size (bytes)

Mask Data

Check Sum ( )

2. Device Information

PFD Option

2.4V

Not use

2 0 0 0

(2 4 K )

4 0 0 0

(1 6 K )

5 0 0 0

(1 2 K )

7 F F F

3. Marking Specification

Customer logo is not required.

YYWW

KOREA

GMS825XX-HH

Hynix

Customer's part number

If the customer logo must be used in the special mark, please submit a clean original of the logo.

4. Delivery Schedule

Date

Quantity

Hynix Confirmation

YYYY

Customer sample

Risk order

pcs

E-mail address:

5. ROM Code Verification

YYYY

Verification date:

Please confirm out verification data.

Check sum:

Tel:

Fax:

Name &
Signature:

E-mail address:

YYYY

Approval date:

I agree with your verification data and confirm you to
make mask set.

Tel:

Fax:

Name &
Signature:

E-mail address:

08 or 16 or 24

S e t "F F

" in b la n ke d a re a

-HH

GMS82516
GMS82524

MAY, 01. 2001

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81516B

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81516B