Table of Contents

OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

PACKAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PORT STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

BASIC INTERVAL TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

TIMER/COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

16-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

16-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

ANALOG TO DIGITAL CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

How to Use A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

BUZZER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

BRK Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Multiple Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Release Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Minimizing Current Consumption in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . 43

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

POWER FAIL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

OSCILLATOR CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

UNUSED PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

GMS81608T (OTP) PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

1. Using the Universal programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2. Using the general EPROM(27C256)
programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

GMS81608T PROGRAMMING MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

APPENDIX

A. INSTRUCTION SET

B. MASK ORDER SHEET

GMS81604 / GMS81608

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

O V E R V I E W

Memory Proliferation

Device

R O M B y t e s

R A M B y t e s

GMS81604

256

GMS81608

256

GMS81608T

8K EPROM

256

Development Tools

The GMS800 family is supported by a full-featured
macro assembler, an in-circuit emulators CHOICE-
Jr.

, socket adapters for OTP device.

The availability of OTP devices are especially useful
for customers expecting frequent code changes and
updates. The OTP devices, packaged in plastic pack-

ages permit the user to program them once. In addition
to the program memory, the configuration fuses must
be programmed.

GMS81604, GMS81608

In-Circuit
Emulators

CHOICE-Jr.

T M

OTP devices

GMS81608T (40 DIP)
GMS81608T K (42 SDIP)
GMS81608T PL (44 pin PLCC)

Socket
Adapters for
OTP Devices

OA816A-40PD (40 DIP)
OA816A-42SD (42 SDIP)
OA816A-44PL (44 PLCC)

Assembler

LGS Macro Assembler

4K/ 8K On-chip Program Memory

256 Bytes of On-Chip Data RAM

Instruction execution time: 0.5us at 8MHz

2.4V to 5.5V Operating Range

1~8 MHz Operating frequency

Basic Interval Timer

Four 8-Bit Timer/ Counters (can be used
as two 16-bit)

Four external interrupt ports

Two Programmable Clock Out

One Buzzer Driving port

31 Programmable I/O, 4 Input pins,

Twelve Interrupt Sources

All LED Direct Drive Output Ports

8-Channel 8-Bit On-Chip Analog to Digital
Converter

Power Fail Processor
(Noise immunity circuit)

Power Down Mode (Stop Mode)

Description

The GMS81604/08 is a high-performance CMOS 8-bit microcontroller with 4K or 8K bytes of ROM. The device
is one of GMS800 family. The LG Semicon GMS81604/08 is a powerful microcontroller which provides a highly
flexible and cost effective solution to many embedded control applications. The GMS81604/08 provides the
following standard features: 8K bytes of ROM, 256 bytes of RAM, 35 I/O lines(33 lines for 40PDIP), 16-bit or
8-bit timer/counter, a precision analog to digital converter, on-chip oscillator and clock circuitry. In addition, the
GMS81604/08 supports power saving modes to reduce power consumption. The Stop Mode saves the RAM
contents but freezes the oscillator disabling all other chip functions until the next hardware reset or external
interrupt.

Features

LG Semicon

GMS81604/08

PIN DESCRIPTIONS

D D

: Supply voltage.

: Circuit Ground.

TEST

: For test purposes only. Connect it to V

D D

RESET

: Reset the MCU.

: Input to the inverting oscillator amplifier and

input to the internal clock operating circuit.

O U T

: Output from the inverting oscillator amplifier.

R00~R07

: R0 is an 8-bit, CMOS, bidirectional I/O

port. As an output port each pin can sink several LS
TTL inputs. R0 pins that have 1 or 0 written to their
Port Direction Mode Register, can be used as outputs
or inputs.

R10~R17

: R1 is an 8-bit, CMOS, bidirectional I/O

port. As an output port each pin can sink several LS
TTL inputs. R1 pins that have 1 or 0 written to their
Port Direction Mode Register, can be used as outputs
or inputs.

R40~R47

: R4 is an 8-bit, CMOS, bidirectional I/O

port. As an output port each pin can sink several LS
TTL inputs. R4 pins that have 1 or 0 written to their
Port Direction Mode Register, can be used as outputs
or inputs.

In addition, Port 4 serves the functions of the various
following special features.

Port Pin

Alternate Function

R40

INT0 (External Interrupt 0)

R41

INT1 (External Interrupt 1)

R42
R43

INT2 (External Interrupt 2)
INT3 (External Interrupt 3)

R44

R45

EC0 (External Count Input to Timer/
Counter 0)
EC2 (External Count Input to Timer/
Counter 2)

R46
R47

T1O (Timer 1 Clock-Out)
T3O (Timer 3 Clock-Out)

R50, R51, R55

: R5 is a 3-bit, CMOS, bidirectional I/O

port. As an output port each pin can sink several LS
TTL inputs. R5 pins that have 1 or 0 written to their
Port Direction Mode Register, can be used as outputs
or inputs. R50 and R51 differs in having internal
pull-ups.

Port R55 serves the functions of special features.

Port Pin

Alternate Function

R55

BUZ (Square wave output for Buzzer
driving)

R60~R67

: R6 is an 8-bit, CMOS, I/O port. R60~R63

can be used as only input, can not be output, R64~R67
are bidirectional I/O port. As an output port each pin
can sink several LS TTL inputs. R64~R67 pins that
have 1 or 0 written to their Port Direction Mode
Register, can be used as outputs or inputs.

R6 serves the functions of following special features.

Port Pin

Alternate Function

R60
R61
R62
R63
R64
R65
R66
R67

AN0 (ADC input 0)
AN1 (ADC input 1)
AN2 (ADC input 2)
AN3 (ADC input 3)
AN4 (ADC input 4)
AN5 (ADC input 5)
AN6 (ADC input 6)
AN7 (ADC input 7)

D D

: Supply voltage to the ladder resistor of ADC

circuit. To enhance the resolution of analog to digital
converter, use independent power source as well as
possible, other than digital power source.

LG Semicon

GMS81604/08

Port Pin

I/O

Descriptions

Pull-up/

Pull-down

R E S E T

S T O P

M o d e

Primary Functions

Secondary Functions

D D

Power supply to MCU

Ground

D D

Power supply for ADC

TEST

Test mode

RESET

Reset the MCU

Pull-up

Low

Last state

Oscillation input

Oscillation

Low

O U T

Oscillation output

Oscillation

High

R00~R07

I/O

General I/O

Input

Last state

R10~R17

I/O

General I/O

Input

Last state

R40/INT0
R41/INT1
R42/INT2
R43/INT3
R44/EC0
R45/EC2
R46/T1O
R47/T3O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

General I/O
"
"
"
"
"
"
"

External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External count input 0
External count input 2
Timer 1 output
Timer 3 output

Input

Last state

R50

R51

R55/BUZ

I/O
I/O
I/O

General I/O
"
"

-
-
Buzzer driving output

Pull-up

Input

Last state

R60/AN0
R61/AN1
R62/AN2
R63/AN3
R64/AN4
R65/AN5
R66/AN6
R67/AN7

I
I
I
I

I/O
I/O
I/O
I/O

General Input
"
"
"
General I/O
"
"
"

Analog input 0
Analog input 1
Analog input 2
Analog input 3
Analog input 4
Analog input 5
Analog input 6
Analog input 7

Input

Last state

N O T E S :

1. R50 and R51 are not physically served on 40 pin package.
2. When input mode is selected, pull-up is activated. In output mode, pull-up is de-activated.
3. In reset status, status of R50,R51 are weak high (Typ. impedance 50~100k

). Other pin impedance is very high(High-Z).

GMS81604/08

LG Semicon

E L E C T R I C A L C H A R A C T E R I S T I C S

Absolute Maximum Ratings

Recommended Operating Conditions

Parameter

Symbol

Condition

Specifications

Unit

Min.

Max.

Supply Voltage

XIN

= 8 MHz

XIN

= 4 MHz

4.5
2.4

5.5
5.5

Operating Frequency

XIN

= 4.5~5.5V

= 2.4~5.5V

1
1

4.2

MHz

Operating Temperature

OPR

-20

Supply Voltage . . . . . . . . . . . . . . . -0.3 to +6.0 V

Storage Temperature . . . . . . . . . . . . -40 to +125

Voltage on any pin with
respect to Ground (V

) . . . . . . -0.3 to V

+0.3 V

Maximum current out of V

pin . . . . . . . . . 150 mA

Maximum current into V

pin . . . . . . . . . 100 mA

Maximum current sunk by (I

per I/O Pin) . . . . 2 0 m A

Maximum output current sourced
by (I

per I/O Pin) . . . . . . . . . . . . . . . 8 m A

Maximum current (

) . . . . . . . . . . . . 120 mA

Maximum current (

) . . . . . . . . . . . . . 5 0 m A

Notice:
Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device at these of any
other conditions above those indicated in the op-
erational sections of this specification is not im-
plied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

GMS81604/08

LG Semicon

DC Characteristics ( 5V )

= 5.0V

10%, V

= 0V, T

= -20 ~ 85

C, f

XIN

= 8 MHz)

Parameter

Pin

Symbol

Test Condition

Specifications

Unit

Min.

Typ.*

Max.

Input High Voltage

, RESET,

R40~R45

IH1

0.8V

R0,R1,R46,R47
R5,R6

IH2

0.7V

Input Low Voltage

IN,

RESET,

R40~R45

IL1

0.2V

R0,R1,R46,R47
R5,R6

IL2

0.3V

Output High Voltage

R0,R1,R4,R5,R6

= 5V

= -2mA

D D

-1.0

D D

-0.4

Output Low Voltage

R0,R1,R4,R5,R6

= 5V

= 10mA

0.6

1.0

Power Fail Detect
Voltage

PFD

=3~4V

3.0

4.0

Input Leakage
Current

RESET, R0, R1,
R4, R5, R6

= V

-5.0

5.0

= 0V

-5.0

5.0

Input Pull-up Current

RESET

= 5V

-180

-120

-30

R50, R51

= 5V

-90

-60

-15

Power Current

Operating mode

XIN

=4MHz

XIN

=8MHz

4.5

STOP mode

STOP

= 5V

Hysteresis

RESET,
R40~R45

= 5V

0.5

0.8

* : Data in "Typ" column is at 5 V, 25

C unless otherwise stated. These parameters are for design guidance only and are not tested.

A/D Converter Characteristics ( 5V )

= 5.0V

10%, V

AIN

= 5.0V, V

= 0V, T

= 25

C )

Parameter

Symbol

Specifications

Unit

Min.

Typ.*

Max.

Analog Input Range

AIN

AVDD

Non-linearity Error

0.7

1.5

LSB

Differential Non-linearity Error

DIF

0.1

0.5

LSB

Zero Offset Error

OFF

1.5

2.5

LSB

Full Scale Error

1.0

1.5

LSB

Accuracy

2.0

3.0

LSB

Input Current

AVDD

0.5

1.0

Conversion Time

CONV

Analog power supply Input
Range

AVDD

4.5

5.0

5.5

* : Data in "Typ" column is at 5 V, 25

C unless otherwise stated. These parameters are for design guidance only and are not tested.

LG Semicon

GMS81604/08

DC Characteristics ( 3V )

= 3.0V

10%, V

= 0V, T

= -20 ~ 85

C, f

XIN

= 4 MHz)

Parameter

Pin

Symbol

Test Condition

Specifications

Unit

Min.

Typ.*

Max.

Input High Voltage

, RESET,

R40~R45

IH1

0.8V

R0,R1,R46,R47
R5,R6

IH2

0.7V

Input Low Voltage

, RESET,

R40~R45

IL1

0.2V

R0,R1,R46,R47
R5,R6

IL2

0.3V

Output High Voltage

R0,R1,R4,R5,R6

= 3V

= -1mA

D D

-0.5

D D

-0.3

Output Low Voltage

R0,R1,R4,R5,R6

= 3V

= 5mA

0.5

0.7

Power Fail Detect
Voltage**

Input Leakage
Current

RESET, R0, R1,
R4, R5, R6

= V

-3.0

3.0

= 0V

-3.0

3.0

Input Pull-up
Current

RESET

= 3V

-60

-40

-15

R50, R51

= 3V

-30

-20

-7.5

Power Current

Operating mode

XIN

=4MHz

STOP mode

STOP

= 3V

Hysteresis

RESET,
R40~R45

= 3V

0.3

0.6

* : Data in "Typ" column is at 3 V, 25

C unless otherwise stated. These parameters are for design guidance only and are not tested.

**: Power Fail Detection function is not available on 3V operation.

A/D Converter Characteristics ( 3V )

= 3.0V

10%, V

AIN

= 3.0V, V

= 0V, T

= 25

Parameter

Symbol

Specifications

Unit

Min.

Typ.*

Max.

Analog Input Range

AIN

AVDD

Non-linearity Error

0.2

1.0

LSB

Differential Non-linearity Error

DIF

0.1

0.5

LSB

Zero Offset Error

OFF

2.0

2.5

LSB

Full Scale Error

1.0

1.5

LSB

Accuracy

2.0

3.0

LSB

Input Current

AVDD

0.3

0.5

Conversion Time

CONV

Analog power supply Input
Range

AVDD

2.7

3.0

3.3

* : Data in "Typ" column is at 3 V, 25

C unless otherwise stated. These parameters are for design guidance only and are not tested.

GMS81604/08

LG Semicon

AC Characteristics

= 2.7~5.5V, V

= 0V, T

= -20 ~ 85

Parameter

Pin

Symbol

Specifications

Unit

Min.

Typ.

Max.

Main clock frequency

XIN

MHz

Oscillation stabilization Time

, X

OUT

External Clock Pulse Width

CPW

External Clock Transition Time

RCP

, t

FCP

Interrupt Pulse Width

INT0, INT1, INT2, INT3

SYS

RESET Input Low Width

RESET

RST

SYS

Event Counter Input Pulse
Width

EC0, EC2

ECW

SYS

Event Counter Transition Time

EC0, EC2

REC

, t

FEC

*: t

SYS

is 2/f

XIN

Timing Chart

1 / f

XIN

RCP

FCP

CPW

0.1V

0.9V

0.8V

0.2V

INT0, INT1
INT2, INT3

RESET

RST

0.2V

EC0, EC2

REC

FEC

ECW

0.8V

0.2V

LG Semicon

GMS81604/08

TYPICAL CHARACTERISTICS

These parameters are for design guidance only and are not tested.

- V

(mA)

=5.0V

=25

(V)

D D

=5V

- V

(mA)

=5.0V

=25

-V

(V)

6 (V)

- V

D D

(mA)

=25

XIN

= 4MHz

XIN

= 8MHz

6 (V)

STOP

(uA)

=25

Operating area

XIN

(MHz)

= -20~80

(V)

GMS81604/08

LG Semicon

M E M O R Y O R G A N I Z A T I O N

The GMS81604 has separate address spaces for Pro-
gram and Data Memory. Program memory can only be
read, not written to. It can be up to 4K (8K for
GMS81608) bytes of Program Memory. Data mem-
ory can be read and written to up to 256 bytes including
the stack area.

Registers

This device has six registers that are the Program
Counter (PC), a Accumulator (A), two Index registers
(X,Y), the Stack Pointer (SP) and the Program Status
Word (PSW). The Program Counter consists of 16-bit
register.

Accumulator

: The accumulator is the 8-bit general

purpose register, used for data operation such as trans-
fer, temporary saving and conditional judgment, etc.

The accumulator can be used as a 16-bit register with
Y register as shown below.

X register, Y register

: In the addressing modes which

use these index registers, the register contents are
added to the specified address and this becomes the
actual address. These modes are extremely effective
for referencing subroutine tables and memory tables.

The index registers also have increment, decrement,
compare and data transfer functions and they can be
used as simple accumulators.

Stack Pointer

: The stack pointer is an 8-bit register

used for occurrence interrupts and calling out subrou-
tines. The stack can be located at any position within
100

to 13F

of the internal data memory. Data store

and restore sequence to(from) stack area is shown in
Figure 0.

Caution:
The stack pointer must be initialized by software
because its value is undefined after reset.
Ex)

LDX

#03FH

TXSP

; SP

Program Counter:

The program counter is a 16-bit

wide which consists of two 8-bit registers, PCH, PCL.
This counter indicates the address of the next instruc-
tion to be executed. In reset state, the program counter
has reset routine address (PCH: FF

, PCL: FE

). .

Program Status Word

: The Program Status Word

(PSW) contains several status bits that reflect the cur-
rent state of the CPU. The PSW shown in Figure 6. It
contains the Negative flag, the Overflow flag, the
Direct page flag, the Break flag, the Half Carry (for
BCD operations), the Interrupt enable flag, the Zero
flag and the Carry bit.

[Carry flag C]
This flag stores any carry or borrow from the ALU of
CPU after an arithmetic operation and is also changed
by the Shift instruction or rotate instruction.

[Zero flag Z]
This flag is set when the result of an arithmetic opera-
tion or data transfer is "0" and is cleared by any other
result.

[Interrupt disable flag I] This flag enables/disables all
interrupts except interrupt caused by Reset or software

PCH

PCL

PSW

ACCUMULATOR

PROGRAM COUNTER

X REGISTER

Y REGISTER

STACK POINTER

PROGRAM STATUS
WORD

Figure 3. Configuration of Registers

TWO 8-BIT REGISTERS

ONE "YA" 16-BIT REGISTER

Figure 4. Configuration of YA 16-bit register

Hardware fixed.

8 7

Stack Address (100

~13F

)

Figure 5. Stack Pointer

GMS81604/08

LG Semicon

BRK instruction. All interrupts are disabled when
cleared to "0". This flag immediately becomes "0"
when an interrupt is served. It is set by the EI instruc-
tion, cleared by the DI instruction.

[Half carry flag H]
After operation, set when there is a carry from bit 3 of
ALU or there is not a borrow from bit 4 of ALU. This
bit can not be set or cleared except CLRV instruction,
clearing with Overflow flag (V).

[Break flag B]
This flag set by software BRK instruction to distin-
guish BRK from TCALL instruction which as the
same vector address.

[Direct page flag G]
This flag assign direct page for direct addressing mode.
In the direct addressing mode, addressing area is

within zero page 00

to FF

when this flag is "0". If it

is set to "1", addressing area is 100

to 1FF

It is set by SETG instruction, and cleared by CLRG.

[Overflow flag V]
This flag is set to "1" when an overflow occurs in the
result of an arithmetic operation involving signs. An
overflow occurs when the result of an addition or
subtraction exceeds +127(7F

) or -128(80

The CLRV instruction clears the overflow flag. There
is no set instruction. When the BIT instruction is
executed, for other than the above, bit 6 of memory is
copy to this flag.

[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the
result of a data or arithmetic operation. When the BIT
instruction is executed, bit 7 of memory is copy to this
flag.

CARRY FLAG RECEIVES
CARRY OUT

ZERO FLAG

INTERRUPT ENABLE
FLAG

HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERANDS

BRK FLAG

G FLAG TO SELECT DIRECT PAGE

OVERFLOW FLAG

NEGATIVE FLAG

P S W

MSB

LSB

RESET VALUE: 00H

Figure 6. PSW (Program Status Word) Register

M(SP)

(PCH)

1) INTERRUPT

SP - 1

M(SP)

(PCL)

SP - 1

M(SP)

(PSW)

SP - 1

(PCH)

M(SP)

2) RETI

SP + 1

(PCL)

M(SP)

SP + 1

(PSW)

M(SP)

SP + 1

M(SP)

(PCH)

3) CALL

SP - 1

M(SP)

(PCL)

SP - 1

4) RET

SP + 1

(PCH)

M(SP)

SP + 1

(PCL)

M(SP)

ACC.

5) PUSH A (X,Y,PSW)

SP - 1

M(SP)

(PCH)

6) POP A (X,Y,PSW)

SP + 1

Figure 7. Stack Operation

LG Semicon

GMS81604/08

Program Memory

A 16-bit program counter is capable of addressing up
to 64K bytes, but this devices have 4K bytes (8K for
GMS81608) program memory space only the physi-
cally implemented. Accessing a location above FFFF

will cause a wrap-around to 0000

Figure 8, shows a map of the upper part of the Program
Memory. After reset, the CPU begins execution from
reset vector which is stored in address FFFE

, FFFF

As shown in Figure 8, each area is assigned a fixed
location in Program Memory. Program Memory area
contains the user program, Page Call (PCALL) area
contains subroutine program, to reduce program byte
length because of using by 2 bytes PCALL instead of
3 bytes CALL instruction. If it is frequently called,
more useful to save program byte length.

Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences execution of the
service routine. The Table Call service locations are
spaced at 2-byte interval : FFC0

for TCALL15,

FFC2

for TCALL14, etc.

Address

T C A L L N a m e

FFC0H
FFC2H
FFC4H
FFC6H
FFC8H

FFCAH
FFCCH
FFCEH

FFD0H
FFD2H
FFD4H
FFD6H
FFD8H

FFDAH
FFDCH
FFDEH

TCALL15
TCALL14
TCALL13
TCALL12
TCALL11
TCALL10
TCALL9
TCALL8
TCALL7
TCALL6
TCALL5
TCALL4
TCALL3
TCALL2
TCALL1
TCALL0/ BRK

1) The BRK software interrupt is using same address with
TCALL0.

The interrupt causes the CPU to jump to specific
location, where it commences execution of the service
routine. The External interrupt 0, for example, is as-
signed to location FFFA

. The interrupt service loca-

tions are spaced at 2-byte interval : FFF8

for External

Interrupt 1, FFFA

for External Interrupt 0, etc.

Any area from FF00

to FFFF

, if it not going to be

used, its service location is available as general pur-
pose Program Memory.

Address

Vector Name

FFE0H
FFE2H
FFE4H
FFE6H
FFE8H

FFEAH
FFECH
FFEEH

FFF0H
FFF2H
FFF4H
FFF6H
FFF8H

FFFAH
FFFCH
FFFEH

-
-
-
Basic Interval Timer
Watch Dog Timer
Analog to Digital Converter
Timer/ Counter 3
Timer/ Counter 2
Timer/ Counter 1
Timer/ Counter 0
External Interrupt 3
External Interrupt 2
External Interrupt 1
External Interrupt 0
-
RESET

F000H

FFFFH

FEFFH

FF00H

PROGRAM

MEMORY

PCALL

AREA

FFBFH
FFC0H

TCALL

AREA

INTERRUPT

VECTOR

AREA

FFDFH

FFE0H

GMS81608

E000H

GMS81604

Figure 8. Program Memory

GMS81604/08

LG Semicon

Data Memory

Figure 9 shows the internal Data Memory space avail-
able. Data Memory are divided into three groups, a
user RAM, control registers and Stack.

Internal Data Memory addresses are always one byte
wide, which implies an address space of 256 bytes
including the stack area. To access above FF

, G-flag

should be set to "1" before, because after MCU reset,
G-flag is "0".

The stack pointer should be initialized within 00

by software because of implemented area of

internal data memory.

The control registers are used by the CPU and Periph-
eral functions for controlling the desired operation of
the device.
Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog
to digital converters, I/O ports. The control registers
are in address C0

to FF

Note that unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses
will in general return random data, and write accesses
will have an indeterminate effect.

More detail informations of each register are explained
in each peripheral sections.

Caution:
Write only registers can not be accessed by bit
manipulation instruction.

Address

Symbol

R / W

Power-on

Reset Value

H 2)

R0
R0DD
R1
R1DD
R4
R4DD
R5
R5DD
R6
R6DD
PMR4
PMR5
BITR
CKCTLR
WDTR
TM0
TM2

Note 3

ADCM
ADR
BUR
PFDR
IENL
IRQL
IENH
IRQH
IEDS

R/W
W

R
W

R/W
R/W
R/W
R/W
R/W
R/W
R/W

R
W

R/W
R/W
R/W
R/W
R/W
W

00000000

--0---00

00000000
00000000
--0-----
00000000
--010111
-0111111
00000000
00000000

X
X
X
X

--000001

X
X

-----100
000-----
000-----
00000000
00000000
00000000

Legend - = Unimplemented locations.
X= Undefined value.

N O T E S :

1) The all write only registers can not be accessed by bit
manipulation instruction.
2) The register BITR and CKCTLR are located at same address.
Address D3H is read as BITR, as written to CKCTLR.
3) Several names are given at same address. Refer to below
table.

Address

When read

When write

Timer mode

Capture Mode

E4H
E5H
E6H
E7H

T0
T1
T2
T3

CDR0
CDR1
CDR2
CDR3

TDR0
TDR1
TDR2
TDR3

4) Only bit 0 of ADCM can be read.

13F

DATA

MEMORY

(RAM)

CONTROL

REGISTERS

STACK

AREA

100

256 BYTES

Figure 9. Data Memory

LG Semicon

GMS81604/08

Control Registers for the GMS81604/08

Address

N a m e

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R0 port data register

R0DD

R0 port direction register

R1 port data register

R1DD

R1 port direction register

R4 port data register

R4DD

R4 port direction register

R5 port data register

R5DD

R5 port direction register

R6 port data register

R6DD

R6 port direction register

PMR4

T3S

T1S

EC2S

EC0S

INT3S

INT2S

INT1S

INT0S

PMR5

BUZS

H 1)

BITR

Basic Interval Timer data register

H 1)

CKCTLR

WDTON

ENPCK

BTCL

BTS2

BTS1

BTS0

WDTR

WDTCL

6-bit Watch Dog Counter register

TM0

CAP0

T1ST

T1SL1

T1SL0

T0ST

T0CN

T0SL1

T0SL0

TM2

CAP2

T3ST

T3SL1

T3SL0

T2ST

T2CN

T2SL1

T2SL0

T0/ TDR0/ CDR0

Timer 0 register/ Timer data register 0/ Capture data register 0

T1/ TDR1/ CDR1

Timer 1 register/ Timer data register 1/ Capture data register 1

T2/ TDR2/ CDR2

Timer 2 register/ Timer data register 2/ Capture data register 2

T3/ TDR3/ CDR3

Timer 3 register/ Timer data register 3/ Capture data register 3

ADCM

ADEN

ADS2

ADS1

ADS0

ADST

ADSF

ADR

ADC result data register

BUR

BUCK1

BUCK0

BU5

BU4

BU3

BU2

BU1

BU0

H 2)

PFDR

PFD

PFR

PFS

IENL

WDTE

BITE

IRQL

AIF

WDTIF

BITIF

IENH

INT0E

INT1E

INT2E

INT3E

T0E

T1E

T2E

T3E

IRQH

INT0IF

INT1IF

INT2IF

INT3IF

T0IF

T1IF

T2IF

T3IF

IEDS

IED3H

IED3L

IED2H

IED2L

IED1H

IED1L

IED0H

IED0L

Legend - = Unimplemented locations.

N O T E S :

1) The register BITR and CKCTLR are located at same address. Address D3

is read as BITR, written to CKCTLR.

2) The register PFDR only be implemented on device, not on In-circuit Emulator.

GMS81604/08

LG Semicon

I/O PORTS

The GMS81604/08 have five ports, R0, R1, R4, R5,
R6. These ports pins may be multiplexed with an
alternate function for the peripheral features on the
device. In general, when a initial reset state, all ports
are used as a general purpose input port.

All pins have data direction registers which can con-
figure these pins as output or input.
A "1" in the port direction register configures the
corresponding port pin as output. Conversely, write
"0" to the corresponding bit to specify as an input pin.
For example, to use the even numbered bit of R1 as
output ports and the odd numbered bits as input ports,
write "55

" to address C1

(R0 direction register)

during initial setting as shown in Figure 10.

Reading data register reads the status of the pins
whereas writing to it will write to the port latch.

R0 and R0DD registers:

R0 is a 8-bit bidirectional

I/O port (address C0

). Each pin is individually con-

figurable as input and output through the R0DD regis-
ter (address C1

R1 and R1DD registers:

R1 is an 8-bit bidirectional

I/O port (address C2

). Each pin is individually con-

figurable as input and output through the R1DD regis-
ter (address C3

R4 and R4DD registers:

R4 is an 8-bit bidirectional

I/O port (address C8

). Each pin is individually con-

figurable as input and output through the R4DD regis-
ter (address C9

In addition, Port R4 is multiplexed with various special
features. The control register PMR4 (address D0

)

controls to select alternate function. After reset, this
value is "0", port may be used as general I/O ports. To
select alternate function such as External interrupt or
External counter or Timer clock out, write "1" to the
corresponding bit of PMR4.

Port Pin

Alternate Function

R40
R41
R42
R43

INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
INT2 (External Interrupt 2)
INT3 (External Interrupt 3)

R44

R45

EC0 (External Count Input to Timer/
Counter 0)
EC2 (External Count Input to Timer/
Counter 2)

R46
R47

T1O (Timer 1 Clock-Out)
T3O (Timer 3 Clock-Out)

Regardless of the direction register R4DD, PMR4 is
selected to use as alternate functions, port pin can be
used as a corresponding alternate features.

0 1 0 1 0 1 0 1

I O I O I O

WRITE "55

" TO PORT R0 DIRECTION REGISTER

7 6 5 4 3 2 1 0 BIT

7 6 5 4 3 2 1 0 PORT

R0 DATA

R0 DIRECTION

R1 DATA

R1 DIRECTION

C0H
C1H
C2H
C3H

I: INPUT PORT
O: OUTPUT PORT

Figure 10. Example port I/O assignment

R07 R06 R05 R04 R03 R02 R01 R00

Port 0 Data Register

ADDRESS: C0

RESET VALUE: Undefined

R07 R06 R05 R04 R03 R02 R01 R00

R 0 D D

ADDRESS: C1

RESET VALUE: 00000000

Direction select
0: Input
1: Output

Input/ Output data

R 0

Port 0 Direction Register

R17 R16 R15 R14 R13 R12 R11 R10

Port 1 Data Register

ADDRESS: C2

RESET VALUE: Undefined

R17 R16 R15 R14 R13 R12 R11 R10

R 1 D D

ADDRESS: C3

RESET VALUE: 00000000

Direction select
0: Input
1: Output

Input/ Output data

Port 1 Direction Register

LG Semicon

GMS81604/08

R5 and R5DD registers:

R5 is a 3-bit bidirectional

I/O port (address CA

). R50, R51 and R55 only are

physically implemented on this device.
R50, R51 have internal pullups which is activated on
input but deactivated on output. As input, these pins
that are externally pull low will source current (I

the DC characteristics) because of the internal pullups.

Caution:
Pins R50, R51 are present on 42SDIP, 44PLCC
package only, but not on 40DIP . Refer to Pin as-
signment.

Each pin is individually configurable as input and
output through the R5DD register (address CB

Port Pin

Alternate Function

R55

BUZ (Square-wave output for
Buzzer driving)

The control register PMR5 (address D1

) controls the

selection alternate function. After reset, this value is
"0", port may be used as general I/O ports. To use
buzzer function, write "1" to the PMR5.

R47 R46 R45 R44 R43 R42 R41 R40

Port 4 Data Register

ADDRESS: C8

RESET VALUE: Undefined

R47 R46 R45 R44 R43 R42 R41 R40

R 4 D D

ADDRESS: C9

RESET VALUE: 00000000

Direction select
0: Input
1: Output

Input/ Output data

R 4

Port 4 Direction Register

T3S T1S EC2S EC0S INT3S INT2S INT1S INT0S

P M R 4

ADDRESS: D0

RESET VALUE: 00000000

0: R41
1: INT1

0: R47
1: T3O

0: R45
1: EC2

0: R46
1: T1O

0: R44
1: EC0

0: R43
1: INT3

0: R42
1: INT2

0: R40
1: INT0

MSB

LSB

IEDS

ADDRESS: F8

RESET VALUE: 00000000

Edge Selection Register

External Interrupt Edge select
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)

INT3

INT2

INT1

INT0

Port 4 Mode Register

R55

R51 R50

Port 5 Data Register

ADDRESS: CA

RESET VALUE: Undefined

R55

R51 R50

R 5 D D

ADDRESS: CB

RESET VALUE: --0---00

Direction select
0: Input
1: Output

Input/ Output data

Port 5 Direction Register

BUZS

P M R 5

ADDRESS: D1

RESET VALUE: --0-----

Port 5 Mode Register

0: R55
1: BUZ (Buzzer Port)

GMS81604/08

LG Semicon

R6 and R6DD registers: R6 is an 8-bit port (address
CC

). Pins R64~R67 are individually configurable as

input and output through the R6DD register (address
CD

), but pins R60~R63 are input only.

Port Pin

Alternate Function

R60
R61
R62
R63
R64
R65
R66
R67

AN0 (ADC input 0)
AN1 (ADC input 1)
AN2 (ADC input 2)
AN3 (ADC input 3)
AN4 (ADC input 4)
AN5 (ADC input 5)
AN6 (ADC input 6)
AN7 (ADC input 7)

R6DD (address CD

) controls the direction of the R6

pins, even when they are being used as analog inputs.
The user must make sure to keep the pins configured
as inputs when using them as analog inputs.

On the initial RESET, R60 can not be used digital

input port, because this port is selected as an ana-

log input port by ADCM register. To use this port as

a digital I/O port, change the value of lower 4 bits of

ADCM (address 0E8

On the other hand, R6 port, all eight pins can not be

used as digital I/O port simultaneousely. At least

one pin is used as an analog input.

R67 R66 R65 R64 R63 R62 R61 R60

Port 6 Data Register

ADDRESS: CC

RESET VALUE: Undefined

R67 R66 R65 R64 R63 R62 R61 R60

R6DD

ADDRESS: CD

RESET VALUE: 0000----

Direction select
0: Input
1: Output

Input/ Output data

Port 6 Direction Register

Fixed as Input.
Can not write.

LG Semicon

GMS81604/08

BASIC INTERVAL TIMER

The GMS81604 has one 8-bit Basic Interval Timer that
is free-run, can not stop. Block diagram is shown in
Figure 11.
The 8-bit Basic interval timer register (BITR) is incre-
mented every internal count pulse which is divided by
prescaler. Since prescaler has divided ratio by 16 to
2048, the count rate is 1/16 to 1/2048 of the oscillator
frequency. As the count overflows from FF

to 00

this overflow causes to generate the Basic interval
timer interrupt. The BITR is interrupt request flag of

Basic interval timer.

Caution:
All control bits of Basic interval timer are in
CKCTLR register which is located at same ad-
dress of BITR (address D3

). Address D3

read as BITR, written to CKCTLR.

When write "1" to bit BTCL of CKCTLR, data register
is cleared to "0" and restart to count-up. It becomes "0"
after one machine cycle by hardware.

128

256

512

1024

2048

BITR (8 BITS)

BASIC INTERVAL TIMER
INTERRUPT

BTCL

BITIF

BTS[2:0]

CLEAR

PRESCALER

MUX

Figure 11. Block Diagram of The Basic Interval Timer

Symbol

Position

Name and Significance

WDTON

CKCTLR.5

WDTON=1, enables Watch Dog Timer operation,
WDTON=0, operates as a 6-bit timer

ENPCK

CKCTLR.4

Enable Peripheral clock.

BTCL

CKCTLR.3

BTCL is set to "1", BITR is cleared. BTCL becomes "0" automatically
after one machine cycle, and starts counting.

BASIC INTERVAL TIMER CLOCK SELECTION

BTS2

BTS1

BTS0

Prescale value

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

16
32
64

128
256
512

1024
2048

W D T O N

ENPCK BTCL

BTS1

BTS2

BTS0

C K C T L R

ADDRESS: D3

RESET VALUE: --010111

Figure 12. CKCTLR: Control Clock Register

GMS81604/08

LG Semicon

T I M E R / C O U N T E R

The GMS81604 has four Timer/Counter registers.
Each module can generate an interrupt to indicate that
an event has occurred (i.e. timer match).

Timer 0 and Timer 1 are can be used either the two
8-bit Timer/Counter or one 16-bit Timer/Counter to
combine them. Also Timer 2 and Timer 3 are same.

In the "timer" function, the register is incremented
every internal clock input. Thus, one can think of it as
counting internal clock input. Since a least clock con-
sists of 4 and most clock consists of 64 oscillator
periods, the count rate is 1/4 to 1/64 of the oscillator
frequency.

In the "counter" function, the register is incremented
in response to a 1-to-0 (falling edge) transition at its
corresponding external input pin, EC0 or

EC2.

In addition the "capture" function, the register is incre-
mented in response external or internal clock sources
same with timer or counter function. When external
clock edge input, the count register is captured into
Timer data register correspondingly.

It has four operating modes: "8-bit timer/counter",

"16-bit timer/counter", "8-bit capture", "16-bit cap-
ture" which are selected by bit in Timer mode register
TM0 and TM2 as shown in right Table.

In operation of Timer 2, Timer 3, their operations are
same with Timer 0, Timer 1, respectively.

TM0 FOR TIMER 0, TIMER 1

CAP0

T1SL1

T1SL0

Timer 0

Timer 1

16-bit Timer/Counter

16-bit Capture

8-bit Timer

8-bit Capture

8-bit Timer

TM2 FOR TIMER 2, TIMER 3

CAP2

T3SL1

T3SL0

Timer 2

Timer 3

16-bit Timer/Counter

16-bit Capture

8-bit Timer

8-bit Capture

8-bit Timer

TIMER 1

TIMER 0

T1SL1

T1SL0 INPUT CLOCK

T0SL1

T0SL0 INPUT CLOCK

0
0
1
1

0
1
0
1

16-BIT TIMER MODE (NOTE 1)
8-BIT TIMER,

PRESCALER

8-BIT TIMER,

0
0
1
1

0
1
0
1

Timer or Counter select

PRESCALER

T M 0

LSB

MSB

T1SL1

T1ST

T1SL0

T0ST

T0SL1

T0CN

T0SL0

CAP0

Capture mode selection flag, When set, timer
operate as one 16-bit capture timer combine
two 8-bit timers.

CAP0

When set, Timer 1 count register is cleared
and start again.
When cleared, stop the counting.

T1ST

Start/Stop control for Timer 0. A logic 1
starts the timer.

T0CN

When set, The Timer 0 Count Register is
cleared and start again.
When cleared, stop the counting.

T0ST

TIMER 1

TIMER 0

TM2 is in Figure 14.

NOTE:
If this mode selected, the Timer 0 are used as a 16-bit timer mode. The Timer 1 is engaged to the Timer 0.
The source clock is selected by bits T0SL1 and T0SL0.

ADDRESS: E2

RESET VALUE: 00H

Figure 13. TM0: Timer 0, Timer 1 Mode Register

LG Semicon

GMS81604/08

TIMER 3

TIMER 2

T3SL1

T3SL0 INPUT CLOCK

T2SL1

T2SL0 INPUT CLOCK

0
0
1
1

0
1
0
1

16-BIT TIMER MODE (NOTE 1)
8-BIT TIMER,

PRESCALER

8-BIT TIMER,

0
0
1
1

0
1
0
1

Timer or Counter select

PRESCALER

LSB

MSB

T3SL1

T3ST

T3SL0

T2ST

T2SL1

T2CN

T2SL0

CAP2

T M 2

Capture mode selection flag, When set, timer
operate as one 16-bit timer combine two 8-bit
timers. See Figure 21 and Figure 22.

CAP2

When set, Timer 3 count register is cleared
and start again.
When cleared, stop the counting.

T3ST

Start/Stop control for Timer 2. A logic 1
starts the timer.

T2CN

When set, Timer 2 count register is cleared
and start again.
When cleared, stop the counting.

T2ST

NOTE:
If this mode selected, the Timer 2 and Timer 3 are used as a 16-bit timer mode. The Timer 3 is engaged to
the Timer 2. The source clock is selected by bits T2SL1 and T2SL0.

TIMER 3

TIMER 2

ADDRESS: E3

RESET VALUE: 00

Figure 14. TM2: Timer 2, Timer 3 Mode Register

LSB

MSB

T D R 0

T D R 1

T D R 2

T D R 3

ADDRESS: E4

RESET VALUE: 00

ADDRESS: E5

RESET VALUE: 00

ADDRESS: E6

RESET VALUE: 00

ADDRESS: E7

RESET VALUE: 00

Figure 15. TDRx : Timer x Data Register

GMS81604/08

LG Semicon

8-bit Timer/Counter Mode

The GMS81604 has four 8-bit Timer/Counters, Timer
0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1
only as shown in Figure 16. because other timer/count-
ers are same with Timer 0 and Timer 1.

The "timer" or "counter" function is selected by control
registers TM0, TM2 as shown in Figure 13 and Figure
14. To use as an 8-bit timer/counter mode, bit CAP0
of TM0 is cleared to "0" and bits T1SL1, T1SL0 of
TM0 or bits T3SL1, T3SL0 of TM2 should not set to
zero (Figure 16).
These timers have each 8-bit count register and data
register. The count register is incremented by every
internal or external clock input. The internal clock has
a prescaler divide ratio option of 4, 16, 64 (selected by
control bits TxSL1, TxSL0 of register TMx).

In the Timer 0, timer register T0 increments from 00

until it matches TDR0 and then reset to 00

. The match

output of Timer 0 generates Timer 0 interrupt (latched
in T0IF bit)

As TDRx and Tx register are in same address, when
reading it as a Tx, written to TDRx.

Caution:
The contents of Timer data register TDRx should
be initialized 1

~FF

except 0

, because it is un-

defined after reset.

In counter function, the counter is incremented every
1-to 0 (falling edge) transition of EC0 or EC2 pin. In
order to use counter function, the bit EC0S, EC2S of
the Port mode register PMR4 are set to "1". The Timer
0 can be used as a counter by pin EC0 input, but Timer
1 can not. Similarly, Timer 2 can be used by pin EC2
input but Timer 3 can not.

T M 0

CAP0

T1ST

T1SL1 T1SL0

T0ST

T0CN

T0SL1 T0SL0

TDR0 (8-BITS)

TIMER 0
INTERRUPT

T0SL[1:0]

EC0 PIN

T0 (8-BITS)

T0CN

COMPARATOR

T0ST

CLEAR

TIMER 1
INTERRUPT

T1O PIN

T1IF

F/F

T0IF

MUX

T1SL[1:0]

MUX

TDR1 (8-BITS)

T1 (8-BITS)

T1ST

PRESCALER

COMPARATOR

CLEAR

TIMER 0

TIMER 1

MSB

LSB

EDGE DETECTOR

0: Stop
1: Clear and Start

ADDRESS: E2

RESET VALUE: 00

Figure 16. 8-bit Timer/Counter Mode

LG Semicon

GMS81604/08

To pulse out, the timer match can goes to port pin as
shown in Figure 16. Thus, pulse out is generated by
the timer match. These operation is implemented to
pin, T1O and T3O. The pin T1O is output from Timer
1, the T3O is from Timer 3. Operation of T3O is
omitted in this document, but still presents and same
architecture with T1O.

T x O

(

H z

)

O s c i l l a t o r

Frequency

Prescaler

T D R

T3S

0: R47
1: T3O (TIMER 3 OUTPUT)

INT3S

0: R43
1: INT3 (EXTERNAL INTERRUPT 3)

T1S

0: R46
1: T1O (TIMER 1 OUTPUT)

INT2S

0: R42
1: INT2 (EXTERNAL INTERRUPT 2)

EC2S

0: R45
1: EC2 (EXTERNAL INPUT PIN FOR
T I M E R 2

INT1S

0: R41
1: INT1 (EXTERNAL INTERRUPT 1)

EC0S

0: R44
1: EC0 (EXTERNAL INPUT PIN FOR
T I M E R 0

INT0S

0: R40
1: INT0 (EXTERNAL INTERRUPT 0)

LSB

MSB

EC2S

T1S

EC0S

INT3S

INT1S

INT2S

INT0S

T3S

P M R 4

ADDRESS: D0

RESET VALUE: 00

Figure 17. PMR4: R4 Port Mode Register

TDR0

MATCH

(TDR0 = T0)

TIMER 0

INTERRUPT

TIME

CLEAR

OCCUR INTERRUPT

CLEAR

OCCUR INTERRUPT

INTERRUPT

PERIOD

OCCUR INTERRUPT

COUNT PULSE

PERIOD

When TM0: 00110111 (PRESCALER= 16)
TDR0: F9

= 249

OSCILLATOR FREQ.= 4MHz

INTERRUPT PERIOD

(

249

)

= 1ms

EX)

4 us

Figure 18. Timer Count Example

GMS81604/08

LG Semicon

16-bit Timer/Counter Mode

The Timer register is being run with all 16 bits. A 16-bit
timer/counter register T0, T1 are incremented from
0000

until it matches TDR0, TDR1 and then resets

to 0000

. The match output generates Timer 0 inter-

rupt.

The clock source of the Timer 0 is selected either
internal or external clock by bit T0SL1, T0SL0.

Even if the Timer 0 (including the Timer 1) is used as
a 16-bit timer, the Timer 2 and Timer 3 can still be used
as either two 8-bit timer or one 16-bit timer by setting
the TM2. Reversely, even if the Timer 2 (including the
Timer 3) is used as a 16-bit timer, the Timer 0 and
Timer 1 can still be used as 8-bit timer independently.

T M 0

CAP0

T1ST

T1SL1 T1SL0

T0ST

T0CN

T0SL1 T0SL0

MSB

LSB

TDR0

(8-BITS)

TIMER 0
INTERRUPT

T0SL[1:0]

XIN PIN

EC0 PIN

(8-BITS)

T0CN

COMPARATOR

T0ST

CLEAR

T0IF

MUX

PRESCALER

T I M E R 0

TDR1

(8-BITS)

THIS FIGURE IS A EXAMPLE OF THE TIMER 0 AND
TIMER 1.
IN THE TIMER 2, EACH REGISTERS AND FLAGS MAY BE
CHANGED CORRESPONDINGLY.

(NOT TIMER 1 INTERRUPT)

EDGE DETECTOR

0: Stop
1: Clear and Start

ADDRESS: E2

RESET VALUE: 00

HIGHER

LOWER

(+TIMER1)

DO NOT CARE

Figure 19. 16-bit Timer/Counter Mode

TDR0

MATCH

TIMER

INTERRUPT

TIME

CLEAR

OCCUR INTERRUPT

MATCH

Clear and Start

Stop

TxST

TxCN

Restart

Count Up

HIGH

LOW

HIGH

LOW

Figure 20. Timer Count Operation

LG Semicon

GMS81604/08

8-bit Capture Mode

The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP2 of timer mode register
TM2 for Timer 2) as shown in Figure 21. In this mode,
Timer 1 still operates as an 8-bit timer/counter.

As mentioned above, not only Timer 0 but Timer 2 can
also be used as a capture mode.

In 8-bit capture mode, Timer 1 and Timer 3 are can not
be used as a capture mode.

The Timer/Counter register is incremented in response
internal or external input. This counting function is
same with normal timer mode, but Timer interrupt is
not generated. Timer/Counter still does the above, but
with the added feature that a edge transition at external

input INTx pin causes the current value in the Timer x
register (T0,T2), to be captured into registers CDRx
(CDR0, CDR2), respectively. After captured, Timer
x register is cleared and restarts by hardware.

Caution:
The CDRx and TDRx are in same address.
In the capture mode, reading operation is read the
CDRx, not TDRx because path is opened to the
C D R x .

It has three transition modes: "falling edge", "rising
edge", "both edge" which are selected by interrupt
edge selection register IEDS (Refer to External inter-
rupt section). In addition, the transition at INTx pin
generate an interrupt.

T M 0

CAP0

T1ST

T1SL1 T1SL0

T0ST

T0CN

T0SL1 T0SL0

T0SL[1:0]

XIN PIN

EC0 PIN

T0 (8-BITS)

T0CN

T0ST

MUX

INT0 PIN

CDR0 (8-BITS)

INT0
INTERRUPT

INT0IF

IEDS[1:0]

THIS FIGURE IS A EXAMPLE OF THE TIMER 0.
IN THE TIMER 2, EACH REGISTERS AND FLAGS
MAY BE CHANGED CORRESPONDINGLY.

EDGE DETECTOR

PRESCALER

MSB

LSB

0: Stop
1: Clear and Start

CAPTURE

ADDRESS: E2

RESET VALUE: 00

Figure 21. 8-bit Capture Mode

GMS81604/08

LG Semicon

16-bit Capture Mode

16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits.

T M 0

CAP0

T1ST

T1SL1 T1SL0

T0ST

T0CN

T0SL1 T0SL0

MSB

LSB

T0SL[1:0]

XIN PIN

EC0 PIN

(8-BITS)

T0CN

T0ST

MUX

INT0 PIN

CDR1

(8-BITS)

INT 0
INTERRUPT

INT0IF

IEDS[1:0]

(8-BITS)

CDR0

(8-BITS)

PRESCALER

EDGE DETECTOR

THIS FIGURE IS A EXAMPLE OF USING TIMER 0
AND TIMER 1.
IN THE TIMER 2 AND TIMER 3 EACH
REGISTERS AND FLAGS MAY BE CHANGED.

TIMER 0

TIMER 1

ADDRESS: E2

RESET VALUE: 00

0: Stop
1: Clear and Start

HIGHER

LOWER

DO NOT CARE

Figure 22. 16-bit Capture Mode

LG Semicon

GMS81604/08

A N A L O G T O D I G I T A L C O N V E R T E R

The analog-to-digital converter (A/D) allows conver-
sion of an analog input signal to a corresponding 8-bit
digital value. The A/D module has eight analog inputs,
which are multiplexed into one sample and hold. The
output of the sample and hold is the input into the
converter, which generates the result via successive
approximation. The analog supply voltage is con-
nected to AV

D D

of ladder resistance of A/D module.

The A/D module has two registers which are the con-
trol register ADCM and A/D result register ADR. The
register ADCM, shown in Figure 24, controls the
operation of the A/D converter module. The port pins
can be configured as analog inputs or digital I/O. To
use analog inputs, I/O is selected input mode by R6DD

direction register.

How to Use A/D Converter

The processing of conversion is start when the start bit
ADST is set to "1". After one cycle, it is cleared by
hardware. The register ADR contains the results of the
A/D conversion. When the conversion is completed,
the result is loaded into the ADR, the A/D conversion
status bit ADSF is set to "1", and the A/D interrupt flag
AIF is set. The block diagram of the A/D module is
shown in Figure 23. The A/D status bit ADSF is set
automatically when A/D conversion is completed,
cleared when A/D conversion is in process. The con-
version time takes maximum 40 uS (at f

XIN

=4 MHz).

R61/AN1

LADDER

RESISTOR

DECODER

R60/AN0

R63/AN3

R62/AN2

R65/AN5

R64/AN4

R67/AN7

R66/AN6

SUCCESSIVE

APPROXIMATION

CIRCUIT

ADR

A/D
INTERRUPT

S/H

ADS[2:0]

001

010

011

100

101

110

111

INPUT CHANNEL SELECTION

A/D RESULT REGISTER

ADEN

ADDRESS: E9

RESET VALUE: Undefined

AIF

SAMPLE & HOLD

"0"

"1"

000

Figure 23. A/D Block Diagram

GMS81604/08

LG Semicon

LSB

MSB

ADEN

ADS2

ADS1

ADST

ADS0

ADSF

A D C M

A/D status bit
0: A/D conversion is in process.
1: A/D conversion is completed, not in
process.

A/D start bit
1: Setting this bit starts an A/D conversion.
After one cycle, bit is cleared to "0".
0: Bit force to zero.

Analog channel select
000: channel 0 (R60/AN0)
001: channel 1 (R61/AN1)
010: channel 2 (R62/AN2)
011: channel 3 (R63/AN3)
100: channel 4 (R64/AN4)
101: channel 5 (R65/AN5)
110: channel 6 (R66/AN6)
111: channel 7 (R67/AN7)

A/D converter Enable bit
0: A/D converter module shut off and
consumes no operating current.
1: Enable A/D converter

RESERVED

ADDRESS: E8

RESET VALUE: --00001

R/W

Figure 24. ADCM: A/D Converter Control Register

LG Semicon

GMS81604/08

B U Z Z E R F U N C T I O N

The buzzer driver consists of 6-bit binary counter, the
buzzer register BUR and the clock selector. It gener-
ates square-wave which is very wide range frequency
(250 Hz~125 kHz at f

XIN

=4 MHz) by user program-

mable counter.

Pin R55 is assigned for output port of Buzzer driver by
setting the bit 5 of PMR5 (address D1

) to "1". At this

time, the pin R55 must be defined as output mode (the
bit 5 of R5DD=1)

The bit 0 to 5 of BUR determines output frequency for
buzzer driving.
Frequency calculation is following below.

BUZ

(

)

XIN

Prescaler ratio

B U R

value

BUZ

: Buzzer frequency

XIN

: Min oscillator frequency

Prescaler: Prescaler divide ratio by BUCK1, BUCK0
BUR:Lower 6-bit of BUR. Buzzer period data value

The bits BUCK1, BUCK0 of BUR selects the source
clock from prescaler output.

The 6-bit buzzer counter is cleared and start the count-
ing by writing signal to the register BUR. It is incre-
ment from 00

until it matches 6-bit register BUR.

Caution:
The register BUR contains undefined value after
reset. It must be initialized none 0

~3F

128

COUNTER

(6 BIT)

BUR[5:0]

(6 BIT)

MUX

BUR[7:6]

F/F

PRESCALER

BUR REGISTER

BUZ PIN

Figure 25. Buzzer Driver

LSB

MSB

BU5

BUCK0

BU4

BU3

BU1

BU2

BU0

BUCK1

B U R

ADDRESS: EC

RESET VALUE: Undefined

Buzzer Source Clock Selection
00: fX

01: fX

10: fX

11: fX

128

Buzzer Period Data

Figure 26. BUR: Buzzer Period Data Register

LSB

MSB

BUZS

P M R 5

ADDRESS: D1

RESET VALUE: --0-----

R55/ BUZ Port Selection
0: R55
1: BUZ

Figure 27. PMR5: Port 5 Mode Register

GMS81604/08

LG Semicon

I N T E R R U P T S

The GMS81604/08 interrupt circuits consist of Inter-
rupt enable register (IENH, IENL), Interrupt request
flags of IRQH, IRQL, priority circuit and Master en-
able flag(I flag of PSW). The configuration of interrupt
circuit is shown in Figure 28.

12 interrupt sources are provided including the Reset.

Interrupt source

Symbol

Priority

Hardware RESET
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
AD Converter
Watch dog timer
Basic interval timer

RST

INT0IF
INT1IF
INT2IF
INT3IF

T0IF
T1IF
T2IF
T3IF

AIF

WDTIF

BITIF

1
2
3
4
5
6
7
8
9

10
11
12

*Vector addresses are shown in Program Memory
section.

The External Interrupts INT0~INT3 can each be tran-
sition-activated, depending on interrupt edge selection
register.

The Timer 0~Timer 3 Interrupts are generated by T0IF
~T3IF, which are set by a match in their respective
timer/counter register.
The AD converter Interrupt is generated by AIF which
is set by finishing the analog to digital conversion.
The Watch dog timer Interrupt is generated by WDTIF
which set by a match in Watch dog timer register.
The Basic Interval Timer Interrupt is generated by
BITIF which are set by a overflow in the timer/counter
register.

The interrupts are controlled by the interrupt master
enable flag I-flag (bit 2 of PSW), the interrupt enable
register (IENH, IENL) and the interrupt request flags
(in IRQH, IRQL) except Power-on reset and software
BRK interrupt.

Interrupt enable registers are shown in Figure 29.
These registers are composed of interrupt enable flags
of each interrupt source, these flags determines

INT0IF

INT1IF

INT2IF

INT3IF

T0IF

T1IF

T2IF

T3IF

AIF

WDTIF

BITIF

PRIORITY

CONTROL

INT2

RESET

BRK (Software Interrupt)

I-FLAG

I-flag is in PSW, it is cleared by "DI", set by "EI"
instruction.
When it goes interrupt service, I-flag is cleared by
hardware, thus any other interrupt are inhibited.
When interrupt service is completed by "RETI"
instruction, I-flag is set to "1" by hardware.

IENH

IENL

IRQH

IRQL

INT1

INT0

INT3

TIMER 0

TIMER 1

TIMER 2

TIMER 3

ADC

WDT

BASIC INTERVAL
TIMER

TO CPU

MSB

LSB

BIT 7

BIT 6

BIT 5

RELEASE THE STOP
(IF IN STOP MODE)

Master Enable Flag

0
1

Figure 28. Block Diagram of Interrupt Function

LG Semicon

GMS81604/08

whether an interrupt will be accepted or not. When
enable flag is "0", a corresponding interrupt source is
prohibited. Note that PSW contains also a master en-
able bit, I-flag, which disables all interrupts at once.

When an interrupt is responded to, the I-flag is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is vectored to. Once
in the interrupt service routine the source(s) of the
interrupt can be determined by polling the interrupt
flag bits.

The interrupt flag bit(s) must be cleared in software
before reenabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read
and write.

External Interrupt

External interrupt on INT0~INT3 pins are edge trig-
gered depending the edge selection register IEDS.

The edge detection of external interrupt has three
transition activated mode: rising edge, falling edge,
both edge. INT0~INT3 are multiplexed with general
I/O ports (R40~R43). To use external interrupt pin, set

bit 0 to bit 3 of the port mode register PMR4.

The PMR4 and IEDS registers are shown in Figure
32.

MSB

LSB

MSB

INT2E

INT1E

INT3E

T0E

T2E

T1E

T3E

INT0E

IENH

Enables or disables the interrupt individually.
If flag is cleared, the interrupt is disabled.
0: Disable
1: Enable

BITE

WDTE

IENL

ADDRESS: F6

RESET VALUE: 00

ADDRESS: F4

RESET VALUE: 000-----

Figure 29. IENH, IENL: Interrupt Enable Registers

INT0

INT1

INT2

INT3

INT0 INTERRUPT

INT1 INTERRUPT

INT2 INTERRUPT

INT3 INTERRUPT

IEDS[1:0]

IEDS[5:4]

IEDS[7:6]

IEDS[3:2]

EDGE DETECTOR

INT0IF

INT1IF

INT2IF

INT3IF

Figure 30. External Interrupt

GMS81604/08

LG Semicon

INTERRUPT
ACTIVE

XIN

8 f

OSC

MAX. 13 f

OSC

INSTRUCTION EXECUTION

(INTERRUPT HOLDING)

INTERRUPT

PROCESSING

INTERRUPT

ROUTINE

Figure 31. INT Pin Interrupt Timing

Relation with Timer/Counter Function

T3S

0: R47
1: T3O (TIMER/COUNTER 3 OUTPUT)

INT3S

0: R43
1: INT3 (EXTERNAL INTERRUPT 3)

T1S

0: R46
1: T1O (TIMER/COUNTER 1 OUTPUT)

INT2S

0: R42
1: INT2 (EXTERNAL INTERRUPT 2)

EC2S

0: R45
1: EC2 (EXTERNAL INPUT PIN FOR
TIMER/COUNTER 2

INT1S

0: R41
1: INT1 (EXTERNAL INTERRUPT 1)

EC0S

0: R44
1: EC0 (EXTERNAL INPUT PIN FOR
TIMER/COUNTER 0

INT0S

0: R40
1: INT0 (EXTERNAL INTERRUPT 0)

LSB

MSB

EC2S

T1S

EC0S

INT3S

INT1S

INT2S

INT0S

T3S

P M R 4

Relation with External Interrupt function

LSB

MSB

IED2H

IED3L

IED2L IED1H

IED0H

IED1L

IED0L

IED3H

IEDS

ADDRESS: D0

RESET VALUE: 00

ADDRESS: F8

RESET VALUE: 00

INT3

INT2

INT1

INT0

Edge selection register
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)

Figure 32. PMR4 and IEDS Registers

LG Semicon

GMS81604/08

BRK Interrupt

Software interrupt can be invoked by BRK instruction,
which is the lowest priority order.

Interrupt vector address of BRK is shared with the
vector of TCALL0 (Refer to Program Memory Sec-
tion). When BRK interrupt is generated, B-flag of
PSW is set to distinguish BRK from TCALL0.

Each processing step is determined by B-flag as shown
below.

Multiple Interrupt

If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are
received simultaneously, an internal polling sequence
determines by hardware which request is serviced.
Hardware interrupt priority is shown in Page37.

However, multiple processing through software for
special features is possible. Generally when an inter-
rupt is accepted, the I-flag is cleared to disable any
further interrupt. But as user set I-flag in interrupt
routine, some further interrupt can be serviced even if
certain interrupt is in progress.

B-FLAG

RETI

BRK or

TCALL0

BRK

INTERRUPT

ROUTINE

TCALL0

ROUTINE

RET

= 0

= 1

Figure 33. Execution of BRK/ TCALL0

MOV IENH,#80H

MOV IENL,#00H

RETI

Occur
TIMER 0 INTERRUPT

INT0

ROUTINE

RETI

MAIN

ROUTINE

T I M E R 0

ROUTINE

MOV IENH,#FFH

MOV IENL,#FFH

INT 0

ROUTINE

In this example, the INT0 interrupt can be serviced without any
pending, even TIMER 0 is in progress.
Because of re-setting the interrupt enable registers IENH, IENL
and master enable flag "EI" in the Timer/Counter 0 routine.

Figure 34. Execution of Multi-Interrupt

GMS81604/08

LG Semicon

W A T C H D O G T I M E R

The purpose of the watchdog timer is to detect the
malfunction (runaway) of program due to external
noise or other causes and return the operation to the
normal condition.

The watchdog timer consists of 6-bit binary counter,
6-bit comparator and the watchdog timer data register.
When the value of 6-bit binary counter is equal to the
lower 6 bits of WDTR, the match is generated to go to
reset the CPU.

The 6-bit binary counter is cleared by WDTCL=1.

Caution:
Because the watchdog timer counter is enabled af-
ter clearing Basic Interval Timer .
After the bit WDTON set to "1", maximum error of
timer is depend on prescaler ratio of Basic Interval
Timer.

This watchdog timer can also be used as a simple 6-bit
timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer.
Interval equation is as below.

WDT

WDTR

Interval of BIT

WDTR[5:0]

(6-BITS)

WATCH-DOG TIMER
INTERRUPT

COUNT SOURCE

WATCHDOG

COUNTER

(6-BITS)

WDTON

COMPARATOR

CLEAR

BASIC INTERVAL TIMER
OVERFLOW

WDTCL

NOTE:
The bit WDTON is in register CKCTLR. See Figure 12.

WDTIF

TO RESET CPU

"0"

"1"

WATCHDOG TIMER

Figure 35. Block Diagram of Watch-dog Timer

LSB

MSB

W D T C L

W D T R

ADDRESS: EC

RESET VALUE: Undefined

W D T C L
0: Free-run Watch-dog Timer
1: WDTCL is set to "1", Counter is cleared. WDTCL becomes "0"
automatically after one machine cycle, and Counter starts counting.

6-bit Watch-dog count register

Reserved

Figure 36. WDTR: Watch-dog Timer Data Register

LG Semicon

GMS81604/08

S T O P M O D E

For applications where power consumption is a critical
factor, device provides reduced power of STOP.

An instruction that STOP causes that to be the last
instruction executed before going into the Stop mode.
In the Stop mode, the on-chip oscillator is stopped.
With the clock frozen, all functions are stopped, but
the on-chip RAM and Control registers are held. The
port pins out the values held by their respective port
data register Rx, port direction register RxDD. The
status of peripherals during Stop mode is shown below.

Peripheral

Status

RAM

Retain

Control registers

Retain

I/O

Retain

Oscillation

Stop

Low

OUT

High

In the Stop mode of operation, V

D D

can be reduced to

minimize power consumption. Care must be taken,
however, to ensure that V

D D

is not reduced before the

Stop mode is invoked, and that V

D D

is restored to its

normal operating level, before the Stop mode is termi-
nated. The reset should not be activated before V

D D

restored to its normal operating level, and must be held
active long enough to allow the oscillator to restart and
stabilize (minimum 20 msec).

Caution:
The NOP instruction have to be written more than
two to next line of the STOP instruction.
Ex)

S T O P
N O P
N O P

Release Stop Mode

The exit from Stop mode is hardware reset or external
interrupt. Reset redefines all the Control registers but
does not change the on-chip RAM. External interrupts
allow both on-chip RAM and Control registers to
retain their values.

If I-flag = 1, the normal interrupt response takes place.
If I-flag = 0, the chip will resume execution starting
with the instruction following the STOP instruction. It
will not vector to interrupt service routine.

When exit from Stop mode by external interrupt from
Stop mode, enough oscillation stabilization time is
required to normal operation. Figure 37 shows the
timing diagram. When release the Stop mode, the

EXTERNAL

INTERRUPT

INTERNAL

CLOCK

OSCILLATOR

> 20 ms

NORMAL OPERATION

BASIC INTERVAL
TIMER COUNTER

CLEAR BASIC
INTERVAL TIMER

N+2

N+1

STABILIZATION

TIME

NORMAL OPERATION

STOP MODE

STOP INSTRUCTION
EXECUTION

Figure 37. Timing of Stop Release by External Interrupt

GMS81604/08

LG Semicon

Basic interval timer is activated on wake-up. It is
incremented from 00

until FF

then 00

. The count

overflow is set to start normal operation. Therefore,
before STOP instruction, user must be set its relevant
prescaler divide ratio to have long enough time (more
than 20msec). This guarantees that crystal oscillator
has started and stabilized.

By reset, exit from Stop mode is shown in Figure 38.

M inimizing Current Consumption in
Stop Mode

The Stop mode is designed to reduce power consump-
tion. To minimize current drawn during Stop mode,
the user should turn-off output drivers that are sourcing
or sinking current, if it is practical. Weak pull-ups on
port pins should be turned off, if possible. All inputs
should be either as V

or at V

D D

(or as close to rail as

possible). An intermediate voltage on an input pin
causes the input buffer to draw a significant amount of
current.

Wake-up and Reset Function Table

Event

Chip Status

before event

Chip function after event

P C

Oscillator

Circuit

RESET

Do not care

Vector

STOP instruction

Normal operation

N+1

off

External Interrupt

Normal operation

Vector

External Interrupt Wake-up

Stop, I-flag = 1
Stop, I-flag = 0

Vector

N+1

on
on

PC: Program Counter contents after the event.
N: Address of STOP instruction.

STOP MODE

RESET

INTERNAL

CLOCK

OSCILLATOR

STOP INSTRUCTION
EXECUTION

= 64 ms

at 8 MHz

STABILIZATION TIME

Time can not be control by software.

Figure 38. Timing of Stop Mode Release by Reset

LG Semicon

GMS81604/08

R E S E T

The reset input is the RESET pin, which is the input to
a Schmitt Trigger. A reset in accomplished by holding
the RESET pin low for at least 8 oscillator periods,
while the oscillator running. After reset, 64ms (at 8
MHz) plus 7 oscillator periods are required to start
execution as shown in Figure 40.

Internal RAM is not affected by reset. When V

D D

turned on, the RAM content is indeterminate. Initial
state of each register is as follow. Therefore, this RAM
should be initialized before reading or testing it.

Register

Content

A
X
Y
P S W
P C
SP

X
X
X

00H

X
X

R0
R0DD
R1
R1DD
R4
R4DD
R5
R5DD
R6
R6DD
PMR4
PMR5

00000000

--0---00

00000000
00000000
--0-----

BITR
CKCTLR
WDTR
TM0
TM2
TDR0/ T0/ CDR0
TDR1/ T1/ CDR1
TDR2/ T2/ CDR2
TDR3/ T3/ CDR3

00H

--010111
-0111111

00H
00H

X
X
X
X

ADCM
ADR
BUR
PFDR

--000001

X
X

-----100

IENH
IENL
IRQH
IRQL
IEDS

00H

000-----

00H

000-----

00H

- = unimplemented bit
X= unknown

RESET

+5V

4.2V RESET IC

7042

10K

10uF

4.2V RESET IC

EX) 5V OPERATION

Figure 39. Example of Reset circuit

RESET

OSCILLATOR

FFFE FFFF

Start

RESET PROCESS STEP

ADDRESS BUS

DATA BUS

ADL

ADH

OP Code

MAIN PROGRAM

= 64 ms

at 8 MHz

STABILIZATION TIME

Figure 40. Timing Diagram after Reset

GMS81604/08

LG Semicon

P O W E R F A I L P R O C E S S O R

The GMS81604/08 have on-chip power fail detection
circuitry to immunize against power noise. A configu-
ration register, PFDR, can enable (if clear/pro-
grammed) or disable (if set) the Power-fail Detect
circuitry. If V

D D

falls below 3.0~4.0V range for longer

than 100 ns, the Power fail situation may reset MCU
according to PFR bit of PFDR.

Caution:
Power fail processor function is not available on
3V operation, because this function will detect
power fail all the time.

As below PFDR register is not implemented on the
in-circuit emulator, user can not experiment with it.
Therefore, after final development of user program,
this function may be experimented.

R/W

MSB

PFR

PFD

PFS

P F D R

ADDRESS: ED

RESET VALUE: -----100

Power Fail Status
0: Normal operate
1: This bit force to "1" when Power fail was
detected.

Reserved

Operation Mode
0: Normal operation regardless of power fail.
1: MCU will be reset during power fail.

Disable flag
0: Power fail detection enable
1: Power fail detection disable

R/W

LSB

Figure 41. PFDR: Power Fail Detector Register

RESET VECTOR

PFS = 1 ?

RAM CLEAR

INITIALIZE RAM DATA

YES

FUNCTION

EXECUTION

INITIALIZE ALL PORTS

INITIALIZE REGISTERS

Skip the initial routine.

PFS = 0

Figure 42. Example S/W of Reset flow by Power Fail

LG Semicon

GMS81604/08

OSCILLATOR CIRCUIT

and X

O U T

are the input and output, respectively,

of a inverting amplifier which can be configured for
use as an on-chip oscillator, as shown in Figure 44.

To drive the device from an external clock source,
X

OUT

should be left unconnected while X

is driven

as shown in Figure 45. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must be
observed.

Oscillation circuit is designed to be used either with a
ceramic resonator or crystal oscillator. Since each crys-
tal and ceramic resonator have their own charac-
t e r i s t i c s , t h e u s e r s h o u l d c o n s u l t t h e c r y s t a l
manufacturer for appropriate values of external com-
ponents.

In addition, see Figure 46. for the layout of the crystal.
In all cases, an external clock operation is available.

OUT

Recommend:
C1,C2 = 30 pF

10 pF for Crystals.

Figure 44. Oscillator Connections

OUT

N/C

EXTERNAL
OSCILLATOR
SIGNAL

Figure 45. External Clock Drive

Configuration

OUT

RESET

R00

R01

Figure 46. Layout of Crystal

LG Semicon

GMS81604/08

U N U S E D P O R T S

All unused ports should be set properly that current
flow through the port does not exist.

First conseider the setting to input mode. Be sure that
there is no current flow after considering its relation-
ship with external circuit. In input mode, the pin im-
pedance viewing from external MCU is very high that
the current does not flow.

But input voltage level should be V

or V

D D

. Be

careful that if unspecified voltage, i.e. if unfirmed

voltage level is applied to input pin, there can be little
current ( max. 1mA at around 2V) flow.

If it is not appropriate to set to input mode, then set to
output mode considering there is no current flow.
Setting to High or Low is decided considering its
relationship with external circuit. For example, if there
is external pull-up resistor then it is set to output mode,
i.e. to High, and if there is external pull-down register,
it is set to low.

GMS81604/08

LG Semicon

G M S 8 1 6 0 8 T ( O T P ) P R O G R A M M I N G

The GMS81608T is one-time PROM (OTP) micro-
controller with 8K bytes electrically programmable
read only memory for the GMS81604/08 system
evaluation, first production and fast mass production.

The programming to the OTP device, user can have
two way. One is using the universal programmer which
is support LGS microcontrollers, other is using the
general EPROM programmer.

1. Using the Universal programmer

Third party universal programmer support to program
the GMS81608T microcontrollers and lists are shown
as below.

Manufacturer: Advantech

Web site: http://www.aec.com.tw

Programmer: LabTool-48

Manufacturer: Hi-Lo systems

Web site: http://www.hilosystems.com.tw

Programmer: ALL-11, GANG-08

Socket adapters are supported by third party program-
mer manufacturer.

2. Using the general EPROM(27C256)
programmer

The programming algorithm is simmilar with the stan-
dart EPROM 27C256. It give some convience that user
can use standard EPROM programmer. Make sure
that 1ms programming pulse must be used, it gener-
ally called "Intelligent Mode". Do not use 100us
programming pulse mode, "Quick Pulse Mode".

When user use general EPROM programmer, socket
adaper is essencially required. It convert pin to fit the
pin of general 27C256 EPROM.

Three type socket adapters are provided according to
package variation as below table.

Socket Adapter

Package Type

OA816A-40SD

40 pin DIP

OA816A-42SD

42 pin SDIP

OA816A-42PL

44 pin PLCC

W ith these socket adapters, the GMS81608T can easy
be programming and verifying using 27C256 EPROM
mode on general-purpose PROM programmer.

In assembler and file type, two files are generated after
compiling. One is "*.HEX", another is "*.OTP". The
"*.HEX" file is used for emulation in circuit emulator
(CHOICE-Dr

T M

or CHOICE-Jr

) and "*.OTP" file

is used for programming to the OTP device.

Programming Procedure

1. Select the EPROM device and manufacturer on
EPROM programmer (Intel 27C256).

2. Select the programming algorithm as an Intelligent
mode (apply 1ms writing pulse), not a Quick pulse
mode.

3. Load the file (*.OTP) to the programmer.

4. Set the programming address range as below table.

Address

Set Value

Buffer start address

6000

Buffer end address

7FFF

Device start address

6000

5. Mount the socket adapter with the GMS81608T on
the PROM programmer.

6. Start the PROM programmer to programming/
verifying.

LG Semicon

GMS81604/08

Pin No. M C U M o d e O T P M o d e

TEST I V

2 AV

D D

- (1) -

3 R67/AN7 I/O (1) -

4 R66/AN6 I/O (1) -

5 R65/AN5 I/O (1) -

6 R64/AN4 I/O (1) -

7 R63/AN3 I (1) -

8 R62/AN2 I (1) -

9 R61/AN1 I (1) -

10 R60/AN0 I (1) -

11 R47/T3O I/O A4 I

12 R46/T1O I/O (1) -

13 R45/EC2 I/O

CE I

14 R44/EC0 I/O

OE I

15 R43/INT3 I/O A3 I

16 R42/INT2 I/O A2 I

17 R41/INT1 I/O A1 I

18 R40/INT0 I/O A0 I

19 R55/BUZ I/O (1) -

20 V

D D

- V

D D

NOTES:

(1) Pins must be connected to VSS, because these
pins are input ports during programming, program verify
and reading
(2) Pins must be connected to VDD.
(3) XOUT pin must be opened during programming.

Pin No. M C U M o d e O T P M o d e

21 R17 I/O A12 I

22 R16 I/O A11

23 R15 I/O A10 I

24 R14 I/O A9 I

25 R13 I/O A8 I

26 R12 I/O A7 I

27 R11 I/O A6 I

28 R10 I/O A5 I

29 R07 I/O O7 O

30 R06 I/O O6 O

31 R05 I/O O5 O

32 R04 I/O O4 O

33 R03 I/O O3 O

34 R02 I/O O2 O

35 R01 I/O O1 O

36 R00 I/O O0 O

RESET I (1) -

38 X

O U T

O (3) -

39 X

I (1) -

40 V

- (1) -

I/O: Input/Output Pin
I: Input Pin
O: Output Pin

40DIP Package for GMS81608T

LG Semicon GMS81608T PROGRAMMING SPECIFICATION

Pin No. M C U M o d e O T P M o d e

TEST I V

2 AV

D D

- (1) -

3 R67/AN7 I/O (1) -

4 R66/AN6 I/O (1) -

5 R65/AN5 I/O (1) -

6 R64/AN4 I/O (1) -

7 R63/AN3 I (1) -

8 R62/AN2 I (1) -

9 R61/AN1 I (1) -

10 R60/AN0 I (1) -

11 R47/T3O I/O A4 I

12 R46/T1O I/O (1) -

13 R45/EC2 I/O

CE I

14 R44/EC0 I/O

OE I

15 R43/INT3 I/O A3 I

16 R42/INT2 I/O A2 I

17 R41/INT1 I/O A1 I

18 R40/INT0 I/O A0 I

19 R55/BUZ I/O (1) -

20 V

D D

- V

D D

21 R51 I/O (2) -

NOTES:

(1) Pins must be connected to VSS, because these
pins are input ports during programming, program verify
and reading
(2) Pins must be connected to VDD.
(3) XOUT pin must be opened during programming.

Pin No. M C U M o d e O T P M o d e

22 R50 I/O (2) -

23 R17 I/O A12 I

24 R16 I/O A11

25 R15 I/O A10 I

26 R14 I/O A9 I

27 R13 I/O A8 I

28 R12 I/O A7 I

29 R11 I/O A6 I

30 R10 I/O A5 I

31 R07 I/O O7 O

32 R06 I/O O6 O

33 R05 I/O O5 O

34 R04 I/O O4 O

35 R03 I/O O3 O

36 R02 I/O O2 O

37 R01 I/O O1 O

38 R00 I/O O0 O

RESET I (1) -

40 X

O U T

O (3) -

41 X

I (1) -

42 V

- (1) -

I/O: Input/Output Pin
I: Input Pin
O: Output Pin

42SDIP Package for GMS81608T

GMS81608T PROGRAMMING SPECIFICATION LG Semicon

Pin No. M C U M o d e O T P M o d e

1 N.C. - N.C. -

TEST I V

3 AV

D D

- (1) -

4 R67/AN7 I/O (1) -

5 R66/AN6 I/O (1) -

6 R65/AN5 I/O (1) -

7 R64/AN4 I/O (1) -

8 R63/AN3 I (1) -

9 R62/AN2 I (1) -

10 R61/AN1 I (1) -

11 R60/AN0 I (1) -

12 R47/T3O I/O A4 I

13 R46/T1O I/O (1) -

14 R45/EC2 I/O

CE I

15 R44/EC0 I/O

OE I

16 R43/INT3 I/O A3 I

17 N.C. - N.C. -

18 R42/INT2 I/O A2 I

19 R41/INT1 I/O A1 I

20 R40/INT0 I/O A0 I

21 R55/BUZ I/O (1) -

22 V

D D

- V

D D

NOTES:

(1) Pins must be connected to VSS, because these
pins are input ports during programming, program verify
and reading
(2) Pins must be connected to VDD.
(3) XOUT pin must be opened during programming.

Pin No. M C U M o d e O T P M o d e

23 R51 I/O (2) -

24 R50 I/O (2) -

25 R17 I/O A12 I

26 R16 I/O A11

27 R15 I/O A10 I

28 R14 I/O A9 I

29 R13 I/O A8 I

30 R12 I/O A7 I

31 R11 I/O A6 I

32 R10 I/O A5 I

33 R07 I/O O7 O

34 R06 I/O O6 O

35 R05 I/O O5 O

36 R04 I/O O4 O

37 R03 I/O O3 O

38 R02 I/O O2 O

39 R01 I/O O1 O

40 R00 I/O O0 O

RESET I (1) -

42 X

O U T

O (3) -

43 X

I (1) -

44 V

- (1) -

I/O: Input/Output Pin
I: Input Pin
O: Output Pin

44PLCC Package for GMS81608T

LG Semicon GMS81608T PROGRAMMING SPECIFICATION

PIN FUNCTION (OTP Mode)

(Program Voltage)

is the input for the program voltage for programming the EPROM.

CE ( Chip Enable)

CE is the input for programming and verifying internal EPROM.

OE (Output Enable)

OE is the input of data output control signal for verify.

(Address Bus)

are address input pins for internal EPROM.

(EPROM Data Bus)

These are data bus for internal EPROM.

P R O G R A M M I N G

The GMS81608T has address A

pins. Therefore, the programmer just program 8K bytes data of addresses

6000

to 7FFF

into the GMS81608T OTP device. During the programming addresses A

, A

programmer must be pulled to a logic high.
When the programmer write the data from 6000

to 7FFF

, consequently, the data actually will be written into

addresses E000

to FFFF

of the OTP device.

Programming Flow

1. The data format to be programmed is made up of Motorola S1 format.

Ex) "Motorola S1" format;
S00B00005741544348363038DF
S1246000E1FF3BFF04A13F8F06E1C1711BFF3F1B003E1B00371B00361BFF3D1B003C1BFF3385
S12460211BFF321BFF351B92131B7FCC1BF3D61B17FD1BFCFC1B821B1BE01D1B8E191BFD18B1
:
:
S1057FF2941FD6
S1057FFEFF1F5F
S9030000FC

2. Down load above data into programmer from PC.

3. Programming the data from address 6000

to 7FFF

into the OTP MCU, the data must be turned over

respectively, and then record the data into the OTP device. When read the data, it also must be turned over.
Ex) 00(00000000)

FF(11111111), 76(01110110)

89(10001001), FF

(11111111)

00(00000000) etc.

4. Of course, the check sum is result of the sum of whole data from address 6000

to 7FFF

in the file (not reverse

data of the OTP MCU).

* When GMS81608T shipped, the blank data of GMS81608T is initially 00

(not FF

GMS81608T PROGRAMMING SPECIFICATION LG Semicon

Address

GMS81608T device

File

xxxxxxxx.OTP

E1
FF
3B
FF
04
A1
3F
8F
:
:
:
:
94
1F
:
FF
1F

Down

Program

6000

6001

6002

6003

6004

6005

6006

6007

:
:
:
:
7FF2

7FF3

:
7FFE

7FFF

E1
FF
3B
FF
04
A1
3F
8F
:
:
:
:
94
1F
:
FF
1F

6000

6001

6002

6003

6004

6005

6006

6007

:
:
:
:
7FF2

7FF3

:
7FFE

7FFF

1E
00
C4
00
FC
5E
C0
70
:
:
:
:
6A
E0
:
00
E0

E000

E001

E002

E003

E004

E005

E006

E007

:
:
:
:
FFF2

FFF3

:
FFFE

FFFF

Reading

Verify

Data

Address

Data Address

Data

Programmer

Buffer

Checksum = E1+FF+3B+FF+04+A1+3F+8F+

+ 94+1F+

+FF+1F

Programming Example

Program

area

8 K B Y T E S

E000

FFFF

Address

File Type:

Motorola

S-format

G M S 8 1 6 0 8 T

6000

7FFF

Address

xxxxxxxx.OTP

Universal

Programmer

Down

Program

Verify

Reading

Buffer Start Address: 6000

Buffer End Address: 7FFF

Device Start Address: E000

Programming Flow

LG Semicon GMS81608T PROGRAMMING SPECIFICATION

D E V I C E O P E R A T I O N M O D E

= 25

M o d e

C E

O E A 0~A15 VPP V D D O 0~O7

Read X X V

D D

5.0V D

O U T

Output Disable V

X V

D D

5.0V Hi-Z

Programming V

X V

D D

Program Verify X X V

D D

O U T

NOTES:
1. X = Either VIL or VIH
3. See DC Characteristics Table for VDD and VPP voltages during programming.

D C C H A R A C T E R I S T I C S

=0 V, T

= 25

Symbol Item Min Typ M a x Unit Test condition

supply voltage 12.0 - 13.0 V

D D (1)

D D

supply voltage 5.75 - 6.25 V

PP (2)

supply current 50 mA

CE=V

D D (2)

D D

supply current 30 mA

Input high voltage 0.8 V

D D

Input low voltage 0.2 V

D D

Output high voltage V

D D

-1.0 V I

O H

= -2.5 mA

Output low voltage 0.4 V I

= 2.1 mA

Input leakage current 5 uA

NOTES:

1. VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. The maximum current value is with outputs O0 to O7 unloaded.

GMS81608T PROGRAMMING SPECIFICATION LG Semicon

NOTES:
1. The input timing reference level is 1.0 V for a VIL and 4.0V for a VIH at VDD=5.0V
2. To read the output data, transition requires on the O E from the high to the low after address setup time tAS.

Address Valid

O E

Valid Output

D H

Addresses

Output

High-Z

VIH

VIL

VIH

VIL

VIH

VIL

(2)

READING WAVEFORMS

W A V E F O R M INPUTS O U T P U T S

Must be steady

May change
from H to L

May change
from L to H

Do not care any
change permitted

Does not apply

W ill be steady

W ill be changing
from H to L

W ill be changing
from L to H

Changing state
unknown

Center line is
high impedance
"Off" state

SWITCHING WAVEFORMS

LG Semicon GMS81608T PROGRAMMING SPECIFICATION

A C R E A D I N G C H A R A C T E R I S T I C S

=0 V, T

= 25

Symbol Item Min Typ M a x Unit Test condition

Address setup time 2 us

O E

Data output delay time 200 ns

D H

Data hold time 0 ns

NOTES:

1. VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.

A C P R O G R A M M I N G C H A R A C T E R I S T I C S

=0 V, T

= 25

C; See DC Characteristics Table for V

D D

and V

voltages.)

Symbol Item Min Typ Max Unit

Condition*

(Note 1)

Address set-up time 2 us

OES

OE set-up time 2 us

Data setup time 2 us

Address hold time 0 us

D H

Data hold time 1 us

DFP

Output disable delay time 0 us

VPS

setup time 2 us

V D S

D D

setup time 2 us

P W

Program pulse width 0.95 1.0 1.05 ms

O P W

CE pulse width when over
programming

2.85 78.75 ms (Note 2)

O E

Data output delay time 200 ns

*AC CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) . . . . 20 ns
Input Pulse Levels . . . . . . . . . . . . . . . 0.45V to 4.55V
Input Timing Reference Level . . . . . . . . . 1.0V to 4.0V
Output Timing Reference Level . . . . . . . . 1.0V to 4.0V

NOTES:

1. VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X
(Intelligent Programming Algorithm).Refer to flow chart of page 13.

LG Semicon GMS81608T PROGRAMMING SPECIFICATION

GMS800 Series

A. INSTRUCTION

A.1 Terminology List

Terminology

Description

Accumulator

X - register

Y - register

PSW

Program Status Word

#imm

8-bit Immediate data

Direct Page Offset Address

!abs

Absolute Address

[ ]

Indirect expression

{ }

{ }+

.bit

Bit Position

A.bit

Bit Position of Accumulator

dp.bit

Bit Position of Direct Page Memory

M.bit

Bit Position of Memory Data (000

~0FFF

)

rel

Relative Addressing Data

upage

U-page (0FF00

~0FFFF

) Offset Address

Table CALL Number (0~15)

Addition

Upper Nibble Expression in Opcode

Subtraction

Multiplication

Division

( )

Contents Expression

AND

Exclusive OR

NOT

Assignment / Transfer / Shift Left

Shift Right

Exchange

Equal

Not Equal

Bit Position

GMS800 Series

A.2 Instruction Map

LOW

HIGH

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

000

SET1
dp.bit

BBS

A.bit,rel

BBS

dp.bit,re

ADC

#imm

ADC

dp+X

ADC

!abs

ASL

TCALL

SETA1

.bit

BIT

POP

PUSH

BRK

001

CLRC

SBC

#imm

SBC

dp+X

SBC

!abs

ROL

TCALL

CLRA1

.bit

COM

POP

PUSH

BRA

rel

010

CLRG

CMP

#imm

CMP

dp+X

CMP

!abs

LSR

TCALL

NOT1

M.bit

TST

POP

PUSH

PCALL

Upage

011

#imm

dp+X

!abs

ROR

TCALL

OR1

OR1B

CMPX

POP

PSW

PUSH

PSW

RET

100

CLRV

AND

#imm

AND

dp+X

AND

!abs

INC

TCALL

AND1

AND1B

CMPY

CBNE

dp+X

TXSP

INC

101

SETC

EOR

#imm

EOR

dp+X

EOR

!abs

DEC

TCALL

EOR1

EOR1B

DBNE

XMA

dp+X

TSPX

DEC

110

SETG

LDA

#imm

LDA

dp+X

LDA
!abs

TXA

LDY

TCALL

LDC

LDCB

LDX

dp+Y

XCN

DAS

111

LDM

dp,#im

STA

dp+X

STA
!abs

TAX

STY

TCALL

STC

M.bit

STX

dp+Y

XAX

STOP

LOW

HIGH

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

000

BPL

rel

CLR1

dp.bit

BBC

A.bit,rel

BBC

dp.bit,rel

ADC

{X}

ADC

!abs+Y

ADC

[dp+X]

ADC

[dp]+Y

ASL
!abs

ASL

dp+X

TCALL

JMP

!abs

BIT

!abs

ADDW

LDX

#imm

JMP

[!abs]

001

BVC

rel

SBC

{X}

SBC

!abs+Y

SBC

[dp+X]

SBC

[dp]+Y

ROL

!abs

ROL

dp+X

TCALL

CALL

!abs

TEST

!abs

SUBW

LDY

#imm

JMP

[dp]

010

BCC

rel

CMP

{X}

CMP

!abs+Y

CMP

[dp+X]

CMP

[dp]+Y

LSR

!abs

LSR

dp+X

TCALL

MUL

TCLR1

!abs

CMPW

CMPX

#imm

CALL

[dp]

011

BNE

rel

{X}

!abs+Y

[dp+X]

[dp]+Y

ROR

!abs

ROR

dp+X

TCALL

DBNE

CMPX

!abs

LDYA

CMPY

#imm

RETI

100

BMI

rel

AND

{X}

AND

!abs+Y

AND

[dp+X]

AND

[dp]+Y

INC

!abs

INC

dp+X

TCALL

DIV

CMPY

!abs

INCW

INC

TAY

101

BVS

rel

EOR

{X}

EOR

!abs+Y

EOR

[dp+X]

EOR

[dp]+Y

DEC

!abs

DEC

dp+X

TCALL

XMA

{X}

XMA

DECW

DEC

TYA

110

BCS

rel

LDA

{X}

LDA

!abs+Y

LDA

[dp+X]

LDA

[dp]+Y

LDY

!abs

LDY

dp+X

TCALL

LDA
{X}+

LDX
!abs

STYA

XAY

DAA

111

BEQ

rel

STA

{X}

STA

!abs+Y

STA

[dp+X]

STA

[dp]+Y

STY

!abs

STY

dp+X

TCALL

STA
{X}+

STX
!abs

CBNE

XYX

NOP

GMS800 Series

iii

A.3 Instruction Set

Arithmetic / Logic Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

ADC #imm

Add with carry.

ADC dp

( A ) + ( M ) + C

ADC dp + X

ADC !abs

NV--H-ZC

ADC !abs + Y

ADC [ dp + X ]

ADC [ dp ] + Y

ADC { X }

AND #imm

Logical AND

AND dp

( A )

( M )

AND dp + X

AND !abs

N-----Z-

AND !abs + Y

AND [ dp + X ]

AND [ dp ] + Y

AND { X }

ASL A

Arithmetic shift left

ASL dp

N-----ZC

ASL dp + X

ASL !abs

CMP #imm

Compare accumulator contents with memory con-
tents
( A ) - ( M )

CMP dp

CMP dp + X

CMP !abs

N-----ZC

CMP !abs + Y

CMP [ dp + X ]

CMP [ dp ] + Y

CMP { X }

CMPX #imm

Compare X contents with memory contents

CMPX dp

( X ) - ( M )

N-----ZC

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

CMPY dp

( Y ) - ( M )

N-----ZC

CMPY !abs

COM dp

1'S Complement : ( dp )

~( dp )

N-----Z-

DAA

Decimal adjust for addition

N-----ZC

DAS

Decimal adjust for subtraction

N-----ZC

DEC A

Decrement

N-----ZC

7 6 5 4 3 2 1 0

"0"

GMS800 Series

DEC dp

( M ) - 1

N-----Z-

DEC dp + X

N-----Z-

DEC !abs

N-----Z-

DEC X

N-----Z-

DEC Y

N-----Z-

DIV

Divide : YA / X Q: A, R: Y

NV--H-Z-

EOR #imm

Exclusive OR

EOR dp

( A )

( M )

EOR dp + X

EOR !abs

N-----Z-

EOR !abs + Y

EOR [ dp + X ]

EOR [ dp ] + Y

EOR { X }

INC A

Increment

N-----ZC

INC dp

( M ) + 1

N-----Z-

INC dp + X

N-----Z-

INC !abs

N-----Z-

INC X

N-----Z-

INC Y

N-----Z-

LSR A

Logical shift right

LSR dp

N-----ZC

LSR dp + X

LSR !abs

MUL

Multiply : YA

N-----Z-

OR #imm

Logical OR

OR dp

( A )

( M )

OR dp + X

OR !abs

N-----Z-

OR !abs + Y

OR [ dp + X ]

OR [ dp ] + Y

OR { X }

ROL A

Rotate left through Carry

ROL dp

N-----ZC

ROL dp + X

ROL !abs

ROR A

Rotate right through Carry

ROR dp

N-----ZC

ROR dp + X

ROR !abs

SBC #imm

Subtract with Carry

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

7 6 5 4 3 2 1 0

"0"

7 6 5 4 3 2 1 0

GMS800 Series

Register / Memory Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

LDA #imm

Load accumulator

LDA dp

( M )

LDA dp + X

LDA !abs

LDA !abs + Y

N-----Z-

LDA [ dp + X ]

LDA [ dp ] + Y

LDA { X }

LDA { X }+

X- register auto-increment : A

( M ) , X

X + 1

LDM dp,#imm

Load memory with immediate data : ( M )

imm

--------

LDX #imm

Load X-register

LDX dp

( M )

N-----Z-

LDX dp + Y

LDX !abs

LDY #imm

Load Y-register

LDY dp

( M )

N-----Z-

LDY dp + X

LDY !abs

STA dp

Store accumulator contents in memory

STA dp + X

( M )

STA !abs

STA !abs + Y

--------

STA [ dp + X ]

STA [ dp ] + Y

STA { X }

STA { X }+

X- register auto-increment : ( M )

A, X

X + 1

STX dp

Store X-register contents in memory

STX dp + Y

( M )

--------

STX !abs

STY dp

Store Y-register contents in memory

STY dp + X

( M )

--------

STY !abs

TAX

Transfer accumulator contents to X-register : X

N-----Z-

TAY

Transfer accumulator contents to Y-register : Y

N-----Z-

TSPX

Transfer stack-pointer contents to X-register : X

N-----Z-

TXA

Transfer X-register contents to accumulator: A

N-----Z-

TXSP

Transfer X-register contents to stack-pointer: sp

N-----Z-

TYA

Transfer Y-register contents to accumulator: A

N-----Z-

XAX

Exchange X-register contents with accumulator :X

--------

GMS800 Series

vii

16-BIT operation

Bit Manipulation

XAY

Exchange Y-register contents with accumulator :Y

--------

XMA dp

Exchange memory contents with accumulator

XMA dp+X

( M )

N-----Z-

XMA {X}

XYX

Exchange X-register contents with Y-register : X

--------

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

ADDW dp

16-Bits add without Carry
YA

( YA ) ( dp +1 ) ( dp )

NV--H-ZC

CMPW dp

Compare YA contents with memory pair contents :
(YA)

(dp+1)(dp)

N-----ZC

DECW dp

Decrement memory pair
( dp+1)( dp)

( dp+1) ( dp) - 1

N-----Z-

INCW dp

Increment memory pair
( dp+1) ( dp)

( dp+1) ( dp ) + 1

N-----Z-

LDYA dp

Load YA
YA

( dp +1 ) ( dp )

N-----Z-

STYA dp

Store YA
( dp +1 ) ( dp )

--------

SUBW dp

16-Bits subtract without carry
YA

( YA ) - ( dp +1) ( dp)

NV--H-ZC

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

AND1 M.bit

Bit AND C-flag : C

( C )

( M .bit )

-------C

AND1B M.bit

Bit AND C-flag and NOT : C

( C )

~( M .bit )

-------C

BIT dp

Bit test A with memory :

MM----Z-

BIT !abs

( A )

( M ) , N

( M

) , V

( M

)

CLR1 dp.bit

Clear bit : ( M.bit )

"0"

--------

CLRA1 A.bit

Clear A bit : ( A.bit )

"0"

--------

CLRC

Clear C-flag : C

"0"

-------0

CLRG

Clear G-flag : G

"0"

--0-----

CLRV

Clear V-flag : V

"0"

-0--0---

EOR1 M.bit

Bit exclusive-OR C-flag : C

( C )

( M .bit )

-------C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

( C )

~(M .bit)

-------C

LDC M.bit

Load C-flag : C

( M .bit )

-------C

LDCB M.bit

Load C-flag with NOT : C

~( M .bit )

-------C

NOT1 M.bit

Bit complement : ( M .bit )

~( M .bit )

--------

OR1 M.bit

Bit OR C-flag : C

( C )

( M .bit )

-------C

OR1B M.bit

Bit OR C-flag and NOT : C

( C )

~( M .bit )

-------C

GMS800 Series

Branch / Jump Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

BBC A.bit,rel

4/6

Branch if bit clear :

--------

BBC dp.bit,rel

5/7

if ( bit ) = 0 , then pc

( pc ) + rel

BBS A.bit,rel

4/6

Branch if bit set :

--------

BBS dp.bit,rel

5/7

if ( bit ) = 1 , then pc

( pc ) + rel

BCC rel

2/4

Branch if carry bit clear
if ( C ) = 0 , then pc

( pc ) + rel

--------

BCS rel

2/4

Branch if carry bit set
if ( C ) = 1 , then pc

( pc ) + rel

--------

BEQ rel

2/4

Branch if equal
if ( Z ) = 1 , then pc

( pc ) + rel

--------

BMI rel

2/4

Branch if minus
if ( N ) = 1 , then pc

( pc ) + rel

--------

BNE rel

2/4

Branch if not equal
if ( Z ) = 0 , then pc

( pc ) + rel

--------

BPL rel

2/4

Branch if minus
if ( N ) = 0 , then pc

( pc ) + rel

--------

BRA rel

Branch always
pc

( pc ) + rel

--------

BVC rel

2/4

Branch if overflow bit clear
if (V) = 0 , then pc

( pc) + rel

--------

BVS rel

2/4

Branch if overflow bit set
if (V) = 1 , then pc

( pc ) + rel

--------

CALL !abs

Subroutine call

CALL [dp]

M( sp)

( pc

), sp

sp - 1, M(sp)

(pc

), sp

- 1,
if !abs, pc

abs ; if [dp], pc

( dp ), pc

(

dp+1 ) .

--------

CBNE dp,rel

5/7

Compare and branch if not equal :

--------

CBNE dp+X,rel

6/8

if ( A )

( M ) , then pc

( pc ) + rel.

DBNE dp,rel

5/7

Decrement and branch if not equal :

--------

DBNE Y,rel

4/6

if ( M )

0 , then pc

( pc ) + rel.

JMP !abs

Unconditional jump

JMP [!abs]

jump address

--------

JMP [dp]

PCALL upage

U-page call
M(sp)

( pc

), sp

sp - 1, M(sp)

( pc

sp - 1, pc

( upage ), pc

"0FF

" .

--------

TCALL n

Table call : (sp)

( pc

), sp

sp - 1,

M(sp)

( pc

),sp

sp - 1,

(Table vector L), pc

(Table vector H)

--------

GMS800 Series

Control Operation & Etc.

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

BRK

Software interrupt : B

"1", M(sp)

(pc

), sp

sp-1,

M(s)

(pc

), sp

sp - 1, M(sp)

(PSW), sp

sp -1,
pc

( 0FFDE

) , pc

( 0FFDF

) .

---1-0--

Disable all interrupts : I

"0"

-----0--

Enable all interrupt : I

"1"

-----1--

NOP

No operation

--------

POP A

sp + 1, A

M( sp )

POP X

sp + 1, X

M( sp )

--------

POP Y

sp + 1, Y

M( sp )

POP PSW

sp + 1, PSW

M( sp )

restored

PUSH A

M( sp )

A , sp

sp - 1

PUSH X

M( sp )

X , sp

sp - 1

--------

PUSH Y

M( sp )

Y , sp

sp - 1

PUSH PSW

M( sp )

PSW , sp

sp - 1

RET

Return from subroutine
sp

sp +1, pc

M( sp ), sp

sp +1, pc

sp )

--------

RETI

Return from interrupt
sp

sp +1, PSW

M( sp ), sp

sp + 1,

M( sp ), sp

sp + 1, pc

M( sp )

restored

STOP

Stop mode ( halt CPU, stop oscillator )

--------

MASK ORDER & VERIFICATION SHEET

GMS81604-HC

1. Customer Information

Company Name

2. Device Information

3. Marking Specification

4. Delivery Schedule

Customer Sample

Date

YYYY

Risk Order

YYYY

Quantity

LG Confirmation

Application

Order Date

YYYY

Tel:

Fax:

Name &
Signature:

Package

40DIP

42SDIP

5. ROM Code Verification

Verification D ate:

YYYY

Approval Date:

YYYY

Please confirm our verification data.

I agree w ith your verification data and confirm

you to m ake m ask set.

Check Sum:

Tel:

Fax:

Name &
Signature:

Tel:

Fax:

Name &
Signature:

Set "FF" in

this area

0000H

7000H

7FFFH

ROM (4K)

6FFFH

Mask Data

Hitel

Chollian

Internet

File Name: ( .OTP)

(Please check mark into )

LG Semicon

pcs

Check Sum: ( )

Customer should write inside thick line box.

This box is written after "5.Verification".

LGS

YYW W KO REA

G M S81604 -HC

Custom er's part num ber

44PLCC

MASK ORDER & VERIFICATION SHEET

GMS81608-HC

1. Customer Information

Company Name

2. Device Information

3. Marking Specification

4. Delivery Schedule

Customer Sample

Date

YYYY

Risk Order

YYYY

Quantity

LG Confirmation

Application

Order Date

YYYY

Tel:

Fax:

Name &
Signature:

Package

40DIP

42SDIP

5. ROM Code Verification

Verification D ate:

YYYY

Approval Date:

YYYY

Please confirm our verification data.

I agree w ith your verification data and confirm

you to m ake m ask set.

Check Sum:

Tel:

Fax:

Name &
Signature:

Tel:

Fax:

Name &
Signature:

Set "FF" in

this area

0000H

6000H

7FFFH

ROM (8K)

5FFFH

Mask Data

Hitel

Chollian

Internet

File Name: ( .OTP)

(Please check mark into )

LG Semicon

pcs

Check Sum: ( )

Customer should write inside thick line box.

This box is written after "5.Verification".

LGS

YYW W KO REA

G M S81608 -HC

Custom er's part num ber

44PLCC

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81608TK

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81608TK