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HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

Table of Contents

OVERVIEW.......................................... 1

Description ...................................................1
Features .......................................................1
Development Tools..................................... 2

BLOCK DIAGRAM .............................. 3
PIN ASSIGNMENT .............................. 4
PACKAGE DIAGRAM ......................... 5
PIN FUNCTION .................................... 6
PORT STRUCTURES .......................... 9

RESET ................................................................ 9
TEST ................................................................... 9
XIN, XOUT ........................................................ 9
OSC1, OSC2 ..................................................... 9
R00~07, R53 ...................................................... 9
R10~15 (AN0~5) ................................................ 9
R16, 17, 20, 24, 25, 26, 27, 52, 67 ................... 10
R21/Sclk, R22/Sout .......................................... 10
R23/Sin ............................................................ 10
R40~43 (PWM0~3) .......................................... 10
R44, 45, 46, 47 (SCL, SDA, PWM) .................. 10
R50/BUZZ, R51/PWM8 .................................... 11
R54/YM, R55/YS, R56/I ................................... 11
R, G, B ............................................................. 11

ELECTRICAL CHARACTERISTICS . 12

Absolute Maximum Ratings .....................12
Recommended Operating Conditions ....12
DC Electrical Characteristics - GMS81C4040

.....................................................................12

A/D Comparator Characteristics .............14
AC Characteristics ....................................14
Typical Characteristics ............................16

MEMORY ORGANIZATION .............. 17

Registers ...................................................17
Program Memory ......................................20

PCALL

rel ..................................................... 21

TCALL

n ....................................................... 21

Data Memory .............................................23

User Memory .................................................... 23
Control Registers ............................................. 23
Stack Area ........................................................ 23

Addressing Mode ......................................25

(1) Register Addressing ................................... 25
(2) Immediate Addressing

#imm .................. 25

(3) Direct Page Addressing

dp ..................... 25

(4) Absolute Addressing

!abs ....................... 25

(5) Indexed Addressing .................................... 26
X indexed direct page (no offset)

{X} ........... 26

X indexed direct page, auto increment

{X}+ . 26

X indexed direct page (8 bit offset)

dp+X ..... 26

Y indexed direct page (8 bit offset)

dp+Y ..... 27

Y indexed absolute

!abs+Y .......................... 27

Direct page indirect

[dp] ............................... 27

X indexed indirect

[dp+X] ............................. 27

Y indexed indirect

[dp]+Y ............................. 28

Absolute indirect

[!abs] ................................ 28

I/O PORTS ......................................... 29

Registers for Port ..................................... 29

Port Data Registers .......................................... 29

I/O Ports Configuration ............................ 30

R0 Ports ........................................................... 30
R1 Ports ........................................................... 30
R2 Port ............................................................. 31
R4 Port ............................................................. 31
R5 Port ............................................................. 32
R6 Port ............................................................. 32

CLOCK GENERATOR ...................... 33
TIMER ................................................ 34

Basic Interval Timer ................................. 34
Timer 0, 1 ................................................... 35
Timer / Event Counter 2, 3 ....................... 37

Timer Mode ...................................................... 39
Event counter Mode ......................................... 39

A/D Converter ................................... 42

Control .............................................................. 42

Serial I/O ........................................... 44

Control .............................................................. 44

Pulse Width Modulation (PWM) ...... 46

8bit PWM Control ............................................. 47
14bit PWM Control ........................................... 47

Interrupt interval measurement circuit

........................................................... 49

Control .............................................................. 49

Buzzer driver .................................... 51

Control .............................................................. 51

On Screen Display (OSD) ................ 53

OSDCON1 ....................................................... 55
OSDCON2 ....................................................... 55
OSDPOL .......................................................... 56
FDWSET .......................................................... 56
L1ATTR ............................................................ 57
L1VPOS ........................................................... 58
L2ATTR ............................................................ 58
L2VPOS ........................................................... 58
COLMOD ......................................................... 58
MESHCON ....................................................... 58
VRAM ............................................................... 58
Font ROM ......................................................... 60

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

Sprite RAM ....................................................... 60
Test Font .......................................................... 61

I2C Bus Interface .............................. 62

Control .............................................................. 62
I2C address register ......................................... 62
I2C data shift register [ICDR] ........................... 63
I2C status register ............................................ 63
I2C control register 1 ........................................ 64
I2C control register 2 ........................................ 64
START condition generation ............................ 65
RESTART condition generation ....................... 65
STOP condition generation .............................. 65
START / STOP condition detect ...................... 66
Address data communication ........................... 67

INTERRUPTS .................................... 68

Interrupt Mode Register ................................... 68

Interrupt Sequence ...................................72

Interrupt acceptance ........................................ 72
Saving/Restoring General-purpose Register ... 73

Multi Interrupt ............................................74

External Interrupt ..................................... 75

Response Time ................................................ 75

WATCHDOG TIMER ......................... 76

Watchdog Timer Control .................................. 76
Enable and Disable Watchdog ......................... 77
Watchdog Timer Interrupt ................................ 77
Minimizing Current Consumption ..................... 78

OSCILLATOR CIRCUIT .................... 80
RESET ............................................... 81

External Reset Input ................................. 81
Watchdog Timer Reset ............................ 82

OTP Programming ........................... 83

GMS87C4060 OTP Programming ............ 83
.Device configuration data ...................... 84
Timing Chart ............................................. 87

Assemble mnemonics ..................... 89

Instruction Map ......................................... 89
Alphabetic order table of instruction ..... 90
Instruction Table by Function ................. 94

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

GMS81C4040/GMS87C4060

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

FOR TELEVISION

1. OVERVIEW

1.1 Description

The GMS81C4040/GMS87C4060 is an advanced CMOS 8-bit microcontroller with 40K(60K) bytes of ROM. The device is
one of GMS800 family. The HYUNDAI's GMS81C4040/GMS87C4060 is a powerful microcontroller which provides a
highly flexible and cost effective solution to many TV applications. The GMS81C4040/GMS87C4060 provides the follow-
ing standard features: 40K(60K) bytes of ROM, 1,536 bytes of RAM, 8-bit timer/counter .

1.2 Features

· 40K(60K) Bytes On-chip Program Memory

· 1,536 Bytes of On-chip Data RAM

(Included 256 bytes stack memory)

· Instruction Cycle Time (ex:NOP)

- 0.5us at 8MHz

· 40 Programmable I/O pins

- 33 I/O and 7 Output pins

· Serial I/O : 8bit x 1ch

· I

C Bus interface

- Multimaster (2 Pairs interface pins)

· A/D Converter : 8bit x 6ch (TBD LSB)

· Pulse Width Modulation

- 14bit x 1ch
- 8bit x 6ch

· Timer

- Timer/Counter : 8bit x 4ch (16bit x 2ch)

- Basic interval timer : 8bit x 1ch
- Watch Dog Timer

· Number of Interrupt sources : 18

· On Screen Display

- Number of characters : 512 (6 characters are
reserved for IC test)
- Character size : 12 dots(X) x 16 dots(Y)
- Character display size : Large, Medium, Small
- DIsplay capability : 24Characters x 16 Line
(Two line VRAM buffer)
- Character, Back ground color : 16kinds
- Special functions : Rounding, Outline, Sprite,
Shadow,...

· Buzzer Driving port

- 500Hz ~ 250kHz @8MHz (Duty 50%)

· Operating Range : 4.5V to 5.5V

Device name

ROM Size

RAM Size

Package

GMS81C4040

40K bytes

Mask ROM

1,536 bytes

52SDIP

GMS87C4060

60K bytes

EPROM

1,536 bytes

52SDIP

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

5. PIN FUNCTION

: Supply voltage.

: Circuit ground.

TEST: Used for shipping inspection of the IC. For normal
operation, it should not be connected .

RESET: Reset the MCU.

: Input to the inverting oscillator amplifier and input to

the internal main clock operating circuit.

OUT

: Output from the inverting oscillator amplifier.

OSC1: Input to the internal On Screen Display operating
circuit.

OSC2: Output from the inverting OSC1 amplifier.

R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

In addition, R1 serves the functions of the various follow-
ing special features.

R20~R27: R2 is a 8-bit CMOS bidirectional I/O port. Each
pins 1 or 0 written to the their Port Direction Register can
be used as outputs or inputs.

In addition, R2 serves the functions of the various follow-
ing special features.

R40~R47: R40~R43 are 8-bit NMOS open drain output
and R45~R47 are bidirectional CMOS Input / NMOS open
drain output port. R4 pins 1 or 0 written to the Port Direc-
tion Register can be used as outputs or inputs.

In addition, R4 serves the functions of the various follow-
ing special features.

R50~R56: R50~R53 are 4-bit CMOS bidirectional I/O and
R54~R56 are CMOS output port. R5 pins 1 or 0 written to
the Port Direction Register can be used as outputs or in-
puts.

In addition, R5 serves the functions of the various follow-
ing special features.

R67: R67 is an 1-bit CMOS bidirectional I/O port. R67
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

In addition, R67 serves the functions of the various follow-
ing special features.

R,G,B: R,G,B CMOS output port. Each pins controls Red,
Green,. Blue color control.

Port pin

Alternate function

R10
R11
R12
R13
R14
R15
R16
R17

AN0 (A/D converter input 0)
AN1 (A/D converter input 1)
AN2 (A/D converter input 2)
AN3 (A/D converter input 3)
AN4 (A/D converter input 4)
AN5 (A/D converter input 5)
VD (Vertical Sync. input)
HD (Horisontal Sync. input)

Port pin

Alternate function

R20
R21
R22
R23
R24
R25
R26
R27

INT2 (External interrupt input 2)
Sclk (Serial communication clock)
Sout (Serial communication data out)
Sin (Serial communication data in)
INT3 (External interrupt input 3)
EC2 (Event counter input 2)
INT4 (External interrupt input 4)
EC3 (Event counter input 3)

Port pin

Alternate function

R40
R41
R42
R43
R44
R45

R46
R47

PWM0 (Pulse Width Modulation output 0)
PWM1 (Pulse Width Modulation output 1)
PWM2 (Pulse Width Modulation output 2)
PWM3 (Pulse Width Modulation output 3)

SCL0 (I

C Clock 0)

SCL1 (I

C Clock 1)

PWM4 (Pulse Width Modulation output 4)

SDA0 (I

C Data 0)

SDA1 (I

C Data 1)

PWM5 (Pulse Width Modulation output 5)

Port pin

Alternate function

R50
R51
R52
R54
R55
R56

BUZZ (Buzzer output)
PWM8 (Pulse Width Modulation output 8)
INT0 (External interrupt input 0)
YM (Back ground)
YS (Edge)
I (Intencity)

Port pin

Alternate function

R67

INT1 (External interrupt input 1)

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

PIN NAME

Pin No.

In/Out

Function

Supply voltage

12, 40

Circuit ground

TEST

For test purposes. Should not be connected. (N.C.)

RESET

Reset signal input

Main oscillation input

OUT

Main oscillation output

OSC1

On screen display functions

On screen display oscillation input

OSC2

On screen display osc. output

R17/HD

I/O

Horisontal Sync. input

R16/VD

I/O

Vertical Sync. input

Red signal output

Green signal output

Blue signal output

R56/I

Intencity signal output

R55/YS

Edge signal output

R54/YM

Background signal output

R40/PWM0

PWM functions

8bit PWM

R41/PWM1

8bit PWM

R42/PWM2

8bit PWM

R43/PWM3

8bit PWM

R45/SCL1/
PWM4

I/O

Include I

C Serial clock 1 (SCL1)

R47/SDA1/
PWM5

I/O

Include I

C Serial data 1 (SDA1)

R51/PWM8

I/O

14bit PWM

R44/SCL0

I/O

C functions

C Serial clock 0

R46/SDA0

I/O

C Serial data 0

R23/Sin

I/O

SCI functions

Serial data input

R22/Sout

I/O

Serial data output

R21/Sclk

I/O

Serial communication clock

R27/EC3

I/O

Timer event functions

Event counter input 3

R25/EC2

I/O

Event counter input 2

R50/Buzzer

I/O

Buzzer function

500Hz ~ 250KHz @8MHz

Table 5-1 Port Function Description

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage ........................................... -0.3 to +6.0 V

Storage Temperature ................................-40 to +125

Voltage on any pin with respect to Ground (V

)

............................................................... -0.3 to V

+0.3

Maximum current out of V

pin ........................100 mA

Maximum current into V

pin ............................80 mA

Maximum current sunk by (I

per I/O Pin) ........20 mA

Maximum output current sourced by (I

per I/O Pin)

.................................................................................8 mA

Maximum current (

) ...................................... 80 mA

Maximum current (

)...................................... 50 mA

Note: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.

7.2 Recommended Operating Conditions

7.3 DC Electrical Characteristics - GMS81C4040

=-10~70

C, V

=4.5~5.5V)

Parameter

Symbol

Condition

Specifications

Unit

Min.

Max.

Supply Voltage

XIN

=8MHz

OSC

=16MHz

4.5

5.5

Operating Frequency

XIN

=4.5~5.5V

MHz

On Screen Display Oper-
ating Frequency

OSC

=4.5~5.5V

MHz

Operating Temperature

OPR

-10

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

High level input voltage

IH1

TEST, RESET, Xin, OSC1, R17~16,
R27~20, R47~44, R52, R67

0.8 V

IH2

R0, R15~10, R53~50

0.7 V

Low level input voltage

IL1

TEST, RESET, Xin, OSC1, R17~16,
R27~20, R47~44, R52, R67

0.12 V

IL2

R0, R15~10, R53~50

0.3 V

High level output voltage

= -5mA

R0, R1, R2, R5, R67

- 1

= -1.2mA

R,G,B

- 1

Low level output voltage

= 5mA

R0, R1, R2, R4, R5, R67, R, G, B

1.0

Supply current in
ACTIVE mode

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

8. MEMORY ORGANIZATION

The GMS81C4040/GMS87C4060 has separate address
spaces for Program memory, Data Memory and Display
memory. Program memory can only be read, not written
to. It can be up to 40K/60K bytes of Program memory.

Data memory can be read and written to up to 1,536 bytes
including the stack area. Font memory has prepared 16K
bytes for OSD.

8.1 Registers

This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.

Figure 8-1 Configuration of Registers

Accumulator: The Accumulator is the 8-bit general pur-
pose register, used for data operation such as transfer, tem-
porary saving, and conditional judgement, etc.

The Accumulator can be used as a 16-bit register with Y
Register as shown below.

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the spec-
ified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have in-
crement, decrement, comparison and data transfer func-
tions, and they can be used as simple accumulators.

Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed

(save or restore).

Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.

The stack can be located at any position within 0100

01FF

of the internal data memory. The SP is not initial-

ized by hardware, requiring to write the initial value (the
location with which the use of the stack starts) by using the
initialization routine. Normally, the initial value of "FF

is used.

Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset rou-
tine address (PC

:0FF

, PC

:0FE

Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3 . It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU

ACCUMULATOR

X REGISTER

Y REGISTER

STACK POINTER

PROGRAM COUNTER

PROGRAM STATUS
WORD

PCL

PCH

PSW

Two 8-bit Registers can be used as a "YA" 16-bit Register

Caution:

The Stack Pointer must be initialized by software be-
cause its value is undefined after RESET.

Example: To initialize the SP

LDX

#0FFH

TXSP

; SP

Stack Address ( 0100

~ 01FF

)

Hardware fixed

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.

Figure 8-3 PSW (Program Status Word) Register

[Zero flag Z]

This flag is set when the result of an arithmetic operation
or data transfer is "0" and is cleared by any other result.

[Interrupt disable flag I]

This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to "0". This flag immedi-
ately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.

[Half carry flag H]

After operation, this is set when there is a carry from bit 3
of ALU or there is borrow from bit 4 of ALU. This bit can
not be set or cleared except CLRV instruction with Over-
flow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
dress.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00

to 0FF

when this flag is "0". If it is set to "1",

addressing area is assigned by DPGR register (address
0F8

). It is set by SETG instruction and cleared by CLRG.

[Overflow flag V]

This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
ceeds +127(7F

) or -128(80

). The CLRV instruction

clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.

NEGATIVE FLAG

MSB

LSB

RESET VALUE : 00

PSW

OVERFLOW FLAG

BRK FLAG

CARRY FLAG RECEIVES

ZERO FLAG

INTERRUPT ENABLE FLAG

CARRY OUT

HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS

SELECT DIRECT PAGE

when G=1, page is addressed by RPR

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

8.2 Program Memory

A 16-bit program counter is capable of addressing up to
64K bytes, but GMS81C4040/GMS87C4060 has 40K/
60K bytes program memory space only physically imple-
mented. Accessing a location above FFFF

will cause a

wrap-around to 0000

Figure 8-5 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFE

and FFFF

as shown in Figure 8-6 .

As shown in Figure 8-5 , each area is assigned a fixed lo-
cation in Program Memory. Program Memory area con-
tains the user program.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL in-
stead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.

Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0

for TCALL15, 0FFC2

for

TCALL14, etc., as shown in Figure 8-7 .

Example: Usage of TCALL

The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to loca-
tion 0FFFC

. The interrupt service locations spaces 2-byte

interval: 0FFF8

and 0FFF9

for External Interrupt 1,

0FFFC

and 0FFFD

for External Interrupt 0, etc.

Any area from 0FF00

to 0FFFF

, if it is not going to be

used, its service location is available as general purpose
Program Memory.

Figure 8-6 Interrupt Vector Area

PROGRAM

MEMORY

TCALL

AREA

INTERRUPT

VECTOR AREA

81C4040:6000H

FEFFH
FF00H

FFC0H

FFDFH
FFE0H

FFFFH

PCALL

AREA

81C4060:1000H

FFBFH

LDA

TCALL

0FH

;

1 B Y TE IN S T R U C T IO N

;

IN S TE A D O F 2 B Y TE S

;

N O R M A L C A L L

;
;TABLE CALL ROUTINE
;
FUNC_A:

LDA

LRG0

RET

;
FUNC_B:

LDA

LRG1

RET

;
;TABLE CALL ADD. AREA
;

ORG

0FFC0H

;

TC A L L A D D R E SS A R E A

FUNC_A

FUNC_B

0FFE0

Address

Vector Area Memory

C Bus Interface Interrupt Vector Area

Serial I/O Interrupt Vector Area

Basic Interval Timer Interrupt Vector Area

Watchdog Timer Interrupt Vector Area

Timer/Counter 3 Interrupt Vector Area

Timer/Counter 1 Interrupt Vector Area

V-Sync Interrupt Vector Area

Timer/Counter 2 Interrupt Vector Area

Timer/Counter 0 Interrupt Vector Area

External Interrupt 2 Vector Area

On Screen Display Interrupt Vector Area

External Interrupt 0 Vector Area

RESET Vector Area

External Interrupt 1 Vector Area

1 Frame Timer Interrupt Vector Area

External Interrupt 3/4 Vector Area

"-" means reserved area.

NOTE:

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa-
ble. Data Memory is divided into four groups, a user RAM,
control registers, Stack, and OSD memory.

Figure 8-8 Data Memory Map

User Memory

The GMS81C4040/GMS87C4060 has 1,536

8 bits for

the user memory (RAM).

Control Registers

The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The basic control registers
are in address range of 00C0

to 00FF

. And OSD control

registers are assigned within 0AE0

~ 0AFF

Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.

More detailed informations of each register are explained
in each peripheral section.

Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write instruc-
tion. Use byte manipulation instruction.

Example; To write at CKCTLR

LDM

CLCTLR,#09H ;Divide ratio

Stack Area

The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.

When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.

The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 19.

Page0

RAM (192 bytes)

Peripheral Reg. (64 bytes)

0100H

00C0H

0000H

RAM (256 bytes)

0200H

RAM (256 bytes)

0300H

RAM (256 bytes)

0400H

RAM (256 bytes)

0500H

RAM (256 bytes)

0600H

RAM (64 bytes)

0A00H

OSD RAM (192 bytes)

0AE0H

Peripheral Reg. (32 bytes)

0C00H

Sprite RAM (96 bytes)

Empty area

Page1

Page2

Page3

Page4

Page5

Page6

PageA

PageC

063FH

Stack area

0C5FH

Address

Symbol

R/W

Reset Value

Addressing

mode

00C0H
00C1H
00C2H
00C3H
00C4H
00C5H
00C8H
00C9H

00CAH
00CBH
00CCH
00CDH
00CEH
00CFH

R0DD

R1DD

R2DD

R4DD

R5DD

R6DD

FUNC1
FUNC2

R/W

W
W
W

????????

00000000

????????

00000000

????????

00000000

????????

0000----

????????

----0000

?-------

0-------

-0000000

---00000

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte
byte
byte

Table 8-1Control registers

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

0D0H
0D1H
0D2H
0D3H
0D4H
0D5H
0D6H

0D7H
0D8H
0D9H

0DAH
0DBH
0DCH
0DEH
0DFH

TM0
TM2

TDR0
TDR1
TDR2
TDR3

BITR

CKCTLR

WDTR

ICAR
ICDR
ICSR

ICCR1
ICCR2

SIOM

SIOR

R/W
R/W
R/W
R/W
R/W
R/W

W
W

R/W
R/W
R/W
R/W
R/W
R/W
R/W

-0000000

????????

--010111

-0111111

00000000

11111111

0001000-

00000000

-0000001

????????

byte
byte

byte, bit
byte, bit
byte, bit
byte, bit

byte
byte
byte

byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit

0E0H
0E1H
0E2H
0E3H
0E4H
0E5H
0E8H
0E9H

0EAH
0EBH
0EEH
0EFH

PWMR0
PWMR1
PWMR2
PWMR3
PWMR4
PWMR5
PWM8H

PWM8L

PWMCR1
PWMCR2

BUR

AIPS

W
W
W
W
W
W

R/W
R/W
R/W
R/W

W
W

????????

--??????

00000000

--0-0000

????????

--000000

byte
byte
byte
byte
byte
byte

byte, bit
byte, bit
byte, bit
byte, bit

byte
byte

0F0H
0F1H
0F2H
0F3H
0F4H
0F5H
0F6H
0F7H
0F9H

0FAH
0FBH
0FCH
0FDH

ADCM

ADR

IEDS

IMOD

IENL

IRQL
IENH

IRQH
IDCR

IDFS

IDR

DPGR

TMR

R/W

R/W
R/W
R/W
R/W
R/W
R/W

R
R

R/W

--011101

????????

--000000

0000000-

00000000

0000-000

1----001

????????

----0000

????????

byte, bit

byte
byte

byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit

byte
byte

byte, bit

byte

0AE0H
0AE1H
0AE2H
0AE3H
0AE4H
0AE5H
0AE6H
0AE8H
0AE9H
0AF0H
0AF1H
0AF3H
0AF4H

OSDcon1
OSDcon2

OSDPOL
FDWSET

EDGEcol

OSDLN
LHPOS

SPVPOS
SPHPOS

L1ATTR

L1VPOS

L2ATTR

L2VPOS

R/W
R/W

W
W
W

W
W
W
W
W
W
W

00000000

-0000000

????????

01111010

10000111

---00000

????????

byte, bit
byte, bit

byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte

Table 8-1Control registers

1. "byte, bit" means that register can be addressed by not only bit

but byte manipulation instruction.

2. "byte" means that register can be addressed by only byte

manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for clear-
ing bit.

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GMS81C4040/87C4060

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8.4 Addressing Mode

The GMS800 series uses six addressing modes;

· Register addressing

· Immediate addressing

· Direct page addressing

· Absolute addressing

· Indexed addressing

· Register-indirect addressing

(1) Register Addressing

(2) Immediate Addressing

#imm

In this mode, second byte (operand) is accessed as a data
immediately.

Example:

FE10: 0435

ADC

#35H

When G-flag is 1, then RAM address is defined by 16-bit
address which is composed of 8-bit direct page accessable
register (DPGR) and 8-bit immediate data.

Example: G=1, DPGR=0CH

F100: E45535

LDM

35H,#55H

(3) Direct Page Addressing

In this mode, a address is specified within direct page.

Example; G=0

E551: C535

LDA

35H;A

RAM[35H]

(4) Absolute Addressing

!abs

Absolute addressing sets corresponding memory data to
Data , i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY

Example;

F100: 0735F0 ADC!0F035H

ROM[0F035H]

A+35H+C

MEMORY

0FE10

0F100

data

55H

data

0C35

0F102

0F101

data

0E551

data

0E550

0F100

data

0F035

0F102

0F101

A+data+C

address: 0F035

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

regard-

less of G-flag and DPGR.

F100: 983501 INC!0135H

ROM[135H]

(5) Indexed Addressing

X indexed direct page (no offset)

{X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15

, G=1, DPGR=03

E550: D4

LDA

{X};ACC

RAM[X].

X indexed direct page, auto increment

{X}+

In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.

LDA, STA

Example; G=0, X=35

F100: DB

LDA

{X}+

X indexed direct page (8 bit offset)

dp+X

This address value is the second byte (Operand) of com-
mand plus the data of

-register. And it assigns the mem-

ory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5

E550: C645

LDA

45H+X

0F100

data

135

0F102

0F101

data+1

data

address: 0135

data

315

0E550

data

36H

0F100

data

0E551

data

0E550

45H+0F5H=13AH

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GMS81C4040/87C4060

May. 2000 Ver 1.0

Y indexed direct page (8 bit offset)

dp+Y

This address value is the second byte (Operand) of com-
mand plus the data of Y-register, which assigns Memory in
Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute

!abs+Y

Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify mem-
ory in whole area.

Example; Y=55

F100: D500FA

LDA

!0FA00H+Y

(6) Indirect Addressing

Direct page indirect

[dp]

Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.

JMP, CALL

Example; G=0

FA00: 3F35

JMP

[35H]

X indexed indirect

[dp+X]

Processes memory data as Data, assigned by 16-bit pair
m e m o r y w h i c h i s d e t e r m i n e d b y p a i r d a t a
[dp+X+1][dp+X] Operand plus X-register data in Direct
page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10

FA00: 1625

ADC

[25H+X]

0F100

data

0FA55

0FA00H+55H=0FA55H

0F102

0F101

jump to address 0E30A

0FA00

0E30A

0E005

0FA00

0E005

data

A + data + C

25 + X(10) = 35

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GMS81C4040/87C4060

May. 2000 Ver 1.0

9. I/O PORTS

The GMS81C4040/GMS87C4060 has digital ports (R0,
R1, R2, R4, R5 and R6) and OSD ports (R,G,B).

These ports pins may be multiplexed with an alternate

function for the peripheral features on the device. In gen-
eral, in a initial reset state, R ports are used as a general
purpose digital port.

9.1 Registers for Port

Port Data Registers

The Port Data Registers in I/O buffer in each R ports are
represented as a Type D flip-flop, which will clock in a val-
ue from the internal bus in response to a "write to data reg-
ister" signal from the CPU. The Q output of the flip-flop is
placed on the internal bus in response to a "read data reg-
ister" signal from the CPU. The level of the port pin itself
is placed on the internal bus in response to "read data reg-
ister" signal from the CPU. Some instructions that read a
port activating the "read register" signal, and others acti-
vating the "read pin" signal

Port Direction Registers

All pins have data direction registers which can define
these ports as output or input. A "1" in the port direction
register configure the corresponding port pin as output.
Conversely, write "0" to the corresponding bit to specify it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbered bits as input
ports, write "55

" to address 0C1

(R0 port direction reg-

ister) during initial setting as shown in Figure 9-1 .

All the port direction registers in the GMS81C4040/
GMS87C4060 have 0 written to them by reset function. On
the other hand, its initial status is input.

Figure 9-1 Example of port I/O assignment

I : INPUT PORT

WRITE "55

" TO PORT R0 DIRECTION REGISTER

R0 DATA

R4 DATA

R0 DIRECTION

R4 DIRECTION

0C0H

0C1H

0C8H

0C9H

BIT

PORT

O : OUTPUT PORT

GMS81C4040/87C4060

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9.2 I/O Ports Configuration

R0 Ports

R0 is an 8-bit CMOS bidirectional I/O port (address
0C0

). Each I/O pin can independently used as an input or

an output through the R0DD register (address 0C1

The control registers for R0 are shown below.

In addition, Port R0 is only digital I/O. After reset, R0DD
value is "0", R0 acts as normal digital input port.

R1 Ports

R1 is an 8-bit CMOS bidirectional I/O port (address
0C2

). Each I/O pin can independently used as an input or

an output through the R1DD register (address 0C3

R1 port have secondary functions as following table.

The control registers for R1 are shown below.

Port R1 is multiplexed with various special features.The
control registers controls the selection of alternate func-
tion. After reset, R1 port acts as normal digital input port.
The way to select alternate function such as A/D input or
HD,VD will be shown in each peripheral section.

Port Pin

Alternate Function

R10
R11
R12
R13
R14
R15
R16
R17

AN0 (A/D input 0)
AN1 (A/D input 1)
AN2 (A/D input 2)
AN3 (A/D input 3)
AN4 (A/D input 4)
AN5 (A/D input 5)
VD (Vertical Sync. input)
HD (Horizontal Sync. input)

R0 Data Register

ADDRESS : 00C0

RESET VALUE : Undefined

R07

R06

R05

R04

R03

R02

R01

R00

Port Direction

R0 Direction Register

R0DD

ADDRESS : 00C1

RESET VALUE : 0000 0000

0: Input
1: Output

R1 Data Register

ADDRESS : 00C2

RESET VALUE : Undefined

R17

R16

R15

R14

R13

R12

R11

R10

Port Direction

R1 Direction Register

R1DD

ADDRESS : 00C3

RESET VALUE : 0000 0000

0: Input
1: Output

A/D Convertor mode Register

ADCM

ADDRESS : 00F0

RESET VALUE : --01 1101

Port Property

Analog input pin selector Register

AIPS

ADDRESS : 00EF

RESET VALUE : --00 0000

0: Digital I/O
1: Analog Input

R16/VD select

Port function select Register 2

FUNC2

ADDRESS : 00CF

RESET VALUE : ---0 0000

0: R16 I/O
1: VD Input

ADEN ADS2 ADS1 ADS0 ADST ADSF

HDS

VDS

YMS

YSS

A/D Status
0: Busy
1: Finish

A/D Start
0: Ignore
1: A/D start

A/D Port select
000: AN0
001: AN1

A/D Enable
0: Disable
1: Enable

010: AN2
011: AN3
100: AN4
101: AN5
110: AN6
111: No Analog port

R17/HD select
0: R17 I/O
1: HD Input

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R2 Port

R2 is an 8-bit CMOS bidirectional I/O port (address
0C4

). Each I/O pin can independently used as an input or

an output through the R2DD register (address 00C5

The control registers for R2 are shown below.

R4 Port

R4 is consrutced with 4-bit Open drain Output port and 4-
bit CMOS bidirectional I/O port (address 0C8

). Each I/O

pin can independently used as an input or an output
through the R4DD register (address 0C9

The control registers for R4 are shown below.

R2 Data Register

ADDRESS : 00C4

RESET VALUE : Undefined

R27

R26

R25

R24

R23

R22

R21

R20

Port Direction

R2 Direction Register

R2DD

ADDRESS : 00C5

RESET VALUE : 0000 0000

0: Input
1: Output

Serial I/O mode Register

SIOM

ADDRESS : 00DE

RESET VALUE : -000 0001

00: Ignore edge

Ext. interrupt edge selection Register

IEDS

ADDRESS : 00F2

RESET VALUE : --00 0000

01: Falling edge
10: Rising edge

R20/INT2

Port function select Register 1

FUNC1

ADDRESS : 00CE

RESET VALUE : -000 0000

0: R20
1: INT2

SM1

SM0

SCK1 SCK0 SIOST SIOSF

INT4S INT3S INT2S INT1S INT0S

Seriial Status
0: Busy
1: Finish

Serial Start
0: Ignore
1: Serial start

Clock select
00: PS3
01: PS4

Serial I/O
0: Serial In
1: Serial Out

10: PS5
11: External

IOSW

EC2S

EC3S

SM1

0
0
1
1

SM0

0
1
0
1

Mode

Send
Receive

R21
R21
Sclk
Sclk
R21

R22
R22
Sout
R22
R22

R23
R23
R23
Sin
R23

R24/INT3
0: R24
1: INT3

R26/INT4
0: R26
1: INT4

R27/EC3
0: R27
1: EC3

R25/EC2
0: R25
1: EC2

IED2H IED2L

IED1H IED1L IED0H IED0L

11: Falling/Rising edge

INT2

R4 Data Register

ADDRESS : 00C8

RESET VALUE : Undefined

R47

R46

R45

R44

R43

R42

R41

R40

Port Direction

R4 Direction Register

R4DD

ADDRESS : 00C9

RESET VALUE : 0000 ----

0: Input
1: Output

C Control Register 1

ICCR1

ADDRESS : 00DB

RESET VALUE : 00-0 0000

EN5,4,3,2,1 : R47,45,43,42,41,40

PWM control Register 1

PWMCR1

ADDRESS : 00EA

RESET VALUE : 0000 0000

0: R4x acts normal digital port
1: R4x acts PWM output port

ALS

ESO

BC2

BC1

BC0

EN2

EN1

EN0

EN8

CNT

Bit count
000

(8bit)

C enable

0: Disable
1: Enable

BSW0

EN3

EN4

EN5

BSW1

0
0
1
1

BSW0

0
1
0
1

R44

R44
SCL0
R44
SCL

R45

R45/PWM4
R45/PWM4
SCL1
SCL

R46

R46
SDA0
R46
SDA

BSW1

001

~111

(1~7bit)

R47

R47/PWM5
R47/PWM5
SDA1
SDA

Slave address identification
0: Accept (Addressing format)
1: Decline (Free data format)

14/8bit PWM count
0: Count start
1: Count stop

R51/PWM8 select
0: R51
1: PWM8

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

R5 Port

R5 is an 7-bit port (address 0CA

). Each I/O pin can inde-

pendently used as an input or an output through the R5DD
register (address 0CB

The control registers for R5 are shown below

R6 Port

R6 is an 1-bit CMOS bidirectional I/O port (address
0CC

). Each I/O pin can independently used as an input or

an output through the R6DD register (address 0CD

The control registers for R6 are shown below

R5 Data Register

ADDRESS : 00CA

RESET VALUE : Undefined

R56

R55

R54

R53

R52

R51

R50

Port Direction

R5 Direction Register

R5DD

ADDRESS : 00CB

RESET VALUE : ---- 0000

0: Input
1: Output

00: Ignore edge

Ext. interrupt edge selection Register

IEDS

ADDRESS : 00F2

RESET VALUE : --00 0000

01: Falling edge
10: Rising edge

R52/INT0

Port function select Register 1

FUNC1

ADDRESS : 00CE

RESET VALUE : -000 0000

0: R52
1: INT0

INT4S INT3S INT2S INT1S INT0S

EC2S

EC3S

IED2H IED2L

IED1H IED1L IED0H IED0L

11: Falling/Rising edge

R56/I

Port function select Register 2

FUNC2

ADDRESS : 00CF

RESET VALUE : ---0 0000

0: R56
1: I Output

HDS

VDS

YMS

YSS

R55/YS
0: R55
1: YS Output

R54/YM
0: R56
1: YM Output

PWM control Register 2

PWMCR2

ADDRESS : 00EB

RESET VALUE : --0- 0000

POL2 POL1

EN7

EN6

BUZS

INT2

R50/BUZZ
0: R50
1: BUZZ

R6 Data Register

ADDRESS : 00CC

RESET VALUE : Undefined

Port Direction

R6 Direction Register

R6DD

ADDRESS : 00CD

RESET VALUE : 0--- ----

0: Input
1: Output

00: Ignore edge

Ext. interrupt edge selection Register

IEDS

ADDRESS : 00F2

RESET VALUE : --00 0000

01: Falling edge
10: Rising edge

R67/INT1

Port function select Register 1

FUNC1

ADDRESS : 00CE

RESET VALUE : -000 0000

0: R67
1: INT1

INT4S INT3S INT2S INT1S INT0S

EC2S

EC3S

IED2H IED2L

IED1H IED1L IED0H IED0L

11: Falling/Rising edge

INT1

R67

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

10. CLOCK GENERATOR

As shown in Figure 10-1 , the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It con-
tains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. The system clock can
also be obtained from the external oscillator.

The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the periph-
eral hardware.

To the peripheral block, the clock among the not-divided
original clocks, divided by

, 4,...,

up to 1024 can be pro-

vided. Peripheral clock is enabled or disabled by bit 4 of
the peripheral clock enable register (ENPCK).

Figure 10-1 Block Diagram of Clock Generator

Note: On the initial reset, all peripherals are run because
peripheral clock is supplied to each function block. If you
want to see more details, see Clock Control Register
(CKCTLR).

Main clock

Minimum instruction cycle time

(ex:NOP ; f

4clock is needed)

3.6MHz

1,111nS

4MHz

1,000nS

8MHz

500nS

Internal system clock

P R E SC A LE R

ENPCK

Peripheral clock

Clock control register

[0D6

]

CKCTLR

WDT ENPCK BTCL BTS2 BTS1 BTS0

Clock pulse Generator

OSC

Circuit

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS1

12
8

25
6

51
2

10
24

20
48

Clock control register

ADDRESS : 00D6

RESET VALUE : --01 0111

CKCTLR

WDT ENPCK BTCL BTS2 BTS1 BTS0

Peri. Clock
0: Stop
1: Supply

Watch-dog
timer select
0: Normal 6bit timer
1: Watch-dog timer

B.I.T set
0: Free run
1: B.I.T clear

B.I.T Clock

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

11. TIMER

11.1 Basic Interval Timer

The GMS81C4040/GMS87C4060 has one 8-bit Basic In-
terval Timer that is free-run and can not be stopped. Block
diagram is shown in Figure 11-1 .

The Basic Interval Timer generates the time base for
watchdog timer counting, and etc. It also provides a Basic
interval timer interrupt (BITIF). As the count overflow
from FF

to 00

, this overflow causes the interrupt to be

generated. The Basic Interval Timer is controlled by the
clock control register (CKCTLR) shown in Figure 11-2 .

Source clock can be selected by lower 3 bits of CKCTLR.

BITR and CKCTLR are located at same address, and ad-
dress 00D6

is read as a BITR and written to CKCTLR..

Figure 11-1 Block Diagram of Basic Interval Timer

Table 11-1 Basic Interval Timer Interrupt Time

MUX

Basic Interval Timer Interrupt

BITR

Select Input clock

source
clock

8-bit up-counter

BITCK

BTCL

Watchdog timer clock (WDTCK)

clear

overflow

Internal bus line

[0D6

]

[0D6

]

BITIF

Clock control register

CKCTLR

WDT ENPCK BTCL BTS2 BTS1 BTS0

PS4

PS5

PS6

PS7

PS8

PS9

PS10

PS11

BTS2~0

Source clock

Interrupt

(overflow) Period

P re -S cale r o utpu t

At f

=8MHz

000

001

010

011

100

101

110

111

PS4

PS5

PS6

PS7

PS8

PS9

PS10

PS11

0.512

1.024

2.048

4.096

8.192

16.384

32.768

65.536

HYUNDAI

GMS81C4040/87C4060

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Figure 11-2 BITR: Basic Interval Timer Mode Register

11.2 Timer 0, 1

Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare
data register, 8-bit count register, Control register, and
Comparator as shown in Figure 11-3 .

These Timers can run separated 8bit timer or combined
16bit timer. These timers are operated by internal clock.

The contents of TDR1 are compared with the contents of
up-counter T1. If a match is found, a timer/counter 1 inter-
rupt (T1IF) is generated, and the counter is cleared. Count-
ing up is resumed after the counter is cleared.

Note: You can read Timer 0, Timer 1 value from TDR0 or
TDR1. But if you write data to TDR0 or TDR1, it changes
Timer 0 or Timer 1 modulo data, not Timer value.

The content of TDR0, TDR1 must be initialized (by soft-
ware) with the value between 01

and FF

,not to 00

Or not, Timer 0 or Timer 1 can not count up forever.

The control registers for Timer 0,1 are shown below.

CKCTLR

INITIAL VALUE: Undefined

ADDRESS: 00D6

BITR

Both register are in same address,

when write, to be a CKCTLR,

when read, to be a BITR.

Caution:

8-BIT BINARY COUNTER

ADDRESS : 00D6

RESET VALUE : --01 0111

WDT ENPCK BTCL BTS2 BTS1 BTS0

Peri. Clock
0: Stop
1: Supply

Watch-dog
timer select
0: Normal 6bit timer
1: Watch-dog timer

B.I.T set
0: Free run
1: Clear 8-bit counter (BITR) to "0". This bit becomes 0

B.I.T Clock

automatically after 1 machine cycle

Timer mode register 0

TM0

ADDRESS : 00D0

RESET VALUE : -000 0000

Timer 0 data register

TDR0

ADDRESS : 00D2

RESET VALUE : Undefined

T1SL0 T0ST

T0CN T0SL1 T0SL0

T1SL1

T1ST

Timer 1 data register

TDR1

ADDRESS : 00D3

RESET VALUE : Undefined

Timer 0 input clock
00: PS2 (f

/ 2

)

01: PS4 (f

/ 2

)

10: PS6 (f

/ 2

)

11: PS8 (f

/ 2

)

Timer 1 input clock
00: Timer 0 overflow (16bit mode)
01: PS2 (f

/ 2

)

10: PS4 (f

/ 2

)

11: PS6 (f

/ 2

)

0: Count Hold
1: Count Continue

Timer 0 control

0: Count Hold
1: Count Clear and Start

Timer 0 start

0: Count Hold
1: Count Clear and Start

Timer 1 start

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

Figure 11-5 Simplified Block Diagram of 16bit Timer0, 1

11.3 Timer / Event Counter 2, 3

Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare
data register, 8-bit count register, Control register, and
Comparator as shown in Figure 11-5 .

These Timers have two operating modes. One is the timer
mode which is operated by internal clock, other is event
counter mode which is operated by external clock from pin
R25/EC2, R27/EC3.

These Timers can run separated 8bit timer or combined
16bit timer.

Note: You can read Timer 2, Timer 3 value from TDR2 or
TDR3. But if you write data to TDR2 or TDR3, it changes
Timer 2 or Timer 3 modulo data, not Timer value.

The content of TDR2, TDR3 must be initialized (by soft-
ware) with the value between 01

and FF

,not to 00

Or not, Timer 2 or Timer 3 can not count up forever.

The control registers for Timer 2,3 are shown below

Internal bus line

TM0

TDR0

Timer 0

Clock

TDR1

Timer 1

Clock

Clear

16bit Comparator

T1IF

MUX

PS2
PS4
PS6
PS8

T0CN

T0ST

Timer mode register 2

TM2

ADDRESS : 00D1

RESET VALUE : -000 0000

Timer 2 data register

TDR2

ADDRESS : 00D4

RESET VALUE : Undefined

T3SL0 T2ST

T2CN T2SL1 T2SL0

T3SL1

T3ST

Timer 3 data register

TDR3

ADDRESS : 00D5

RESET VALUE : Undefined

Timer 2 input clock
00: PS2 (f

/ 2

)

01: PS4 (f

/ 2

)

10: PS6 (f

/ 2

)

11: PS8 (f

/ 2

)

Timer 3 input clock
00: Timer 2 overflow (16bit mode)
01: PS2 (f

/ 2

)

10: PS4 (f

/ 2

)

11: PS6 (f

/ 2

)

0: Count Hold
1: Count Continue

Timer 2 control

0: Count Hold
1: Count Clear and Start

Timer 2 start

0: Count Hold
1: Count Clear and Start

Timer 3 start

Port function select Register 1

FUNC1

ADDRESS : 00CE

RESET VALUE : -000 0000

INT4S INT3S INT2S INT1S INT0S

EC2S

EC3S

R27/EC3
0: R27
1: EC3

R25/EC2
0: R25
1: EC2

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

Figure 11-8 Simplified Block Diagram of 16bit Timer/Event Counter 2,3

Timer Mode

In the timer mode, the internal clock is used for counting
up. Thus, you can think of it as counting internal clock in-
put. The contents of TDRn (n=0~3) are compared with the
contents of up-counter, Timer n. If match is found, a timer

n interrupt (TnIF) is generated and the up-counter is
cleared to 0. Counting up is resumed after the up-counter
is cleared.

As the value of TDRn is changeable by software, time in-
terval is set as you want

Figure 11-9 Timer Mode Timing Chart

Event counter Mode

In event timer mode, counting up is started by an external
trigger. This trigger means falling edge of the ECn (n=2~3)
pin input. Source clock is used as an internal clock selected
with TM2. The contents of TDRn are compared with the
contents of the up-counter. If a match is found, an TnIF in-
terrupt is generated, and the counter is cleared to 00

. The

counter is restarted by the falling edge of the ECn pin in-

put.

The maximum frequency applied to the ECn pin is f

[Hz] in main clock mode.

In order to use event counter function, the bit EC2S, EC3
of the Port Function Select Register1 FUNC1(address
0CE

) is required to be set to "1".

After reset, the value of TDRn is undefined, it should be

Internal bus line

TM2

TDR2

Timer 2

Clock

TDR3

Timer 3

Clock

Clear

16bit Comparator

T3IF

MUX

EC2
PS4
PS6
PS8

T0CN

T0ST

N-2

N-1

Source clock

Up-counter

TDRn (n=0~3)

TnIF (n=0~3) interrupt

Start count

Match
Detect

Counter
Clear

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

12. A/D Converter

The A/D convertor circuit is shown in Figure 12-1 .

The A/D convertor circuit consists of the comparator and
c o n t r o l r e g i s te r A I P S ( 0 0 E F

) , A D C M ( 0 0 F 0

) ,

ADR(00F1

). The AIPS register select normal port or an-

alog input. The ADCM register control A/D converter's
activity. The ADR register stores A/D converted 8bit re-
sult. The more details are shown Figure 12-2 .

Figure 12-1 Block Diagram of A/D convertor circuit

Control

The GMS81C4040/GMS87C4060 contains a A/D con-
verter module which has six analog inputs.

1. First of all, you have to select analog input pin by set the
ADCM and AIPS.

2. Set ADEN (A/D enable bit : ADCM bit5).

3. Set ADST (A/D start bit : ADCM bit1). We recommend
you do not set ADEN and ADST at once, it makes worse
A/D converted result.

4. ADST bit will be cleared automatically 1cycle after you
set this.

Example:

; Set AIPS, change ? to what you want
;

0 : digital port

;

1 : analog port

LDM AIPS,#00??????b

; Set ADEN, xxx is analog port number

LDM ADCM,#001xxx00b
; or "SET1 ADEN"

; Set ADST, xxx is analog port number

LDM ADCM,#001xxx10b
; or "SET1 ADST"
:
:

5. After A/D conversion is completed, ADSF bit and inter-
rupt flag IFA will be set. (A/D conversion takes 36 ma-
chine cycle : 9uS when f

=8MHz).

Note: Make sure AIPS bits, if you using a port which is set
digital input by AIPS, analog voltage will be flow into MCU
internal logic not A/D converter. Sometimes device or port
is damaged permanently.

Comparator

AN0

MUX

AN1

AN2

AN3

port
select

S/H

ADCM [F0

]

ADEN ADS2 ADS1 ADS0 ADST ADSF

ADR [F1

]

AN4

AN5

Control circuit

Succesive
Approximation
Circuit

IFA

Vref

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

13. Serial I/O

The Serial I/O circuit is shown in Figure 13-1 .

The Serial I/O circuit consists of the octal counter, SI-
OR(DF

), SIOM(DE

). The SIOR register stores received

data or data which will be transfered. The SIOM register
controls serial communication mode, speed, start, etc.

The more details about registers are shown Figure 13-2 .

Figure 13-1 Block Diagram of Serial I/O circuit

Control

The GMS81C4040/GMS87C4060 contains a Synchronous
type Serial I/O module.

1. You have to select serial I/O pins by set the SM1~0.

Note: Sout pin can handle serial data output or serial data
input. You can input serial data to Sout pin when IOSW bit
is 1. But Sin pin is dedicated serial data input pin.

2. You have to select serial communication clock by set the
SCK1~0.

3. If you want to send data, write it to SIOR. Or not skip
this.

4. Start serial communication by set SIOST(Serial I/O
start, SIOM bit1).

. After serial communication is completed, SIOSF bit and

interrupt flag IFSIO will be set.

MUX

SIOM [DE

]

SM1

SM0

SCK1 SCK0 SIOST SIOSF

SIOR [DF

]

Sout

Sin

Octal counter

Control
Circuit

IFSIO

IOSW

MUX

PS3

PS5

PS4

Exclk

Sclk

SM1

SM0

Function

Port select

R21

R22

R23

R21

R22

R23

Send

Sclk

Sout

R23

Receive

Sclk

R22

Sin

R21

R22

R23

SCK1

SCK0

Selected Clock

Ex: Frequency

=8MHz)

PS3

1uS

PS4

2uS

PS5

4uS

External clock

User define

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

8bit PWM Control

The GMS81C4040/GMS87C4060 contains a one 14bit
PWM and six 8bit PWM module.

1. 8bit PWM0~5 is wholy same internal circuit, but
PWM0~5 output port is NMOS open drain.

2. Al l PWM polarity has the same by POL2's value.

3. Calulate Frame cycle and Pulse width is as following.
PWM Frame Cycle = 2

/ f

(Sec)

PWM Width = (PWMRn+1) * 2

/ f

(n=0~5)

Pulse Duty (%) = (PWMRn +1) / 256 *100(%) (n=0~5)

Figure 14-3 Wave form example for 8bit PWM

4. PWM output is enabled during ENn(n=0~5) bit (See
PWMCR1~2) contains 1.

Figure 14-4 8bit PWM Registers

5. CNTB controls all PWM counter enable.
If CNTB=0, Counter is enabled.

14bit PWM Control

1. 14bit PWM's operation concept is not the same as 8bit
PWM.
1 PWM frame contains 64 sub PWMs.
PWM8H : Set sub PWM's basic Pulse Width.
PWM8L : Number of sub PWM which is added 1 clock.

2. PWM polarity is selected by POL1's value.
If POL1=0, Positive Polarity.

3. Calulate Frame cycle and Pulse width is as following.
Main PWM Frame Cycle = 2

/ f

(Sec).

Sub PWM Frame Cycle = Main Frame Cycle / 64.

4. Table 14-1, "PWM8L and Sub frame matching table,"
on page 47 show PWM8L function.

Figure 14-5 Wave form example for 14bit PWM

Positive Polarity (POL2=0)

Negative Polarity (POL2=1)

1. Frame cycle
2. Pulse Width

PWM Data Register

PWMR0~5

ADDRESS : 0E0~E5

RESET VALUE : Undefined

EN5,4,3,2,1 : R47,45,43,42,41,40

PWM control Register 1

PWMCR1

ADDRESS : 0EA

RESET VALUE : 0000 0000

0: R4x acts normal digital port
1: R4x acts PWM output port

EN2

EN1

EN0

EN8

CNTB

EN3

EN4

EN5

PWM control Register 2

PWMCR2

ADDRESS : 0EB

RESET VALUE : --0- 00--

POL2 POL1

BUZS

8bit PWM Polarity
0: Positive (PWM from Rising edge)
1: Negative (PWM from Rising edge)

14bit Counter enable
0: Counter run
1: Counter stop

Bit value

Sub frame number which is

added 1 clock

Pulse
count

if Bit0=1

if Bit1=1

16, 48

if Bit2=1

8, 24, 40, 56

if Bit3=1

4, 12, 20, 28, 36, 44, 52, 60

if Bit4=1

2, 6, 10, 14, 18, 22, 26, 30, 34,
38, 42, 46, 50, 54

if Bit5=1

1, 3, 5, 7, 9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29, 31, 33, 35, 37,
39, 41, 43, 45, 47, 49, 51, 53, 55,
57, 59, 61, 63

Table 14-1 PWM8L and Sub frame matching table

Main PWM Frame

.....

1 2

61 62 63

Sub PWM Frame

Sub PWM Frame
which is added
1 clock

1 clock width : PS2

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

15. Interrupt interval measurement circuit

The Interrupt interval measurement circuit is shown in Fig-
ure 15-1 .

The Interrupt interval measurement circuit consists of the
input multiplexer, sampling clock multiplexer, Edge detec-

tor, 8bit counter, measured result storing register, FIFO
(9bit, 6level) interrupt, Control register, etc.

The more details about registers are shown Figure 15-2 .

Figure 15-1 Block Diagram of Interrupt interval measurement circuit

Control

The GMS81C4040/GMS87C4060 contains a Interrupt in-
terval measurement module.

1. Select interrupt input pin what you want to measure by
set the FUNC1 [00CE

2. Set IDCR [00F9

] : FIFO clear, interrupt mode, inter-

rupt edge select, external interrupt select between INT3
and INT4, sampling clock select.

3. Set IDCR [00F9

] : set IDST to start measuring.

4. Counter value is stored to IDR [00FB

] when selected

edge is detected. After data was written, timer is cleard au-
tomatically and it counts continue.

. You can select interrupt occuring point by set Interrupt

Mode Select bit (IMS), every edge what you selected or
FIFO 4 level is filled.

6. If input signal's interval is larger than maximum counter
value (0FF

), counter occurring an interrupt and count

again from 00

7. See Figure 15-4 FIFO operating mechanism.

MUX

IDCR [F9

]

I34H

I34L

ISEL

IDCK

IDST

IDFS [FA

]

INT3

INT4

8bit counter

FIFO

(9bit, 6level)

INTV

IMS

DPOL

FOE

FFUL FEMP

FCLR

MUX

PS8

PS9

MUX

Edge detector

Clear

IDR [FB

]

Overflow

FCLR

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

Figure 15-2 Int. interval measurement Registers

Figure 15-3 Setting for measurement

Figure 15-4 Example for FIFO operating mechanism

IDR

ADDRESS : 00FB

RESET VALUE : Undefined

Interrupt interval determination

IDCR

ADDRESS : 00F9

RESET VALUE : 0000 -000

Counter control
0: stop
1: Clear & count

Sampling clock select
0: PS9
1: PS8

Int. occuring time
0: Every selected

I34H

I34L

FCLR

ISEL

IDCK

IDST

IMS

See Figure 15-3

R24/INT3

Port function select Register 1

FUNC1

ADDRESS : 00CE

RESET VALUE : -000 0000

0: R24
1: INT3

INT4S INT3S INT2S INT1S INT0S

EC2S

EC3S

control Register

External Interrupt select
0: INT3
1: INT4

FIFO clear
0: Ignored
1: Clear and return to 0

edge by I34H/L
1: Every FIFO 4level
is filled

is filled

Interrupt interval determination

IDFS

ADDRESS : 00FA

RESET VALUE : 1--- -001

FIFO Empty flag
0: Data filled
1: Empty

FIFO Full flag
0: Not full
1: Full

DPOL

FOE

FFUL

FEMP

FIFO status Register

FIFO overrun error flag
0: No Error
1: Error detected

Data polarity
0: Data is stored every Falling edge

Interrupt interval determination
FIFO Data Register

1: Data is stored every Rising edge

R26/INT4
0: R26
1: INT4

Item

Symbol

I34H

I34L

Detecting

edge

Frame Cycle

Rising

edge

Falling

edge

Pulse width

Both edge

Interrupt input

1) FIFO storing mechanism

2) FIFO reading mechanism

FEMP=1, FFUL=0

FEMP=0, FFUL=0

FEMP=0, FFUL=1

FEMP=0

FEMP=1

Read out

Data in

Data 6 will be erased.

Data 1

Data 2

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 1

Data 2

Data 1

Data 2

Data 3

Data 4

Data 5

Data 7

FOE=1 (Over run error)

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

16. Buzzer driver

The Buzzer driver circuit is shown in Figure 16-1 .

The Buzzer driver circuit consists of the 6bit counter, 6bit
comparator, Buzzer data register BUR(00EE

). The BUR

The more details about registers are shown Figure 16-2 .

Figure 16-1 Block Diagram of Buzzer driver circuit

Control

The GMS81C4040/GMS87C4060 contains a Buzzer driv-
er module.

1. Selec t an input clock am ong PS4~7 by se t the
BUCK1~0 of BUR.

2. Select output frequency by change the BU5~0.
Output frequency = 1 / (PSx * BUy *2) Hz.
x=4~7, y=5~0
See example Table 16-1 and Table 16-2.

Note: Do not select 00

to BU5~0. It means counter stop.

3. Set BUZS bit for output enable.

4. Output waveform is rectagle clock which has 50% duty.

5. You can use this clock for the other purposes.

Figure 16-2 Buzzer driver Registers

BUR [EE

]

BU5

BU4

BU3

BU2

BU1

BU0

6bit counter

Output
Generator

BUZZ

BUCK

MUX

PS4

PS6

PS5

PS7

BUCK

-1

-0

clear

6bit Comparator

clear

PWMCR2 [EB

]

BUZS

POL2

POL1

EN7

EN6

BUR write

BUCK1

BUCK0

Clock source

PS4

PS5

PS6

PS7

Buzzer data Register

BUR

ADDRESS : 0EE

RESET VALUE : ???? ????

Input select

Clock Select

PWM control Register 2

PWMCR2

ADDRESS : 0EB

RESET VALUE : --0- 00--

POL2 POL1

BUZS

R50/Buzz select
0: R50
1: Buzz output

BU5

BU4

BU3

BU2

BU1

BU0

BUCK

-1

-0

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

BUR5~0

Output frequency (KHz)

Dec

Hex

PS4

PS5

PS6

PS7

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

01
02
03
04
05
06
07
08
09
0A
0B

0C
0D
0E
0F

10
11
12
13
14
15
16
17
18
19
1A
1B

1C
1D
1E
1F

20
21
22
23
24
25
26
27
28
29
2A
2B

2C
2D
2E
2F

30
31
32
33
34
35
36
37
38
39
3A
3B

3C
3D
3E
3F

250
125
83.333
62.5
50
41.666
35.714
31.25
27.728
25
22.728
20.834
19.23
17.858
16.666
15.626
14.706
13.888
13.158
12.5
11.904
11.364
10.87
10.416
10
9.616
9.26
8.928
8.62
8.334
8.064
7.812
7.576
7.352
7.124
6.944
6.756
6.578
6.41
6.25
6.098
5.952
5.814
5.682
5.556
5.434
5.32
5.208
5.102
5
4.902
4.808
4.716
4.63
4.546
4.464
4.386
4.31
4.238
4.166
4.098
4.032
3.968

125
62.5
42.666
31.25
25
20.888
17.858
15.625
13.888
12.5
11.364
10.417
9.615
8.929
8.333
7.813
7.353
6.944
6.579
6.25
5.952
5.682
5.435
5.208
5
4.808
4.63
4.464
4.31
4.167
4.032
3.906
3.788
3.676
3.571
3.472
3.378
3.289
3.205
3.125
3.049
2.976
2.907
2.841
2.778
2.717
2.66
2.604
2.551
2.5
2.451
2.404
2.358
2.315
2.273
2.232
2.193
2.155
2.119
2.083
2.049
2.016
1.984

62.5
31.25
20.833
15.625
12.5
10.461
8.928
7.813
6.944
6.25
5.682
5.209
4.808
4.484
4.166
3.906
3.676
3.472
3.289
3.125
2.976
2.841
2.718
2.604
2.5
2.404
2.315
2.232
2.155
2.084
2.016
1.953
1.894
1.838
1.786
1.736
1.689
1.645
1.602
1.563
1.524
1.488
1.453
1.421
1.389
1.359
1.33
1.302
1.276
1.25
1.225
1.202
1.179
1.157
1.136
1.116
1.096
1.078
1.059
1.042
1.025
1.008
0.992

31.25
15.625
10.436
7.813
6.25
5.208
4.464
3.907
3.472
3.125
2.841
2.604
2.404
2.242
2.083
1.953
1.838
1.736
1.644
1.562
1.438
1.420
1.359
1.302
1.25
1.202
1.158
1.116
1.078
1.042
1.008
0.976
0.947
0.919
0.893
0.868
0.845
0.822
0.801
0.781
0.762
0.744
0.727
0.710
0.694
0.679
0.665
0.651
0.638
0.625
0.613
0.601
0.590
0.579
0.568
0.558
0.548
0.539
0.530
0.521
0.512
0.504
0.496

Table 16-1 . Example for f

=8MHz

BUR5~0

Output frequency (KHz)

Dec

Hex

PS4

PS5

PS6

PS7

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

01
02
03
04
05
06
07
08
09

0A
0B
0C
0D
0E
0F

10
11
12
13
14
15
16
17
18
19

1A
1B
1C
1D
1E
1F

20
21
22
23
24
25
26
27
28
29

2A
2B
2C
2D
2E
2F

30
31
32
33
34
35
36
37
38
39

3A
3B
3C
3D
3E
3F

375
187.5
125
93.75
75
62.5
53.572
46.875
41.666
37.5
34.09
31.25
28.846
26.786
25
23.436
22.058
20.833
19.736
18.75
17.858
17.045
16.304
15.625
15
14.424
13.888
13.393
12.932
12.5
12.096
11.718
11.364
11.03
10.714
10.416
10.136
9.868
9.616
9.375
9.146
8.929
8.72
8.523
8.334
8.152
7.978
7.813
7.654
7.5
7.352
7.212
7.076
6.944
6.818
6.696
6.578
6.466
6.356
6.25
6.148
6.048
5.952

187.5
93.75
62.5
46.875
37.5
31.25
26.786
23.436
20.833
18.75
17.045
15.625
14.423
13.393
12.5
11.719
11.029
10.417
9.868
9.375
8.929
8.523
8.152
7.813
7.5
7.212
6.944
6.696
6.466
6.25
6.048
5.859
5.682
5.515
5.357
5.208
5.068
4.934
4.808
4.688
4.573
4.464
4.36
4.261
4.167
4.076
3.989
3.906
3.827
3.75
3.676
3.606
3.538
3.472
3.409
3.348
3.289
3.233
3.178
3.125
3.074
3.024
2.976

93.75
46.875
31.35
23.436
18.75
15.625
13.393
11.719
10.417
9.375
8.523
7.813
7.211
6.696
6.25
5.859
5.515
5.208
4.934
4.688
4.464
4.261
4.076
3.906
3.75
3.606
3.472
3.348
3.233
3.125
3.024
2.930
2.841
2.757
2.679
2.604
2.534
2.467
2.404
2.344
2.287
2.232
2.18
2.131
2.083
2.038
1.995
1.953
1.913
1.875
1.838
1.802
1.769
1.736
1.705
1.674
1.645
1.616
1.589
1.563
1.537
1.512
1.488

46.875
23.438
15.625
11.719
9.375
7.813
6.696
5.895
5.208
4.688
4.261
3.906
3.606
3.348
3.125
2.930
2.757
2.604
2.467
2.344
2.232
2.131
2.038
1.953
1.875
1.803
1.736
1.674
1.616
1.563
1.512
1.465
1.420
1.379
1.339
1.302
1.267
1.234
1.202
1.172
1.143
1.116
1.09
1.065
1.042
1.019
0.997
0.977
0.957
0.938
0.919
0.901
0.884
0.868
0.852
0.837
0.822
0.808
0.795
0.781
0.768
0.756
0.744

Table 16-2 . Example for f

=12MHz

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

17. On Screen Display (OSD)

The On Screen Display circuit is shown in Figure 17-1 .

The GMS81C4040/GMS87C4060 can support 512 OSD
chacters, but the last 6 characters (number 506 ~ 511,
1FA

~ 1FF

) are reserved for IC test and its pattern is

fixed by manufacturer. So you can use 506 characters for
your own.

The OSD circuit consists of the Position attribute register,
Line register, Full screen screen control register, sprite
control register, sprite position reigster, I/O polarity regis-
ter, sprite RAM, font ROM, VRAM, etc. The more details
about registers are shown Figure 17-2.

Figure 17-1 Block Diagram of On Screen Display circuit

L1ATTR [AF0

]

OSD Control
Circuit

OSDLN [AE5

]

OSDCON1 [AE0

]

OSDCON2 [AE1

]

SPVPOS [AE8

]

OSDPOL [AE2

]

Line 1,2 Attribute,
Position register

Line register

Full screen control

Sprite position register

I/O polarity register

Sprite control register

L1VPOS [AF1

]

L2ATTR [AF3

]

L2VPOS [AF4

]

SPHPOS [AE9

]

LHPOS [AE6

]

Horizontal position register

FDWSET [AE3

]

Field detection register

EDGECOL [AE4

]

Edge color register

VRAM

Font ROM

Sprite Control
Circuit

Sprite RAM

OSD, Sprite Generation Circuit

Sprite Control
Circuit

Output
Control
Circuit

Synchronization
Circuit

HSYNC

VSYNC

OSC1

OSC2

I
YS
YM

Color Mode Register

COLMOD [0AEF

]

Mesh Control Register

MESHCON [0AEB

]

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

Figure 17-3 OSD Control Registers - 1

OSDCON1

bit 0: STOCK

It controls OSD LC oscillation. If oscillation is stoped,
IC's power consumption is decreased.

bit 1: DDCLK

If you set this bit to 1, OSD input clock is doubled from LC
oscillation. It makes OSD horisontal image size as dou-
bled.

bit 2: DLINE

If you set this bit to 1, OSD vertical scan counter input
clock is doubled from normal state. It makes OSD vertical
image size as doubled.

bit 7~3: FULLM, I, B, G, R

It controls back ground color as below.

OSDCON2

bit 0: OSDON

It controls OSD, Sprite, Full screen background at once. It
does not affect anything to Vsync interrupt and OSD inter-
rupt, etc.

bit 1: PROSD

It controls screen output priority between sprite and OSD.
If its value is 1, OSD hide sprite pattern in overapped area.

bit 2: ENSP

It enables sprite display.

bit 3: DUSP

It doubles sprite's horizontal & vertical size during this
value is 1.

bit 4: ONL1

It enables OSD line 1 display. If it is enabled, OSD inter-
rupt is activated.

bit 5: ONL2

It enables OSD line 2 display. If it is enabled, OSD inter-
rupt is activated.

bit 6: OBGW

It controls character's width. Default width is 12dots. If its
value is set, 2 dots (background color) are added both left

Color

Transparent (Normal TV)

RED

Table 17-1 Full Screen Back ground color selection

Sprite OSD control Register

OSDCON2

ADDRESS : 0AE1

RESET VALUE : 0000 0000

Full screen control Register

OSDCON1

ADDRESS : 0AE0

RESET VALUE : 0000 0000

STOP OSD clock

0: Release
1: Stop

FULB FULG FULR DLINE DDCLKSTOCK

FULI

OBGW ONL2 ONL1 DUSP ENSP PRO

OSD

FULM

Double dot clock mode

0: Normal
1: Double

Double scan line mode

0: Normal
1: Double

Full screen background

FULLM
FULLI
FULLB
FULLG
FULLR

: Half blank
: Half intensity
: Blue
: Green
: Red

OSD, Sprite

0: All Off
1: All On

Priority

0: Sprite > OSD
1: OSD > Sprite

Sprite enable

0: Disable
1: Enable

Sprite size

0: Normal
1: Double

Background width

0: 12dots
1: 14dots

OSD line 2

0: Off
1: On

OSD line 1

0: Off
1: On

per 1 character

DUSP
CL

Double sprite
dot clock
(Sprite size)

0: x1, x2
1: x2, x4

GREEN

RED+GREEN

BLUE

BLUE+RED

BLUE+GREEN

RED+GREEN+BLUE (WHITE)

BLACK

Half intensity RED

Half intensity GREEN

Half intencity RED+GREEN

Half intensity BLUE

Half intensity GREEN+BLUE

Half intensity WHITE

Half BLANK

Color

Table 17-1 Full Screen Back ground color selection

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

and right side of character.

bit 7: DUSPCL

It controls sprite's dot clock and scan line speed. It does not
affect to OSD. Sprite size is controlled as below.

Figure 17-4 OSD Registers - 2

OSDPOL

bit7~0 : POL HS, VS, I, YM, YS, B, G, R

It controls HS, VS, I, YM, YS, B, G, R port's polarity. If
its value is 1, polarity is active high.

FDWSET

FDWSET (Field Detection Window Seting) register de-
tects the begin of VSync(Vertical Sync.) signal and distin-
guishs its current field is Even field or Odd field.

Figure 17-5 FDWSET detection region

The region of FMIN[2:0] ~ FMAX[3:0] is field detection
window.

FMAX[3:0] can divide the region between HSync(Hori-
zontal Sync.) by 16. You can assume there is 4 bit horizon-
tal counter, for example HCOUNT[3:0] which count 0~15.

If the start of VSync is detected at the window, next field
is even. Else if VSync is detected another region of the
window, next field is odd.

It means start of VSync is detected during FMIN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and FPOL value is 0, it dis-
tinguish odd field.

And, start of VSync is detected during FMIN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and FPOL value is 1, it dis-
tinguish even field.

FMIN[2:0], FMAX[3:0] are compared with the horizontal
counter in OSD block.

DUSPCL

DUSP

Size

Normal

12x16

x 2

24x32

Not used

x 4

48x64

Table 17-2 Sprite pattern size

I/O Polarity ( initial ) Register

OSDPOL

ADDRESS : 0AE2

RESET VALUE : Undefined

POL

POLI

POL

POLB POLG POLR

POL

0: Active Low
1: Active High

OSD display enable,

POLHS
POLVS
POLI
POLYM
POLB
POLG
POLR

: Hsync. input
: Vsync. input
: Half intensity output
: Half blank output
: Blue output
: Green output
: Red output

include the edge color.

0: Off
1: On

Field detection Register

FDWSET

ADDRESS : 0AE3

RESET VALUE : 0111 1010

FPOL

F M IN 2 ~ 0

F M A X 3 ~ 0

Field detection polarity

0: Detect Odd field

Field detection
Maximum pointer

Field detection
Minimum pointer

Masking range : Min.~Max.
1: Detect Even field
Detecting range : Min.~Max.

HSync

Ex1: VSync(Odd)

Ex2: VSync(Even)

FMIN

FMAX

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

Figure 17-6 OSD Registers - 3

Figure 17-7 OSD Registers - 4

L1ATTR

bit 0 : LIV8

It is equivalent with L1VPOS's bit 8. See more details in
L1VPOS.

bit 1: FSC1

It selects character outline and shadow color. If it is 1, it se-
lect EDGE2 color in EDGECOL register. Or not, it select
EDGE1 color. According to EDGECOL register and this
bit character and shadow colors are selected simulteneous-
ly

bit 3~2: CSZ11~CSZ10

It controls OSD character's size ( x1, x2, x3). You can use
this register and DDCLK, DLINE bit, horizontal / vertical
size can be controlled (x2, x4, x6).

bit 4: ENSH1

It enables line 1's character(foreground) shadow.

bit 5: ENOL1

It enables line 1's character(foreground) outline.

bit 6: WDSL1

It shows thickness of line 1's shadow and outline.

bit 7: OBGH1

It controls character's height. Default height is 16dots. If
its value is set, 2 dots (background color) are added both
top and bottom side of character.

OSD line Register

OSDLN

ADDRESS : 0AE5

RESET VALUE : ---0 0000

Background shadow / edge

EDGECOL

ADDRESS : 0AE4

RESET VALUE : Undefined

EDGnI

EDG

Edge 2 color

V L R 4 ~ 0

color Register

EDG

Edge 1 color

EDGnB
EDGnG
EDGnR

: Half Intensity
: Blue
: Green
: Red

n : 1 ~ 2

Current displayed OSD line number

( 00000 ~ 11111

: 0 ~ 63 )

OSD line horizontal

LHPOS

ADDRESS : 0AE6

RESET VALUE : Undefined

OSD line's horizontal position (00 ~ FF

)

Sprite vertical

SPVPOS

ADDRESS : 0AE8

RESET VALUE : Undefiend

Sprite horisontal

SPHPOS

ADDRESS : 0AE9

RESET VALUE : Undefined

position Register

Sprite's vertical position (00 ~ FF

)

Sprite's horisontal position (00 ~ FF

)

OSD line 1's

L1VPOS

ADDRESS : 0AF1

RESET VALUE : Undefined

OSD line 1's

L1ATTR

ADDRESS : 0AF0

RESET VALUE : Undefined

Vertical position

Foreground shadow

ENOL ENSH

CSZ

FSC1

L1V8

WDSL

Character size

L1V7

L1V6

L1V5

L1V4

L1V3

L1V2

L1V1

L1V0

attribute Register

vertical position Register

OSD line 1's vertical position (include L1V8 : 000 ~ 1FF

)

OBGH

L1VPOS's bit8

out line color
0: Edge 1's color
1: Edge 2's color

00: Normal
01: 2 times
10: 3 times
11: Reserved

Character Shodow

0: Disable
1: Enable

charcater outline

0: Disable
1: Enable

Shadow / Outline

0: 1dot
1: Propotional

Character

0: 16dots
1: 18dots

background
height

width

to character
size

control

WDSL

ENOL

ENSH

outline, shadow

No outline, No shadow

Thin shadow

Thin outline

Thick shadow

No outline, No shadow

Thick shadow

Thick outline

Thick shadow

Table 17-3 Character Outline, Shadow table

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

L1VPOS

It shows OSD line 1's vertical position in 9bit format
(LIV8 + L1VPOS, 000 ~ 1FF

Figure 17-8 OSD Registers - 5

Figure 17-9 OSD Register - 6

L2ATTR

It controls OSD line 2's attributes. Its function is the same
as L1ATTR.

L2VPOS

It shows OSD line 2's vertical position. Its function is the
same as L1VPOS.

COLMOD

It controls OSD output mode-RGB direct half intencity.

Figure 17-10 OSD Register - 7

bit 0: C16EN

It enables RGB port half intencity output. When this bit is
set, RGB port generates half intencity output. Half intenci-
ty output is 3.5V voltage level output of RGB port. When
you use this bit, you must fill all the other bit with `0'.

Note: When you do not use RGB direct half intncsity out-
put , please initialize this register as 00h.

MESHCON

It controls OSD mesh mode color.

Figure 17-11 OSD Register - 8

Note: Please initialize this register as 00h. Though this
register is for mesh mode color, it is not used currently.

VRAM

VRAM contains 1 OSD line, 24 character's attributes.

Each character's attribute is constructed with 3 bytes, it
contains color data for background, shadow, outline, char-
acter and character number ( 000

~ 1FF

, 512 characters

OSD line 2's

L2VPOS

ADDRESS : 0AF4

RESET VALUE : Undefined

OSD line 2's

L2ATTR

ADDRESS : 0AF3

RESET VALUE : Undefined

Vertical position

Foreground shadow

ENOL ENSH

CSZ

FSC2

L2V8

WDSL

Character size

L2V7

L2V6

L2V5

L2V4

L2V3

L2V2

L2V1

L2V0

attribute Register

vertical position Register

OSD line 2's vertical position (include L2V8 : 000 ~ 1FF

)

OBGH

L2VPOS's bit8

out line color
0: Edge 1's color
1: Edge 2's color

00: Normal
01: 2 times
10: 3 times
11: Reserved

Shodow control

0: Disable
1: Enable

Out line control

0: Disable
1: Enable

Shadow / Outline

0: 1dot
1: Propotional

Character

0: 16dots
1: 18dots

background
height

width

to character
size

OSD line 2's

L2VPOS

ADDRESS : 0AF4

RESET VALUE : Undefined

OSD line 2's

L2ATTR

ADDRESS : 0AF3

RESET VALUE : Undefined

Vertical position

Foreground shadow

ENOL ENSH

CSZ

FSC2

L2V8

WDSL

Character size

L2V7

L2V6

L2V5

L2V4

L2V3

L2V2

L2V1

L2V0

attribute Register

vertical position Register

OSD line 2's vertical position (include L2V8 : 000 ~ 1FF

)

OBGH

L2VPOS's bit8

out line color
0: Edge 1's color
1: Edge 2's color

00: Normal
01: 2 times
10: 3 times
11: Reserved

Shodow control

0: Disable
1: Enable

Out line control

0: Disable
1: Enable

Shadow / Outline

0: 1dot
1: Propotional

Character

0: 16dots
1: 18dots

background
height

width

to character
size

Color Output Mode

COLMOD

ADDRESS : 0AEF

RESET VALUE : Undifined

RGB Half intensity enable

C16EN

1: Enable

0: Enable

(see Note)

Fill with `0'

Mesh Mode Color

MESHCON

ADDRESS : 0AEB

RESET VALUE : See Note

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

), etc.

Note: if (BSL = 1) & (BSCUL = 0) & (LnATTR,ENSHn = 1),
then the right bottom shadow of font character is shifted to
1 dot right side. This shadow effect will continue until that
(BSR) of adjacent character attribution become (BSR = 1).

Line

No.

Character

No.

Address (bit 23~0)

Hexa decimal

A40

A20

A00

A41

A21

A01

A42

A22

A02

A55

A35

A15

A56

A36

A16

A57

A37

A17

AC0

AA0

A80

AC1

AA1

A81

AC2

AA2

A82

AD5

AB5

A95

AD6

AB6

A96

AD7

AB7

A97

Table 17-4 VRAM memory map

Bit No.

Name

Function

BSR

Enable right side background
shadow.
cf. If BSL=1 and BSCUL=1 and
LnATTR.ENSHn=1, character's
right bottom shadow is shifted to
right side by 1dot unit.
It acts continued until current
character's right side chacter's
BSR is set to 1.

BSL

Enable left side background
shadow.

BSD

Enable bottom side background
shadow.

BSU

Enable top side background
shadow.

BSCDR

Select color of right and bottom

side shadow of the background

0: Edge1, 1: Edge2 color

Table 17-5 VRAM (bit15~0) function

BSCUL

Select color of left and top side
shadow of the background
0: Edge1, 1: Edge2 color

ENRND

Enable character's rounding

8~0

CG8~0

Character font number
( among 000 ~ 1FF

)

Bit No. &

Name

Output ( Polarity :

Through)

Character

color

Y
S

Clear

Red

Green

Yellow

Blue

Magenta

Cyan

White

Black

Half-I,Red

Half-I,Green

Half-I,

Yellow

Half-I,Blue

Half-I,

Magenta

Half-I,Cyan

Half-I,White

Table 17-6 VRAM (bit19~16) function

Bit No.

Name

Function

Table 17-5 VRAM (bit15~0) function

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

Font ROM

The GMS81C4040/GMS87C4060 OSD character size is
fixed as 12dots (Horisontal) * 16dots (Vertical).

1. Each horisontal data (12dots) needs 2byte ROM.

2. One character is constructed with 16 horisontal data to
vertically. As a result, one character needs 32bytes (2 * 16
bytes).

3. GMS81C4040/GMS87C4060 contains 512 characters.
Total Font ROM memory size is calulated as 16,384bytes
( 32bytes / character * 512 character )

4. Font ROM memory is located from 10000

~ 13FFF

this memory can not be accessed by user program.

5. A character's address and dot position in font ROM is
described in Figure 17-12 .

Figure 17-12 Example for a character (53

)

Sprite RAM

The GMS81C4040/GMS87C4060 contains a 32bytes
(12dot * 16dot) sprite RAM.

1. In view point, sprite is similar to character font but it is
not using font ROM.

2. You can selct color by dot unit.

3. Using above 1 and 2, you can make any of patterns what
you want by software. For example, arrow cursor or some-

Bit No. &

Name

Output ( Polarity :

Through)

Back

ground

color

Y
S

Clear

Red

Green

Yellow

Blue

Magenta

Cyan

White

Half

blanking

Half-I,Green

Half-I,

Yellow

Half-I,Blue

Half-I,

Magenta

Half-I,Cyan

Half-I,White

Black

Table 17-7 VRAM (bit 23 ~ 20) function

Charact

er code

Address range

Upper 4bit

Lower 8bit

000

12000

~ 1200F

10000

~ 1000F

001

12010

~ 1201F

10010

~ 1001F

002

12020

~ 1202F

10020

~ 1002F

xyz

(12000H + xyz0H) ~

(12000H + xyzFH)

(10000H + xyz0H) ~

(10000H + xyzFH)

1FD

13FD0

~ 13FDF

11FD0

~ 11FDF

1FE

13FE0

~ 13FEF

11FE0

~ 11FEF

1FF

13FF0

~ 13FFF

11FF0

~ 11FFF

Table 17-8 Font ROM memory map

MSB

LSB

Address

12530

12531

12532

12533

12534

12535

12536

12537

12538

12539

1253A

1253B

1253C

1253D

1253E

1253F

Data

Address

10530

10531

10532

10533

10534

10535

10536

10537

10538

10539

1053A

1053B

1053C

1053D

1053E

1053F

Data

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

thing.

4. Sprite position is controlled by sprite position register
SPVPOS[0AE8

] and SPHPOS[0AE9

5. Sprite RAM is located 0C00~0CF5

. One sprite RAM

byte contains 2 dot's color data. See more details in Table
17-9 ~ Table 17-11.

Test Font

GMS81C4040 use first OSD font as test purpose(see
Fig17-13). When you design OSD characte font, you incert
following font to Font ROM 00h. If you like to use this font
originally, please contact us

Figure 17-13 Test Font Pattern

Column
number

Row number

MSB

LSB

0C05

0C00

0C15

0C10

0C25

0C20

(n=0~F)

0Cn5

0Cn0

0C05

0C00

0C05

0C00

Table 17-9 Sprite RAM address map

Odd dot color

Even dot color

bit No.

Function

Table 17-10 A sprite RAM's contents

Color

Clear

Red

Green

Yellow

Blue

Black

Cyan

White

Table 17-11 Sprite RAM Color Table

1000H 00H

1001H 00H

1002H 00H

1003H F8H

1004H FCH

1005H 0EH

1006H 06H

1007H 06H

1008H 06H

1009H 06H

100AH 06H

100BH 06H

100CH 0EH

100DH FCH

100EH F8H

100FH 00H

1200H 00H

1201H 00H

1202H 00H

1203H 01H

1204H 03H

1205H 07H

1206H 06H

1207H 06H

1208H 06H

1209H 06H

120AH 06H

120BH 06H

120CH 07H

120DH 03H

120EH 01H

120FH 00H

MSB

LSB address data

address data

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

18. I

C Bus Interface

The I

C Bus interface circuit is shown in Figure 18-1 .

The multi-master I

C Bus interface is a serial communica-

tions circuit, conforming to the Phlips I

C Bus data trans-

fer format. This interface, offering both arbitration lost
detection and a synchronous functions, is useful for the
multi-master serial communications.

This multi-master I

C Bus interface circuit consists of the

C address register, the I

C data shift register, the I

clock control register, the I

C control register, the I

C sta-

tus register and other control circuits.

The more details about registers are shown Figure 18-2 ~
Figure 18-6 .

Figure 18-1 Block Diagram of multi-master I

C circuit

Control

The GMS81C4040/GMS87C4060 contains two I

C Bus

interface modules. It supports multi-master function, so it
contains arbitration lost detection, synchronization func-
tion,etc.

C address register

It contains slave address (7bit) which is used during slave
mode and Read/Write bit.

Bit 7 ~ 0 : Slave address 6~0

Note: Bit 7~0 (SAD6~0) store slave address. The address
data transmitted from the master is compared with the con-
tents of these bits.

ICAR [D8

]

IFI2CR

Bit counter

SCL

Address
comparator

ICDR [D9

]

Interrupt
Generation
Circuit

Data
Control
Circuit

ICSR [00DA

]

MST

TRX

AAS

AD0

LRB

Noise
Elimination
Circuit

AL
Circuit

BB
Circuit

Clock
Control
Circuit

Noise
Elimination
Circuit

ICCR1 [00DB

]

B S E L 1 ~ 0

ALS

ESO

B C 2 ~ 0

ICCR2 [DC

]

ACLK ACK

C C R 3 ~ 0

Clock division

External clock

SDA

SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W

ITEM

Function

Format

Philips

standard

7bit addressing format

Communication

mode

Master transmitter
Master receiver
Slave transmitter
Slave receiver

SCL clock

frequency

66.6KHz ~ 500KHz (f

=12MHz)

44.4KHz ~ 333.3KHz (f

=8MHz)

ITEM

Function

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

Figure 18-2 I

C address Register

C data shift register [ICDR]

The I

C data shift register is an 8bit shift register to store

received data and write transmit data.

When transmit data is written into this register, it is trans-
fered to the outside from bit7 in synchronization with the
SCL clock, and each time one-bit data is output, the data of
this register are shifted one bit to the left. When data is re-
ceived, it is input to this register from bit0 in synchroniza-
tion with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.

The I

C data shift register is in a write enable status only

when the ESO bit of the I

C control register (address

00DC

) is "1". The bit counter is reset by a write instruc-

tion to the I

C data shift register. Reading data from the

C data shift register is always enabled regardless of the

ESO bit value.

Figure 18-3 Data shift register

C status register

The I

C status register controls the I

C Bus interface sta-

tus. The low-order 4bits are read only bits and the high-or-
der 4bits can be read out and written to.

The more details about its bits are shown Table 18-1.

ICAR

ADDRESS : 00D8

RESET VALUE : 0000 0000

SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W

Slave address

ICDR

ADDRESS : 00D9

RESET VALUE : 0000 0000

S hift le ft 1-bit e ach S C L

Bit

No.

Name

Function

7
6

MST

TRX

00: Slave / Receiver mode
01: Slave / Transmitter mode
10: Master / Receiver mode
11: Master / Transmitter mode
MST is cleared when
- After reset.
- After the arbitration lost is occured and
1 byte data transmission is finished.
- After stop condition is detected.
- When start condition is disabled by
start condition duplication preventation
function.
TRX is cleared when
- After reset.
- When arbitration lost or stop condition
is occured .
- When MST is `0', and start condition
or ACK non-return mode is detected.

BB(Bus busy)bit is 1 during bus is busy.
This bit can be written by S/W. its value
is `1' by start condition, and cleared by
stop condition.

PIN(Pending Interrupt Not)bit is inter-
rupt request bit.

If I

C interrupt request is issued, its

value is 0.
PIN is cleared when
- After 1 byte trasmission / receive is fin-
ished.
PIN is set when
- After reset.
- After write instruction is excuted into

C data shift register ICDR.

- When PIN bit low, the output of SCL is
pulled down, So if you want to release
SCL, you must perform write instruction
CDR.

Arbitration lost detection flag.
If arbitration lost is detected, AL=1, or 0.

AAS

Slave address comparison flag.
It shows compared result with received

address data and I

C address register

(ICAR).
It is 1, when two of data is same.

Table 18-1 Bit function

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

Figure 18-4 I

C status Register

C control register 1

It controls communication data format.

Figure 18-5 I

C control Register 1

C control register 2

It controls SCL mode, SCL frequency, etc.

It contains 8bit data to transmit to external device when tr-
asmitter mode, or received 8bit data from external device
when receive mode.

AD0

General call detection flag.
If general call is detected, AD0=1, or
not 0.
* General call : If received address is all
`0' . it is called general call.

LRB

Last received bit.
it is used for receive confirmation. If
ACK is returned, LRB=0, or not 1.

Bit

No.

Name

Function

7
6

BSEL1
BSEL0

C connection control.

00: No connection
01: SCL1, SDA1
10: SCL2, SDA2
11: SCL1, SDA1, SCL2, SDA2

ALS

Data format selection.
0: Addressing format
1: Free data format

ESO

C Bus interface use enable flag

0: Disabled
1: Enabled

BC2

Bit counter.
000

: 8bit

001

~111

: 1~7bit

BC1

BC0

Table 18-2 Bit function

Bit

No.

Name

Function

Table 18-1 Bit function

ICSR

ADDRESS : 00DA

RESET VALUE : 0001 0000

MST

TRX

AAS

AD0

LRB

Bit

No.

Name

Function

ACLK

Select acknowledge clock (ACK) mode.
0: No acknowledge clock mode.
acknowledge clock is not generated
after data was transmismitted.
1: acknowledge clock mode.
acknowledge clock is generated after
data was transmismitted.

ACK

If acknowledge clock is returned, this bit
is 0. Or not 1.

(fixed)

Not used.

Table 18-3 Bit function

ICCR1

ADDRESS : 00DB

RESET VALUE : 00-0 0000

ALS

ESO

BC2

BC1

BC0

BSEL

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GMS81C4040/87C4060

May. 2000 Ver 1.0

Figure 18-6 I

C control Register 2

Figure 18-7 Interrupt request signal generation timing

START condition generation

When the ESO bit of the I

C control register (00DB

) is

"1", writing to the I

C status register will generate START

condition. Refer to Figure 18-8 for the START condition
generation timing diagram.

Figure 18-8 START condition generation timing

RESTART condition generation

RESTART condition's setting sequence is as followings.

1. Write 020

to I

C status register (ICSR, 00DA

)

2. Write slave address to I

C data shift register (ICDR,

00D9

)

3. Write 0F0

to I

C status register (ICSR, 00DA

)

STOP condition generation

Writing `C0h' to ICSR will generate a stop condition,

3
2
1
0

CCR3
CCR2
CCR1
CCR0

SCL Frequency selection

SCL frequency = f

/ (12 * CCR)

Value

= 12MHz

= 8MHz

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Not allowed
Not allowed
500.0KHz
333.3KHz
250.0KHz
200.0KHz
166.6KHz
142.9KHz
125.0KHz
111.1KHz
100.0KHz
90.0KHz
83.3KHz
76.4KHz
71.4KHz
66.6KHz

Not allowed
Not allowed
333.3KHz
222.2KHz
166.6KHz
133.3KHz
111.1KHz
95.2KHz
83.3KHz
74.1KHz
66.6KHz
60.6KHz
55.5KHz
51.3KHz
47.6KHz
44.4KHz

Bit

No.

Name

Function

Table 18-3 Bit function

ICCR2

ADDRESS : 00DC

RESET VALUE : 000- 0000

ACLK

ACK

CCR3 CCR2

CCR1 CCR0

SCL

C Request

ICSR write signal

SCL

SDA

BB (Bus busy) flag

SETUP

HOLD

: Setup time
: Hold time
: Set time for BB

SETUP

HOLD

C status reg.)

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

19. INTERRUPTS

The GMS81C4040/GMS87C4060 interrupt circuits con-
sist of Interrupt enable register (IENH, IENL), Interrupt re-
quest flags of IRQH, IRQL, Priority circuit and Master
enable flag ("I" flag of PSW). 16 interrupt sources are pro-
vided. The configuration of interrupt circuit is shown in
Figure 19-2 .

Below table shows the Interrupt priority

The External Interrupts can each be transition-activated (1-
to-0 or 0-to-1 transition).
When an external interrupt is generated, the flag that gen-
erated it is cleared by the hardware when the service rou-
tine is vectored to only if the interrupt was transition-
activated.

T h e T i m e r /C o u nt e r I n te r r up t s a r e ge n e r a t e d b y
TnIF(n=0~3), which is set by a match in their respective
timer/counter register.

The Basic Interval Timer Interrupt is generated by BITIF
which are set by a overflow in the timer register.

The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IE NH, IE NL) a nd the interrupt reques t flags (in
IRQH,IRQL) except Power-on reset and software BRK in-
terrupt.

Interrupt Mode Register

It controls interrupt priority. It takes only one specified in-
terrupt.

Of course, interrupt's priority is fixed by H/W, but some-
times user want to get specified interrupt even if higher
priority interrupt was occured. Higher priority interrupt is
processed the next time.

It contains 2bit data to enable priority selection and 4bit
data to select specified interrupt.

Figure 19-1 Interrupt Mode Register

Reset/Interrupt

Symbol

Priority

Hardware Reset
External Interrupt 0
OSD Interrupt
External Interrupt 1
External Interrupt 2
Timer/Counter 0
Timer/Counter 2
1 Frame Interrupt
VSync Interrupt
Timer/Counter 1
Timer/Counter 3
Interrupt interval measure
Watchdog Timer
Basic Interval Timer
Serial I/O Interrupt

C Interrupt

RESET

INT0
OSD
INT1
INT2

Timer 0
Timer 2
1Frame

VSync

Timer 1
Timer 3

INTV(INT3/4)

WDT

BIT

SIO

I2C

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

Bit No.

Name

Value

Function

5,4

IM1~0

00
01

Mode 0: H/W priority
Mode 1: S/W priority
Interrupt is disabled, even
if IE is set.

3~0

IP3~0

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

INT0
OSD
INT1
INT2
Timer 0
Timer 2
1Frame
VSync
Timer 1
Timer 3
INTV(INT3/4)
WDT
BIT
SIO
I2C
Not used

Table 19-1 Bit function

IMOD

ADDRESS : 00F3

RESET VALUE : Undefined

IM0

IP3

IP2

IP1

IP0

IM1

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

Interrupt enable registers are shown in Figure 19-4 . These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is "0", a corre-

sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.

Figure 19-3 Interrupt Request Flags

INT2

R/W

INT0

VSync interrupt request flag

INITIAL VALUE: 0000 0000

ADDRESS: 00F7

IRQH

OSD

MSB

LSB

1Frame VSync

INT1

R/W

WDT

R/W

INITIAL VALUE: 0000 000-

ADDRESS: 00F5

IRQL

MSB

I2C

BIT

INTV

R/W

1 Frame interrupt request flag

Timer / Counter 2 interrupt request flag

Timer / Counter 0 interrupt request flag

External interrupt 2 interrupt request flag

External interrupt 1 interrupt request flag

On screen display interrupt request flag

External interrupt 0 interrupt request flag

C interrupt request flag

LSB

Serial I/O interrupt request flag

Basic interval timer interrupt request flag

Watch-dog timer interrupt request flag

Interrupt interval measurement interrupt request flag (INT3/4)

Timer / Counter 3 interrupt request flag

Timer / Counter 1 interrupt request flag

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

19.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an in-
struction. Interrupt acceptance sequence requires 8 f

s at f

MAIN

=4MHz) after the completion of the current in-

struction execution. The interrupt service task terminates
upon execution of an interrupt return instruction [RETI].

Interrupt acceptance

Figure 19-5 Interrupt Service routine Entering Timing

1. The interrupt master enable flag (I-flag) is cleared to

"0" to temporarily disable the acceptance of any fol-
lowing maskable interrupts. When a non-maskable in-
terrupt is accepted, the acceptance of any following
interrupts is temporarily disabled.

2. Interrupt request flag for the interrupt source accepted

is cleared to "0".

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto
the stack area. The stack pointer decrements 3 times.

4. The entry address of the interrupt service program is

read from the vector table address, and the entry ad-
dress is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

V.L.

System clock

Address Bus

SP-1

SP-2

V.H.

New PC

V.L.

Data Bus

Not used

PCH

PCL

PSW

ADL

OP code

ADH

Instruction Fetch

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.

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GMS81C4040/87C4060

May. 2000 Ver 1.0

A maskable interrupt is not accepted until the I-flag is set
to "1" even if a maskable interrupt of higher priority than
that of the current interrupt being serviced.

When nested interrupt service is necessary, the I-flag is set
to "1" in the interrupt service program. In this case, accept-
able interrupt sources are selectively enabled by the indi-
vidual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but not the accumulator and other reg-
isters. These registers are saved by the program if neces-
sary. Also, when nesting multiple interrupt services, it is
necessary to avoid using the same data memory area for
saving registers.

The following method is used to save/restore the general-
purpose registers.

Example: Register save using push and pop instructions

General-purpose register save/restore using push and pop
instructions;

19.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction,
which is the lowest priority order.

Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin-
guish BRK from TCALL 0.

Each processing step is determined by B-flag as shown in
Figure 19-6 .

Figure 19-6 Execution of BRK/TCALL0

INTxx:

PUSH

LDA

DPGR

PUSH

;SAVE ACC.
;SAVE X REG.
;SAVE DPGR
; Direct page
; accessable reg.
;

interrupt processing

POP

STA

DPGR

POP

RETI

;RESTORE DPGR
;RESTORE X REG.
;RESTORE ACC.
;RETURN

Basic Interval Timer

012

0E3

0FFE6

0FFE7

0E312

0E313

Entry Address

Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.

Vector Table Address

main task

interrupt
service task

saving
registers

restoring
registers

acceptance of
interrupt

interrupt return

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

TCALL0

ROUTINE

RET

BRK or

TCALL0

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

19.3 Multi Interrupt

If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the same priority level are received
simultaneously, an internal polling sequence determines
by hardware which request is serviced.

Figure 19-7 Execution of Multi Interrupt

However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user set I-flag in interrupt routine, some further interrupt
can be serviced even if certain interrupt is in progress.

Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.

TIMER1:

PUSH

LDM

IENH,#80H

;

Enable INT0 only

LDM

IENL,#0

;

Disable other

;

Enable Interrupt

:
:
:

:
:
:
LDM

IENH,#FFH

;

Enable all interrupts

LDM

IENL,#FEH

POP

RETI

enable INT0

TIMER 1
service

INT0
service

Main Program
service

Occur
TIMER1 interrupt

Occur
INT0

disable other

enable INT0
enable other

In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

19.4 External Interrupt

The external interrupt on INT0, INT1... pins are edge trig-
gered depending the edge selection register.

Refer to "6. PORT STRUCTURES" on page 9.

The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, both edge.

Figure 19-8 External Interrupt Block Diagram

INT0, INT1 and INT2 are multiplexed with general I/O
ports. To use external interrupt pin, the bit of port function
register FUNC1 should be set to "1" correspondingly.

Response Time

The INT0, INT1 and INT2 edge are latched into INT0IF,
INT1IF and INT2IF at every machine cycle. The values
are not actually polled by the circuitry until the next ma-
chine cycle. If a request is active and conditions are right
for it to be acknowledged, a hardware subroutine call to the
requested service routine will be the next instruction to be
executed. For example, the DIV instruction takes twelve
machine cycles. Thus, a minimum of twelve complete ma-
chine cycles elapse between activation of an external inter-
rupt request and the beginning of execution of the first
instruction of the service routine

Figure 19-9 Interrupt Response Timing Diagram ( Interrupt overhead )

INT0IF

INT0 pin

INT0 INTERRUPT

INT1IF

INT1 pin

INT1 INTERRUPT

INT2IF

INT2 pin

INT2 INTERRUPT

IEDS

[00F2

]

edge s

l
e

t
i
o

System clock

Instruction Fetch

Last instruction execution (0~12cycle)

Enter interrupt service routine (8cycle)

Interrupt request sampling

1cycle

Interrupt overhaed (9~21cycle)

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

20. WATCHDOG TIMER

The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re-
sumes the CPU to the normal state.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.

When the watchdog timer is not being used for malfunc-
tion detection, it can be used as a timer to generate an in-
terrupt at fixed intervals.

Figure 20-1 Block Diagram of Watchdog Timer

Watchdog Timer Control

Figure 20-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.

The CPU malfunction is detected as setting the detection
time, selecting output, and clearing the binary counter. Re-
peatedly clearing the binary counter within the setting de-
tection time.

If the malfunction occurs for any cause, the watchdog tim-
er output will become active at the rising overflow from
the binary counters unless the binary counter are cleared.
At this time, when WDTON=1 a reset is generated, which
drives the RESET pin low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (IFWDT) is
generated.

Figure 20-2 Watchdog timer register

to reset CPU

WDTR

Watchdog Timer Register

(BIT overflow : IFBIT)

Clock source

6-bit up-counter

enable

WDT

6-bit compare data

comparator

WDTR[bit5~0]

Watchdog Timer interrupt

WDTCL[bit6]

clear

[00D7

]

IFWDT

CKCTLR

Clock control Register

[00D6

]

WDTON[bit5]

CKTCLR

ADDRESS : 00D6

RESET VALUE : 0000 0000

WDT

ENP BTCL BTS2 BTS1 BTS0

Watchdog timer On/Off control

WDTR

ADDRESS : 00D7

RESET VALUE : -011 1111

WDT

W D T R 5 ~ 0

Slave address

0: Normal 6bit timer, Watchdog off
1: Watchdog timer

Watchdog timer Clear
0: Watchdog timer free run
1: Watchdog timer clear and free run

Automatically cleared this bit after 1cycle

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

Example: Sets the watchdog timer detection time

Enable and Disable Watchdog

Watchdog timer is enabled by setting WDTON (bit 5 in
CKTCLR) to "1". WDTON is initialized to "0" during re-
set, WDTON should be set to "1" to operate after reset is
released.

Example: Enables watchdog timer reset

:
LDM

CKTCLR,#001?????b ;WDTON

:
:

The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKTCLR.

Watchdog Timer Interrupt

The watchdog timer can also be used as a simple 6-bit tim-
er by clearing bit 5 (WDTON) of CKTCLR. The interval
of watchdog timer interrupt is decided by Basic Interval
Timer.

Interval equation is shown as below.

The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.

Example: 6-bit timer interrupt setting up.

LDX

#03FH

TXSP

;SP

LDM

CKTCLR,#000?????b ;WDTON

LDM

WDTR,#01??????b ;WDTCL

:
:

Refer table and see BIT timer ().

LDM

WDTR,#01??????b

;

Clear Counter and set value(??????b)

;

You have to set WDTR first, for prevent unpredictable interrupt

;

when you set WDTON bit.

LDM

CKCTLR,#00111???b

;

Select clock source(???b)

and WDTON=1

LDM

WDTR,#01??????b

;

Clear counter

:
:
:
:
LDM

WDTR,#01??????b

;

Clear counter

:
:
:
:
LDM

WDTR,#01??????b

;

Clear counter

Within WDT
detection time

CKCTLR

BTS2~0

BIT input

clock

Watchdog

timer input

clock

IFWDT cycle

000

PS4 (2uS)

512uS

32,256uS

001

PS5 (4uS)

1,024uS

64,512uS

010

PS6 (8uS)

2,048uS

129,024uS

011

PS7 (16uS)

4,096uS

258,048uS

100

PS8 (32uS)

8,192uS

516,096uS

101

PS9 (64uS)

16,384uS

1,032,192uS

110

PS10 (128uS)

32,768uS

2,064,384uS

111

PS11 (256uS)

65,536uS

4,128,768uS

Table 20-1 Watchdog timer MAX. cycle (Ex:f

=8MHz)

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

21. OSCILLATOR CIRCUIT

The GMS81C4040/GMS87C4060 has two oscillation cir-
cuits internally. X

and X

OUT

are input and output for

main frequency and OSC1 and OSC2 are input and output

for OSD(On Screen display) frequency, respectively, of a
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 21-1 .

Figure 21-1 Oscillation Circuit

Oscillation components have their own characteristics, so
user should consult the component manufacturers for ap-
propriate values of external components.

In addition, see Figure 21-2 for the layout of the crystal.

Note: Minimize the wiring length. Do not allow wiring to in-
tersect with other signal conductors. Do not allow wiring to
come near changing high current. Set the potential of the
grounding position of the oscillator capacitor to that of V

Do not ground to any ground pattern where high current is
present. Do not fetch signals from the oscillator.

Figure 21-2 Layout example of Oscillator PCB circuit

OUT

Recommend

OUT

External Clock

Open

External Oscillator

LC Oscillator

Crystal Oscillator

fc (MHz)

you have to tune the

For selection L,C value,

OSC2

OSC1

frequency to appropriate

range which is dependent
to your target set.

fc (MHz)

C1 & C2 (pF)

Recommend

fc (MHz)

C1 & C2 (pF)

L (uH)

100

OUT

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

22. RESET

The GMS81C4040/GMS87C4060 have two types of reset
generation procedures; one is an external reset input, other

is a watch-dog timer reset. Table 22-1 shows on-chip hard-
ware initialization by reset action.

Table 22-1 Initializing Internal Status by Reset Action

22.1 External Reset Input

The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, a reset is ap-
plied and the internal state is initialized. After reset, 64ms
(at 4 MHz) add with 7 oscillator periods are required to
start execution as shown in Figure 22-2 .

Internal RAM is not affected by reset. When V

is turned

on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before reading or testing it.

When the RESET pin input goes high, the reset operation
is released and the program execution starts at the vector
address stored at addresses FFFE

- FFFF

A connecting for simple power-on-reset is shown in Figure
22-1 .

Figure 22-1 Simple Power-on-Reset Circuit

Figure 22-2 Timing Diagram after RESET

On-chip Hardware

Initial Value

On-chip Hardware

Initial Value

Program counter

(FFFF

) - (FFFE

)

Peripheral clock

Off

RAM page register

DPGR

Watchdog timer

Disable

G-flag of PSW

Control registers

Refer to Table 8-1 on page 22

RESET

GND

MCU

MAIN PROGRAM

Oscillator

pin)

FFFE FFFF

Stabilization Time

= 62.5mS at 4.19MHz

RESET

ADDRESS

DATA

Start

ADL

ADH

BUS

RESET Process Step

x 256

MAIN

1024

Fetch

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

23. OTP Programming

23.1 GMS87C4060 OTP Programming

You can burn out GMS87C4060 OTP through the general
Gang programmer using Intel 27010/C010 mode. In Dev-
leopment tool package auxiliary, GMS87C4060-to-27010/
C010 conversion socket is included. GMS87C4060 have
two ROM memory areas. One is Program ROM memory
and the other is Font ROM memory. Program ROM area is
from 1000h to FFFFh Font ROM area is from 10000h to
13FFFh. When you acquire new OTP, actually, the OTP is
not fully blank. The OPT have six test pattern in the OSD
Font ROM memory(see figure23-1). The test pattern are
written at 11FA0h ~ 11FFFh and 13FA0h ~ 13FFFh.

Note: DO NOT write any data in this area(11FA0h ~
11FFFh, 13FA0h ~ 13FFFh)

Blank Check

If you run blank check function of ROM writer, ROM
writer inform blank error because of test pattern. To avoid
this situation, you must run the blank check function sep-
eretely. For example, check OTP address rage of 1000h ~
11F9Fh at first. And then check OPT address range of
12000h ~ 13F9Fh. If you have ROM writer without partial
blank check function, please do not run blank check func-
tion.

Figure 23-1 GMS87C4060 OTP Memory Map

Program Writing

There are two kind of OTP file. One is program OTP

file(***.OTP) and the other is font OTP file(***.FNT).
You can make each file through ASMLINKER.exe and
OSDFONT.exe respectively. All OTP file is Motolora S-
format. You can burn the program file and font file respec-
tively or together. To burn program file and font file re-
spectively, refer following procedure

1. Make program OTP file and font OTP file repec-
tively.

2. Check whether six test pattern is included in font
OTP file(see below Six Text Pattern)

3. Burn program OTP file(Set chip target address
1000h ~ FFFFh)

4. Burn font OTP file(Set chip target address 10000h
~13FFFh)

Note: When you program the OTP file, DO NOT check the
blank. Because there are already written data(Six test pat-
tern / 11FA0h ~ 11FFFh, 13FA0h~13FFFh) It will occur
blank error

To burn program file and font file together, refer following
procedure

1. Add program OTP file and font OTP file

2. Check whether six test pattern is included in font
OTP file(see below Six Text Pattern)

3. Burn OTP file(Set chip target address 1000h ~
13FFFh)

About other details, refer ROM wirter manual.

Six Test Pattern

When you make font file through OSDFONT.exe, please
confirm whether six test pattern is included or not in char-
acter address 1FAh ~ 1FFh, To include six test patern, refer
following procedure.

1. Make Font file and save it to your PC

2. Reopen the font file and save it to your HDD once
again.

3. Then six test pattern will be included automatically.
(Character address 1FAh ~ 1FFh)

1000H

FFFFH

13FFFH

OSD Font
Memory

Program
Memory

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

24. Assemble mnemonics

24.1 Instruction Map

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

000

NOP

SET1

dp.bit

BBS

A.bit,rel

BBS

dp.bit,rel

ADC

#imm

ADC

dp+X

ADC

!abs

ASL

TCALL

SETA1

.bit

BIT

POP

PUSH

BRK

001

CLRC

SBC

#imm

SBC

dp+X

SBC

!abs

ROL

TCALL

CLRA1

.bit

COM

POP

PUSH

BRA

rel

010

CLRG

CMP

#imm

CMP

dp+X

CMP

!abs

LSR

TCALL

NOT1

M.bit

TST

POP

PUSH

PCALL

Upage

011

#imm

dp+X

!abs

ROR

TCALL

OR1

OR1B

CMPX

POP

PSW

PUSH

PSW

RET

100

CLRV

AND

#imm

AND

dp+X

AND

!abs

INC

TCALL

AND1

AND1B

CMPY

CBNE

dp+X

TXSP

INC

101

SETC

EOR

#imm

EOR

dp+X

EOR

!abs

DEC

TCALL

EOR1

EOR1B

DBNE

XMA

dp+X

TSPX

DEC

110

SETG

LDA

#imm

LDA

dp+X

LDA

!abs

TXA

LDY

TCALL

LDC

LDCB

LDX

dp+Y

XCN

DAS

111

LDM

dp,#imm

STA

dp+X

STA

!abs

TAX

STY

TCALL

STC

M.bit

STX

dp+Y

XAS

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

000

BPL

rel

CLR1

dp.bit

BBC

A.bit,rel

BBC

dp.bit,rel

ADC

{X}

ADC

!abs+Y

ADC

[dp+X]

ADC

[dp]+Y

ASL

!abs

ASL

dp+X

TCALL

JMP

!abs

BIT

!abs

ADDW

LDX

#imm

JMP

[!abs]

001

BVC

rel

SBC

{X}

SBC

!abs+Y

SBC

[dp+X]

SBC

[dp]+Y

ROL

!abs

ROL

dp+X

TCALL

CALL

!abs

TEST

!abs

SUBW

LDY

#imm

JMP

[dp]

010

BCC

rel

CMP

{X}

CMP

!abs+Y

CMP

[dp+X]

CMP

[dp]+Y

LSR

!abs

LSR

dp+X

TCALL

MUL

TCLR1

!abs

CMPW

CMPX

#imm

CALL

[dp]

011

BNE

rel

{X}

!abs+Y

[dp+X]

[dp]+Y

ROR

!abs

ROR

dp+X

TCALL

DBNE

CMPX

!abs

LDYA

CMPY

#imm

RETI

100

BMI

rel

AND

{X}

AND

!abs+Y

AND

[dp+X]

AND

[dp]+Y

INC

!abs

INC

dp+X

TCALL

DIV

CMPY

!abs

INCW

INC

TAY

101

BVS

rel

EOR

{X}

EOR

!abs+Y

EOR

[dp+X]

EOR

[dp]+Y

DEC

!abs

DEC

dp+X

TCALL

XMA

{X}

XMA

DECW

DEC

TYA

110

BCS

rel

LDA

{X}

LDA

!abs+Y

LDA

[dp+X]

LDA

[dp]+Y

LDY

!abs

LDY

dp+X

TCALL

LDA

{X}+

LDX

!abs

STYA

XAY

DAA

111

BEQ

rel

STA

{X}

STA

!abs+Y

STA

[dp+X]

STA

[dp]+Y

STY

!abs

STY

dp+X

TCALL

STA

{X}+

STX

!abs

CBNE

XYX

NOP

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

24.2 Alphabetic order table of instruction

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

ADC #imm

Add with carry.

NV - - H - ZC

ADC dp

A + (M) + C

ADC dp + X

ADC !abs

ADC !abs+Y

ADC [dp+X]

ADC [dp]+Y

ADC {X}

ADDW dp

16-bits add without carry : YA

YA + (dp+1)(dp)

NV - - H - ZC

AND #imm

Logical AND

N - - - - - Z -

AND dp

A ^ (M)

AND dp + X

AND !abs

AND !abs+Y

AND [dp+X]

AND [dp] + Y

AND {X}

AND1 M.bit

Bit AND C-flag : C

C ^ (M.bit)

- - - - - - - C

AND1B M.bit

Bit AND C-flag and NOT : C

C ^ ~(M.bit)

- - - - - - - C

ASL A

Arithmetic shift left

N - - - - - ZC

ASL dp

ASL dp + X

ASL !abs

BBC A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBC dp.bit,rel

5/7

if(bit) = 0, then PC

PC + rel

BBS A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBS dp.bit,rel

5/7

if(bit) = 1, then PC

PC + rel

BCC rel

2/4

Branch if carry bit clear :
if(C) = 0, then PC

PC + rel

MM - - - - Z -

BCS rel

2/4

Branch if carry bit set : If (C) =1, then PC

PC + rel

- - - - - - - -

BEQ rel

2/4

Branch if equal : if (Z) = 1, then PC

PC + rel

- - - - - - - -

BIT dp

Bit test A with memory :

MM - - - - Z -

BIT !abs

A ^ M, N

), V

)

BMI rel

2/4

Branch if munus : if (N) = 1, then PC

PC + rel

- - - - - - - -

BNE rel

2/4

Branch if not equal : if (Z) = 0, then PC

PC + rel

- - - - - - - -

BPL rel

2/4

Branch if not minus : if (N) = 0, then PC

PC + rel

- - - - - - - -

BRA rel

Branch always : PC

PC + rel

- - - - - - - -

BRK

Software interrupt:

- - - 1 - 0 - -

"1", M(SP)

(PC

), SP

SP - 1,

M(s)

(PC

), SP

S - 1, M(SP)

PSW,

SP - 1, PC

(0FFDE

), PC

(0FFDF

)

BVC rel

2/4

Branch if overflow bit clear :

- - - - - - - -

If (V) = 0, then PC

PC + rel

BVS rel

2/4

Branch if overflow bit set :

- - - - - - - -

If (V) = 1, then PC

PC + rel

CALL !abs

Subroutine call

- - - - - - - -

CALL [dp]

M(SP)

(PC

), SP

SP-1, M(SP)

(PC

), SP

SP-1

if !abs, PC

abs ; if [dp], PC

(dp), PC

(dp+1)

CBNE dp,rel

5/7

Compare and branch if not equal ;

- - - - - - - -

CBNE dp + X, rel

6/8

If A

(M), then PC

PC + rel.

CLR1 dp.bit

Clear bit : (M.bit)

"0"

- - - - - - - -

CLR1A A.bit

Clear A.bit : (A.bit)

"0"

- - - - - - - -

CLRC

Clear C-flag : C

"0"

- - - - - - - 0

CLRG

Clear G-flag : G

"0"

- - 0 - - - - -

C 7 6 5 4 3 2 1 0

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

CLRV

Clear V-flag : V

"0"

- 0 - - 0 - - -

CMP #imm

Compare accumulator contents with memory contents

N - - - - - ZC

CMP dp

A - (M)

CMP dp + X

CMP !abs

CMP !abs + Y

CMP [dp + X]

CMP [dp] + Y

CMP {X}

CMPW dp

Compare YA contents with memory pair contents :

N - - - - - ZC

YA - (dp+1)(dp)

CMPX #imm

Compare X contents with memory contents

N - - - - - ZC

CMPX dp

X - (M)

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

N - - - - - ZC

CMPY dp

Y - (M)

CMPY !abs

COM dp

1's complement : (dp)

~(dp)

N - - - - - Z -

DAA

Decimal adjust for addition

N - - - - - ZC

DAS

Decimal adjust for substraction

N - - - - - ZC

DBNE dp,rel

5/7

Decrement and branch if not equal :

- - - - - - - -

DBNE Y,rel

4/6

if (M)

0, then PC

PC + rel.

DEC A

Decrement

N - - - - - Z -

DEC dp

M - 1

DEC dp + X

DEC !abs

DEC X

DEC Y

DECW dp

Decrement memory pair : (dp+1)(dp)

{(dp+1)(dp)} - 1

N - - - - - Z -

Disable interrupts : I

"0"

- - - - - 0 - -

DIV

Divide : YA/A

Q:A, R:Y

NV - - H - Z -

Enable interrupts : I

"1"

- - - - - 1 - -

EOR #imm

Exclusive OR

N - - - - - Z -

EOR dp

(M)

EOR dp + X

EOR !abs

EOR !abs + Y

EOR [ dp + X]

EOR [dp] + Y

EOR {X}

EOR1 M.bit

Bit exclusive-OR C-flag : C

(M.bit)

- - - - - - - C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

(M.bit)

- - - - - - - C

INC A

Increment

N - - - - - ZC

INC dp

(M)

(M) + 1

N - - - - - Z -

INC dp + X

INC !abs

INC X

INC Y

INCW dp

Increment memory pair : (dp+1)(dp)

{(dp+1)(dp)} + 1

N - - - - - Z -

JMP !abs

Unconditional jump

- - - - - - - -

JMP [!abs]

jump address

JMP [dp]

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

LDA #imm

Load accumulator

N - - - - - Z -

100

LDA dp

(M)

101

LDA dp + X

102

LDA !abs

103

LDA !abs + Y

104

LDA [dp + X]

105

LDA [dp]+Y

106

LDA {X}

107

LDA {X}+

X-register auto-increment : A

(M), X

X + 1

108

LDC M.bit

Load C-flag : C

(M.bit)

- - - - - - - C

109

LDCB M.bit

Load C-flag with NOT : C

~(M.bit)

- - - - - - - C

110

LDM dp,#imm

Load memory with immediate data : (M)

imm

- - - - - - - -

111

LDX #imm

Load X-register

N - - - - - Z -

112

LDX dp

(M)

113

LDX dp + Y

114

LDX !abs

115

LDY #imm

Load X-register

N - - - - - Z -

116

LDY dp

(M)

117

LDY dp + Y

118

LDY !abs

119

LDYA dp

Load YA : YA

(dp+1)(dp)

N - - - - - Z -

120

LSR A

Logical shift right

N - - - - - ZC

121

LSR dp

122

LSR dp + X

123

LSR !abs

124

MUL

Multiply : YA

Y x A

N - - - - - Z -

125

NOP

00,FF

No operation

- - - - - - - -

126

NOT1 M.bit

Bit complement : (M.bit)

~(M.bit)

- - - - - - - -

127

OR #imm

Logical OR

N - - - - - Z -

128

OR dp

A V (M)

129

OR dp + X

130

OR !abs

131

OR !abs + Y

132

OR [dp +X}

133

OR [dp] + Y

134

OR {X}

135

OR1 M.bit

Bit OR C-flag : C

C V (M.bit)

- - - - - - - C

136

OR1B M.bit

Bit OR C-flag and NOT : C

C V ~(M.bit)

- - - - - - - C

137

PCALL

U-page call : M(SP)

(PC

), SP

SP -1,

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

(upage), PC

"OFF

138

POP A

Pop from stack

- - - - - - - -

139

POP X

SP + 1, Reg.

M(SP)

140

POP Y

141

POP PSW

(restored)

142

PUSH A

Push to stack

- - - - - - - -

143

PUSH X

M(SP)

Reg. SP

SP - 1

144

PUSH Y

145

PUSH PSW

146

RET

Return from subroutine :

- - - - - - - -

SP+1, PC

M(SP), SP

SP+1, PC

M(SP)

147

RETI

Return from interrupt :

(restored)

SP+1, PSW

M(SP), SP

SP+1,PC

M(SP),

SP+1, PC

M(SP)

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

7 6 5 4 3 2 1 0 C

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

148

ROL A

Rotate left through carry

N - - - - - ZC

149

ROL dp

150

ROL dp + X

151

ROL !abs

152

ROR A

Rotate right through carry

N - - - - - ZC

153

ROR dp

154

ROR dp + X

155

ROR !abs

156

SBC #imm

Substract with carry

NV - - HZC

157

SBC dp

A - (M) - ~(C)

158

SBC dp + X

159

SBC !abs

160

SBC !abs + Y

161

SBC [dp + X]

162

SBC [dp] + Y

163

SBC {X}

164

SET1 dp.bit

Set bit : (M.bit)

"1"

- - - - - - - -

165

SETA1 A.bit

Set A.bit : (A.bit)

"1"

- - - - - - - -

166

SETC

Set C-flag : C

"1"

- - - - - - - 1

167

SETG

Set G-flag : G

"1"

- - 1 - - - - -

168

STA dp

Store accumulator contents in memory

- - - - - - - -

169

STA dp + X

(M)

170

STA !abs

171

STA !abs + Y

172

STA [dp + X]

173

STA [dp] + Y

174

STA {X}

175

STA {X}+

X-register auto-increment : (M)

A, X

X + 1

176

STC M.bit

Store C-flag : (M.bit)

- - - - - - - -

177

STX dp

Store X-register contents in memory

- - - - - - - -

178

STX dp + Y

(M)

179

STX !abs

180

STY dp

Store Y-register contents in memory

- - - - - - - -

181

STY dp + X

(M)

182

STY !abs

183

STYA dp

Store YA : (dp+1)(dp)

- - - - - - - -

184

SUBW dp

16-bits substract without carry : YA

YA - (dp+1)(dp)

NV - - H - ZC

185

TAX

Transfer accumulator contents to X-register : X

N - - - - - Z -

186

TAY

Transfer accumulator contents to Y-register : Y

N - - - - - Z -

187

TCALL n

Table call :

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

M(SP)

(PC

), SP

SP -1

(Table vector L), PC

(Table vector H)

188

TCLR1 !abs

Test and clear bits with A :

N - - - - - Z -

A - (M), (M)

(M) ^ ~(A)

189

TSET1 !abs

Test and set bits with A :

N - - - - - Z -

A - (M), (M)

(M) V (A)

190

TSPX

Transfer stack-pointer contents to X-register : X

N - - - - - Z -

191

TST dp

Test memory contents for negative or zero : (dp) - 00

N - - - - - Z -

192

TXA

Transfer X-register contents to accumulator : A

N - - - - - Z -

193

TXSP

Transfer X-register contents to stack-pointer : SP

N - - - - - Z -

194

TYA

Transfer Y-register contents to accumulator : A

N - - - - - Z -

195

XAX

Exchange X-register contents with accumulator : X

- - - - - - - -

196

XAY

Exchange Y-register contents with accumulator : Y

- - - - - - - -

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

C 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 C

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

24.3 Instruction Table by Function

1. Arithmetic/Logic Operation

197

XCN

Exchange nibbles within the accumulator:

N - - - - - Z -

~ A

198

XMA dp

Exchange memory contents with accumulator

N - - - - - Z -

199

XMA dp + X

(M)

200

XMA {X}

201

XYX

Exchange X-register contents with Y-register : X

- - - - - - - -

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

ADC #imm

Add with carry.

NV - - H - ZC

ADC dp

A + (M) + C

ADC dp + X

ADC !abs

ADC !abs+Y

ADC [dp+X]

ADC [dp]+Y

ADC {X}

AND #imm

Logical AND

N - - - - - Z -

AND dp

A ^ (M)

AND dp + X

AND !abs

AND !abs+Y

AND [dp+X]

AND [dp] + Y

AND {X}

ASL A

Arithmetic shift left

N - - - - - ZC

ASL dp

ASL dp + X

ASL !abs

CMP #imm

Compare accumulator contents with memory contents

N - - - - - ZC

CMP dp

A - (M)

CMP dp + X

CMP !abs

CMP !abs + Y

CMP [dp + X]

CMP [dp] + Y

CMP {X}

CMPX #imm

Compare X contents with memory contents

N - - - - - ZC

CMPX dp

X - (M)

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

N - - - - - ZC

CMPY dp

Y - (M)

CMPY !abs

COM dp

1's complement : (dp)

~(dp)

N - - - - - Z -

DAA

Decimal adjust for addition

N - - - - - ZC

DAS

Decimal adjust for substraction

N - - - - - ZC

DEC A

Decrement

N - - - - - Z -

DEC dp

M - 1

DEC dp + X

DEC !abs

DEC X

DEC Y

C 7 6 5 4 3 2 1 0

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

DIV

Divide : YA/A

Q:A, R:Y

NV - - H - Z -

EOR #imm

Exclusive OR

N - - - - - Z -

EOR dp

(M)

EOR dp + X

EOR !abs

EOR !abs + Y

EOR [ dp + X]

EOR [dp] + Y

EOR {X}

INC A

Increment

N - - - - - ZC

INC dp

(M)

(M) + 1

N - - - - - Z -

INC dp + X

INC !abs

INC X

INC Y

LSR A

Logical shift right

N - - - - - ZC

LSR dp

LSR dp + X

LSR !abs

MUL

Multiply : YA

Y x A

N - - - - - Z -

OR #imm

Logical OR

N - - - - - Z -

OR dp

A V (M)

OR dp + X

OR !abs

OR !abs + Y

OR [dp +X}

OR [dp] + Y

OR {X}

ROL A

Rotate left through carry

N - - - - - ZC

ROL dp

ROL dp + X

ROL !abs

ROR A

Rotate right through carry

N - - - - - ZC

ROR dp

ROR dp + X

ROR !abs

SBC #imm

Substract with carry

NV - - HZC

SBC dp

A - (M) - ~(C)

SBC dp + X

SBC !abs

SBC !abs + Y

SBC [dp + X]

SBC [dp] + Y

SBC {X}

TST dp

Test memory contents for negative or zero : (dp) - 00

N - - - - - Z -

XCN

Exchange nibbles within the accumulator:

N - - - - - Z -

~ A

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

7 6 5 4 3 2 1 0 C

C 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 C

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

2. Register / Memory Operation

3. 16-Bit Operation

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

LDA #imm

Load accumulator

N - - - - - Z -

LDA dp

(M)

LDA dp + X

LDA !abs

LDA !abs + Y

LDA [dp + X]

LDA [dp]+Y

LDA {X}

LDA {X}+

X-register auto-increment : A

(M), X

X + 1

LDM dp,#imm

Load memory with immediate data : (M)

imm

- - - - - - - -

LDX #imm

Load X-register

N - - - - - Z -

LDX dp

(M)

LDX dp + Y

LDX !abs

LDY #imm

Load X-register

N - - - - - Z -

LDY dp

(M)

LDY dp + Y

LDY !abs

STA dp

Store accumulator contents in memory

- - - - - - - -

STA dp + X

(M)

STA !abs

STA !abs + Y

STA [dp + X]

STA [dp] + Y

STA {X}

STA {X}+

X-register auto-increment : (M)

A, X

X + 1

STX dp

Store X-register contents in memory

- - - - - - - -

STX dp + Y

(M)

STX !abs

STY dp

Store Y-register contents in memory

- - - - - - - -

STY dp + X

(M)

STY !abs

TAX

Transfer accumulator contents to X-register : X

N - - - - - Z -

TAY

Transfer accumulator contents to Y-register : Y

N - - - - - Z -

TSPX

Transfer stack-pointer contents to X-register : X

N - - - - - Z -

TXA

Transfer X-register contents to accumulator : A

N - - - - - Z -

TXSP

Transfer X-register contents to stack-pointer : SP

N - - - - - Z -

TYA

Transfer Y-register contents to accumulator : A

N - - - - - Z -

XAX

Exchange X-register contents with accumulator : X

- - - - - - - -

XAY

Exchange Y-register contents with accumulator : Y

- - - - - - - -

XMA dp

Exchange memory contents with accumulator

N - - - - - Z -

XMA dp + X

(M)

XMA {X}

XYX

Exchange X-register contents with Y-register : X

- - - - - - - -

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

ADDW dp

16-bits add without carry : YA

YA + (dp+1)(dp)

NV - - H - ZC

CMPW dp

Compare YA contents with memory pair contents :

N - - - - - ZC

YA - (dp+1)(dp)

DECW dp

Decrement memory pair : (dp+1)(dp)

{(dp+1)(dp)} - 1

N - - - - - Z -

INCW dp

Increment memory pair : (dp+1)(dp)

{(dp+1)(dp)} + 1

N - - - - - Z -

HYUNDAI

GMS81C4040/87C4060

May. 2000 Ver 1.0

4. Bit Manipulation

5. Branch / Jump Operation

LDYA dp

Load YA : YA

(dp+1)(dp)

N - - - - - Z -

STYA dp

Store YA : (dp+1)(dp)

- - - - - - - -

SUBW dp

16-bits substract without carry : YA

YA - (dp+1)(dp)

NV - - H - ZC

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

AND1 M.bit

Bit AND C-flag : C

C ^ (M.bit)

- - - - - - - C

AND1B M.bit

Bit AND C-flag and NOT : C

C ^ ~(M.bit)

- - - - - - - C

BIT dp

Bit test A with memory :

MM - - - - Z -

BIT !abs

A ^ M, N

), V

)

CLR1 dp.bit

Clear bit : (M.bit)

"0"

- - - - - - - -

CLR1A A.bit

Clear A.bit : (A.bit)

"0"

- - - - - - - -

CLRC

Clear C-flag : C

"0"

- - - - - - - 0

CLRG

Clear G-flag : G

"0"

- - 0 - - - - -

CLRV

Clear V-flag : V

"0"

- 0 - - 0 - - -

EOR1 M.bit

Bit exclusive-OR C-flag : C

(M.bit)

- - - - - - - C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

(M.bit)

- - - - - - - C

LDC M.bit

Load C-flag : C

(M.bit)

- - - - - - - C

LDCB M.bit

Load C-flag with NOT : C

~(M.bit)

- - - - - - - C

NOT1 M.bit

Bit complement : (M.bit)

~(M.bit)

- - - - - - - -

OR1 M.bit

Bit OR C-flag : C

C V (M.bit)

- - - - - - - C

OR1B M.bit

Bit OR C-flag and NOT : C

C V ~(M.bit)

- - - - - - - C

SET1 dp.bit

Set bit : (M.bit)

"1"

- - - - - - - -

SETA1 A.bit

Set A.bit : (A.bit)

"1"

- - - - - - - -

SETC

Set C-flag : C

"1"

- - - - - - - 1

SETG

Set G-flag : G

"1"

- - 1 - - - - -

STC M.bit

Store C-flag : (M.bit)

- - - - - - - -

TCLR1 !abs

Test and clear bits with A :

N - - - - - Z -

A - (M), (M)

(M) ^ ~(A)

TSET1 !abs

Test and set bits with A :

N - - - - - Z -

A - (M), (M)

(M) V (A)

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

BBC A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBC dp.bit,rel

5/7

if(bit) = 0, then PC

PC + rel

BBS A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBS dp.bit,rel

5/7

if(bit) = 1, then PC

PC + rel

BCC rel

2/4

Branch if carry bit clear :
if(C) = 0, then PC

PC + rel

MM - - - - Z -

BCS rel

2/4

Branch if carry bit set : If (C) =1, then PC

PC + rel

- - - - - - - -

BEQ rel

2/4

Branch if equal : if (Z) = 1, then PC

PC + rel

- - - - - - - -

BMI rel

2/4

Branch if munus : if (N) = 1, then PC

PC + rel

- - - - - - - -

BNE rel

2/4

Branch if not equal : if (Z) = 0, then PC

PC + rel

- - - - - - - -

BPL rel

2/4

Branch if not minus : if (N) = 0, then PC

PC + rel

- - - - - - - -

BRA rel

Branch always : PC

PC + rel

- - - - - - - -

BVC rel

2/4

Branch if overflow bit clear :

- - - - - - - -

If (V) = 0, then PC

PC + rel

BVS rel

2/4

Branch if overflow bit set :

- - - - - - - -

If (V) = 1, then PC

PC + rel

GMS81C4040/87C4060

HYUNDAI

May. 2000 Ver 1.0

6. Control Operation & etc.

CALL !abs

Subroutine call

- - - - - - - -

CALL [dp]

M(SP)

(PC

), SP

SP-1, M(SP)

(PC

), SP

SP-1

if !abs, PC

abs ; if [dp], PC

(dp), PC

(dp+1)

CBNE dp,rel

5/7

Compare and branch if not equal ;

- - - - - - - -

CBNE dp + X, rel

6/8

If A

(M), then PC

PC + rel.

DBNE dp,rel

5/7

Decrement and branch if not equal :

- - - - - - - -

DBNE Y,rel

4/6

if (M)

0, then PC

PC + rel.

JMP !abs

Unconditional jump

- - - - - - - -

JMP [!abs]

jump address

JMP [dp]

PCALL

U-page call : M(SP)

(PC

), SP

SP -1,

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

(upage), PC

"OFF

TCALL n

Table call :

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

M(SP)

(PC

), SP

SP -1

(Table vector L), PC

(Table vector H)

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

BRK

Software interrupt:

- - - 1 - 0 - -

"1", M(SP)

(PC

), SP

SP - 1,

M(s)

(PC

), SP

S - 1, M(SP)

PSW,

SP - 1, PC

(0FFDE

), PC

(0FFDF

)

Disable interrupts : I

"0"

- - - - - 0 - -

Enable interrupts : I

"1"

- - - - - 1 - -

NOP

No operation

- - - - - - - -

POP A

Pop from stack

- - - - - - - -

POP X

SP + 1, Reg.

M(SP)

POP Y

POP PSW

(restored)

PUSH A

Push to stack

- - - - - - - -

PUSH X

M(SP)

Reg. SP

SP - 1

PUSH Y

PUSH PSW

RET

Return from subroutine :

- - - - - - - -

SP+1, PC

M(SP), SP

SP+1, PC

M(SP)

RETI

Return from interrupt :

(restored)

SP+1, PSW

M(SP), SP

SP+1,PC

M(SP),

SP+1, PC

M(SP)

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81C40XX

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81C40XX