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GMS81C50 Series

CONTENTS

1. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. PIN ASSIGNMENT (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4. PACKAGE DIMENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1 28 SOP PIN DIMENSION (DIMENSIONS IN INCH) . . . . . . . . . . . . 7
4.2 28 Skinny DIP PIN DIMENSION (DIMENSIONS IN INCH) . . . . . . . 7
4.3 40 PDIP Pin Dimension (dimension in inch) . . . . . . . . . . . . . . . . . . . 8
4.4 44 PLCC Pin Dimension (dimension in mm) . . . . . . . . . . . . . . . . . . 8
4.5 44 QFP Pin Dimension (dimension in mm) . . . . . . . . . . . . . . . . . . . . 9

5. PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6. PORT STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.1 R0 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 R1 Ports (R10, R11, R12, R13, R14) . . . . . . . . . . . . . . . . . . . . . . . 12
6.3 R1 Ports (R15, R16, R17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4 R2, R3, R4 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.5 REMOUT Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.6 Xin, Xout Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.7 RESET Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.8 TEST Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1 Absolute maximum ratings ( Ta=25 'C) . . . . . . . . . . . . . . . . . . . . . 16
7.2 Recommended Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 DC characteristics (VDD=2.2~4.0, Vss=0, Ta=0~70 `C) . . . . . . . . 17
7.4 REMOUT Port Ioh characteristics graph . . . . . . . . . . . . . . . . . . . . 18
7.5 REMOUT port Iol characteristics graph . . . . . . . . . . . . . . . . . . . . . 18
7.6 AC characteristics (VDD=2.2~4.0V, Vss=0V, Ta=0~70'C) . . . . . . . 19

8. MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.4 Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

GMS81C50 Series

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9. I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.1 R0 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2 R1 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.3 R2 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10. CLOCK GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10.1 Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11. TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11.1 Basic Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2 Timer0, Timer1, Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12. INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12.1 Interrupt priority and sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2 INTERRUPT CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . 58
12.3 INTERRUPT ACCEPT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12.4 INTERRUPT PROCESSING SEQUENCE . . . . . . . . . . . . . . . . . . 60
12.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction) 61
12.6 MULTIPLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.7 Key Scan Input Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

13. WATCH DOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

13.1 Control of WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.2 WDT Interrupt Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

14. STANDBY FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

14.1 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.2 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.3 STANDBY MODE RELEASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14.4 RELEASE OPERATION OF STANDBY MODE . . . . . . . . . . . . . . 72

15. OSCILLATION CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

16. RESET FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

16.1 EXTERNAL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16.2 POWER ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16.3 Low Voltage Detection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16.4 Low Voltage Indicator Register (LVIR) . . . . . . . . . . . . . . . . . . . . . 79

HYUNDAI

GMS81C50 Series

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

FOR UR (Universal Remocon) & KEYBOARD

1. OVERVIEW

1.1 Description

The GMS81C50 Series is an advanced CMOS 8-bit microcontroller with 16K/24K/32K bytes of ROM. The device is one of
GMS800 family. The LG Semicon GMS81C50 Series is a powerful microcontroller which provides a highly flexible and
cost effective solution to many UR & Keyboard applications. The GMS81C50 Series provides the following standard fea-
tures: 16K/24K/32K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock circuitry. In addi-
tion, the GMS81C50 Series supports power saving modes to reduce power consumption.

1.2 Features

· Instruction Cycle Time:

- 1us at 4MHz

· Programmable I/O pins

· Operating Voltage

- 2.2 ~ 4.0 V @ 4MHz

· Timer

- Timer / Counter ......... 16 Bit * 1 ch
......... 8 Bit * 2 ch
- Basic Interval Timer ...... 8 Bit * 1 ch

- Watch Dog Timer ............ 6Bit * 1ch

· 8 Interrupt sources

* Nested Interrupt control is available.
- External input: 2
- Keyscan input
- Basic Interval Timer
- Watchdog timer
- Timer : 3

· Power On Reset

· Power saving Operation Modes

- STOP
- SLEEP

· Low Voltage Detection Circuit

· Watch Dog Timer Auto Start (During 1second

after Power on Reset)

1.3 Development Tools

The GMS81C50 Series is supported by a full-featured

Device Name

ROM Size

RAM Size

Package

GMS81C5016

16K Bytes

448 Bytes
( included

256 bytes

stack memory )

28 SOP

28 Skinny DIP

40 PDIP

44 PLCC

44 QFP

GMS81C5024

24K Bytes

GMS81C5032

32K Bytes

28 PIN

40 PIN

44 PIN

INPUT

OUTPUT

I/O

GMS81C50 Series

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3. PIN ASSIGNMENT (Top View)

R14/ EC

R03
R04
R05
R06
R07

VDD

XOUT

XIN

R11/ INT1

R12/ INT2

R13

TEST

R02

R01

R00

R10

RESET

R15/ T2

REMOUT

R16/ T1

R17/ T0

R24

VSS

R20

R21

R22

R23

40PDIP

R00

R01

R02

R03

R04

R05

R06

R07

R34

R35

VDD

R36

R37

XOUT

XIN

R10

R11/ INT1

R12/ INT2

R15 / T2

TEST

R14 / EC

R27

R26

R25

R24

R23

R22

R21

R20

VSS

R33

R32

R31

R30

REMOUT

R17 / T0

R16 / T1

RESET

R13

R40

GMS81C50 Series

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5. PIN FUNCTION

: Supply voltage.

: Circuit ground.

TEST: Used for shipping inspection of the IC. For normal
operation, it should be connected to V

RESET: Reset the MCU.

: Input to the inverting oscillator amplifier and input to

the internal main clock operating circuit.

OUT

: Output from the inverting oscillator amplifier.

R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

In addition, R1 serves the functions of the various follow-

ing special features.

R20~R22, R30~R37 : R2 & R3 is a 8-bit CMOS bidirec-
tional I/O port. Each pins 1 or 0 written to the their Port Di-
rection Register can be used as outputs or inputs.

R40 : R40 is 1-bit CMOS bidirectional I/O port. This pin 1
or 0 written to the its Port Direction Register can be used
as outputs or inputs.

Port pin

Alternate function

R11
R12
R14
R15
R16
R17

INT1 (External Interrupt input 1)
INT2 (External Interrupt input 2)
/EC (Event Counter input )
T2 (Timer / Counter input 2)
T1 (Timer / Counter input 1)
T0 (Timer / Counter input 0)

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GMS81C50 Series

PIN NAME

INPUT/

OUTPUT

Function

@ RESET @ STOP

R00

I/O

R01

R02

R03

R04

R05

R06

R07

R10

R11/INT1

R12/INT2

R13

R14/EC

R15/T2

R16/T1

R17/T0

R20

R21

R22

R23

R24

XIN

XOUT

REMOUT

RESET

TEST

VDD

I/O

- Each bit of the port can be

individually configured as an
input or an output by user software

- Push-pull output
- CMOS input with pull-up resistor

(can be selectable by user software)

- Can be programmable as Key

Scan Input or Open drain output

- Pull-ups are automatically
disabled at output mode

- Each bit of the port can be

individually configured as an
input or an output by user software

- CMOS input with pull-up resistor

(can be selectable by user software)

- Push-pull output
- Can be programmable as

Open drain output

- Direct Driving of LED(N-TR)
- Pull-ups are disabled at output

mode

Low

High

- Oscillator Input
- Oscillator Output

`L` output

`L` Output

- High Current Output

`L` level

state

of before

STOP

- Includes pull-up resistor

- Positive power supply

- Ground

Pin Numbers

28Pin

40PDIP 44PLCC

44QFP

R25

I/O

R26

I/O

R27

I/O

VSS

12,23,24

6,7,39

1,2.34

17,28,29

R30

R31

R32

R33

R34

I/O

INPUT

State

of before

STOP

R35

I/O

R36

I/O

R37

I/O

R40

I/O

GMS81C50 Series

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7. ELECTRICAL CHARACTERISTICS

7.1 Absolute maximum ratings ( Ta=25 'C)

Note: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in

the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability

7.2 Recommended Operating Ranges

Supply Voltage

Input Voltage

Output Voltage

Operating Temperature

Storage Temperature

Power Dissipation

VDD

Topr

Tstg

-0.3 ~ +7.0

-0.3 ~ VDD + 0.3

0 ~ 70

-65 ~ 150

700

-0.3 ~ VDD + 0.3

Parameter

Unit

Symbol

Rating

Supply Voltage

VDD

Operating Temperature

Topr

Oscillation Frequency

fXin

fXin = 4MHz

MHz

2.2

4.0

Parameter

Unit

Symbol

min.

Condition

typ.

max.

1.0

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GMS81C50 Series

7.6 AC characteristics (VDD=2.2~4.0V, Vss=0V, Ta=0~70'C)

(Continued)

Parameter

Symbol

Specification

Unit

min.

typ.

max.

No.

External clock input cycle time

System clock cycle time

tcp

Xin

250

500

1000

tsys

500

1000

2000

External clock pulse width High

tcpH

Xin

External clock pulse width Low

tcpL

Xin

External clock rising time

trcp

Xin

External clock falling time

tfcp

INT1~ INT2

interrupt pulse width High

tIH

tsys

INT1~ INT2

Interrupt pulse width Low

tIL

tsys

Reset input pulse width low

tRSTL

tsys

Event counter input pulse width high

tECH

tsys

RESET

Event counter input pulse width low

tECL

tsys

Event counter input pulse rising time

trEC

Event counter input pulse falling time

tfEC

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GMS81C50 Series

8. MEMORY ORGANIZATION

The GMS81C50 Series has separate address spaces for
Program memory, Data Memory and Display memory.
Program memory can only be read, not written to. It can be

up to 32K bytes of Program memory. Data memory can be
read and written to up to 448 bytes including the stack area.

8.1 Registers

This device has six registers that are the Program Counter
(PC), an Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.

Figure 8-1 Configuration of Registers

Accumulator:

The Accumulator is the 8-bit general purpose register, used
for data operation such as transfer, temporary saving, and
conditional judgement, etc. The Accumulator can be used
as a 16-bit register with Y Register as shown below.

In the case of multiplication instruction, execute as a mul-
tiplier register. After multiplication operation, the lower 8-
bit of the result enters. (Y*A => YA). In the case of divi-
sion instruction, execute as the lower 8-bit of dividend. Af-
ter division operation, quotient enters.

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers:

In the addressing mode which uses these index registers,
the register contents are added to the specified address,
which becomes the actual address. These modes are ex-
tremely effective for referencing subroutine tables and
memory tables. The index registers also have increment,
decrement, comparison and data transfer functions, and
they can be used as simple accumulators.

* X Register : In the case of division instruction, execute
as register.

* Y Register : In the case of 16-bit operation instruction,
execute as the upper 8-bit of YA. (16-bit accumulator). In
the case of multiplication instruction, execute as a multipli-
cand register. After multiplication operation, the upper 8-
bit of the result enters. In the case of division instruction,
execute as the upper 8-bit of dividend. After division oper-
ation, remains enters. Y register can be used as loop
counter of conditional branch command. (e.g.DBNE Y,
rel)

Stack Pointer:

The Stack Pointer is an 8-bit register used for occurrence
interrupts, calling out subroutines and PUSH, POP, RETI,
RET instruction. Stack Pointer identifies the location in the
stack to be accessed (save or restore).

Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost. The SP is post-decremented when a subrou-
tine call or a push instruction is executed, or when an inter-
rupt is accepted. The SP is pre-incremented when a return
or a pop instruction is executed.

The stack can be located at any position within 100

1FF

of the internal data memory. The SP is not initialized

by hardware, requiring to write the initial value (the loca-
tion with which the use of the stack starts) by using the ini-
tialization routine. Normally, the initial value of "FF

" is

ACCUMULATOR

X REGISTER

Y REGISTER

STACK POINTER

PROGRAM COUNTER

PROGRAM STATUS
WORD

PCL

PCH

PSW

Two 8-bit Registers can be used as a "YA" 16-bit Register

GMS81C50 Series

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used.

Figure 8-3 Stack Operation

Program Counter:

The Program Counter is a 16-bit wide which consists of
two 8-bit registers, PCH and PCL. This counter indicates
the address of the next instruction to be executed. In reset
state, the program counter has reset routine address
(PC

:0FF

, PC

:0FE

Program Status Word:

The Program Status Word (PSW) contains several bits that

reflect the current state of the CPU. The PSW is described
in Figure 8-4 . It contains the Negative flag, the Overflow
flag, the Break flag the Half Carry (for BCD operation),
the Interrupt enable flag, the Zero flag, and the Carry flag.

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.

Stack Address ( 100

~ 1FF

)

Hardware fixed

Caution:

The Stack Pointer must be initialized by software be-
cause its value is undefined after RESET.

Example: To initialize the SP

LDX

#0FFH

TXSP

; SP

At execution of
a CALL/TCALL/PCALL

PCL

PCH

01FF

SP after
execution

SP before
execution

01FD

01FE

01FD

01FC

01FF

Push
down

At acceptance
of interrupt

PCL

PCH

01FF

01FC

01FE

01FD

01FC

01FF

Push
down

PSW

At execution
of RET instruction

PCL

PCH

01FF

01FE

01FD

01FC

01FD

Pop
up

At execution
of RETI instruction

PCL

PCH

01FF

01FE

01FD

01FC

Pop
up

PSW

0100H

01FFH

Stack
depth

At execution
of PUSH instruction

01FF

01FE

01FD

01FC

01FF

Push
down

SP after
execution

SP before
execution

PUSH A (X,Y,PSW)

At execution
of POP instruction

01FF

01FE

01FD

01FC

01FE

Pop
up

POP A (X,Y,PSW)

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GMS81C50 Series

[Zero flag Z]

This flag is set when the result of an arithmetic operation
or data transfer is "0" and is cleared by any other result.

Figure 8-4 PSW (Program Status Word) Register

[Interrupt disable flag I]

This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to "0". This flag immedi-
ately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.

[Half carry flag H]

After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
dress.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In

the direct addressing mode, addressing area is from zero
page 00

to 0FF

when this flag is "0". If it is set to "1",

addressing area is 1 Page. It is set by SETG instruction and
cleared by CLRG.

[Overflow flag V]

This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
ceeds +127(7F

) or -128(80

). The CLRV instruction

clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.

NEGATIVE FLAG

MSB

LSB

RESET VALUE : 00

PSW

OVERFLOW FLAG

BRK FLAG

CARRY FLAG RECEIVES

ZERO FLAG

INTERRUPT ENABLE FLAG

CARRY OUT

HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS

SELECT DIRECT PAGE

when g=1, page is addressed by RPR

GMS81C50 Series

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8.2 Program Memory

A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 16K/24K/32K bytes pro-
gram memory space only physically implemented. Ac-
cessing a location above FFFF

will cause a wrap-around

to 0000

Figure 8-5 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFE

and FFFF

as shown in Figure 8-6 .

As shown in Figure 8-5 , each area is assigned a fixed lo-
cation in Program Memory. Program Memory area con-
tains the user program.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL in-
stead of 3 bytes CALL instruction. If it is frequently
called, it is more useful to save program byte length.

Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0

for TCALL15, 0FFC2

for

TCALL14, etc., as shown in Figure 8-7 .

Example: Usage of TCALL

The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to loca-
tion 0FFFA

. The interrupt service locations spaces 2-byte

interval: 0FFF8

and 0FFF9

for External Interrupt 1,

0FFFA

and 0FFFB

for External Interrupt 0, etc.

Any area from 0FF00

to 0FFFF

, if it is not going to be

used, its service location is available as general purpose
Program Memory.

Figure 8-6 Interrupt Vector Area

PROGRAM

MEMORY

TCALL

AREA

INTERRUPT

VECTOR AREA

8000H

FF00H

FFC0H

FFE0H

FFFFH

PCALL

AREA

U-PAGE

A000H

C000H

32KByte

24KByte

16KByte
Range

Range

LDA

#5
TCALL

0FH

;

1BYTE INSTR UCTIO N

;

INSTEAD O F 2 BYTES

;

NO R M AL C ALL

;
;TABLE CALL ROUTINE
;
FUNC_A:

LDA

LRG0

RET

;
FUNC_B:

LDA

LRG1

RET

;
;TABLE CALL ADD. AREA
;

ORG

0FFC0H

;

TCALL ADDRESS AREA

FUNC_A

FUNC_B

Address

Vector Area Memory

Basic Interval Timer Interrupt Vector Area

Timer2 Interrupt Vector Area

Timer0 Interrupt Vector Area

External Interrupt 2 Vector Area

Key Scan Interrupt Vector Area

RESET Vector Area

External Interrupt 1 Vector Area

Timer1 Interrupt Vector Area

Watch Dog Timer Interrupt Vector Area

"-" means reserved area.

NOTE:

0FFDE

S/W Interrupt Vector Area

HYUNDAI

GMS81C50 Series

Figure 8-7 PCALL and TCALL Memory Area

PCALL

rel

4F35

PCALL 35H

TCALL

TCALL

0FFC0

Address

Program Memory

0FF00

Address

PCALL Area Memory

0FFBF

PCALL Area

(192 Bytes)

* means that the BRK software interrupt is using
same address with TCALL0.

NOTE:

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

TCALL 8

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

0FF35H

0FF00H

0FFFFH

11111111 11010110

01001010

PC:

0FFD6H

0FF00H

0FFFFH

0FFD7H

0D125H

Reverse

GMS81C50 Series

HYUNDAI

Example: The usage software example of Vector address and the initialize part.

ORG

0FFE0H

NOT_USED

BIT_INT

; BIT

WDT_INT

; Watch Dog Timer

NOT_USED

TMR2_INT

; Timer-2

TMR1_INT

; Timer-1

TMR0_INT

; Timer-0

NOT_USED

;

INT2

; Int.2

INT1

; Int.1

KEY_INT

; Key Scan

NOT_USED

;

RESET

; Reset

ORG

08000H

;********************************************
;

MAIN PROGRAM

;********************************************
;
RESET:

;Disable All Interrupts

LDX

RAM_CLR:

LDA

;RAM Clear(!0000H->!00BFH)

STA

{X}+

CMPX

#0C0H

BNE

RAM_CLR

;

;
LDX

#03FH

;Stack Pointer Initialize

TXSP

LDM

R0, #0

;Normal Port 0

LDM

R0DD,#1000_0010B

;Normal Port Direction

LDM

PUR0,#1000_0010B

;Pull Up Selection Set

LDM

PMR0,#0000_0001B

;R0 port / int

:
:
LDM

PCOR,#1

;Enable Peripheral clock

:
:

HYUNDAI

GMS81C50 Series

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa-
ble. Data Memory is divided into 3 groups, a user RAM,
control registers, Stack.

Figure 8-8 Data Memory Map

User Memory

The GMS81C50 Series has 448

8 bits for the user mem-

ory (RAM).

Control Registers

The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0

to 0FF

Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.

More detailed informations of each register are explained
in each peripheral section.

Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write instruc-
tion. Use byte manipulation instruction.

Example; To write at CKCTLR

LDM

CLCTLR,#09H ;Divide ratio

Stack Area

The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.

When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.

The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-3 on page 22.

RAM

(192 Bytes)

CONTROL

REGISTERS

0000H

00BFH

00C0H

00FFH

0100H

01FFH

PAGE0

PAGE1

RAM (STACK)
(256 Bytes)

Address

Function Register

Read
Write

Symbol

RESET Value

00C0h

PORT R0 DATA REG.

R/W

undefined

00C1h

PORT R0 DATA DIRECTION REG.

R0DD

00000000b

00C2h

PORT R1 DATA REG.

R/W

undefined

00C3h

PORT R1 DATA DIRECTION REG.

R1DD

00000000b

00C4h

PORT R2 DATA REG.

R/W

undefined

00C5h

PORT R2 DATA DIRECTION REG.

R2DD

00000000b

00C6h

reserved

GMS81C50 Series

HYUNDAI

00C7h

CLOCK CONTROL REG.

CKCTLR

--110111b

BASIC INTERVAL REG.

BTR

undefined

00C8h

WATCH DOG TIMER REG.

WDTR

-0001111b

00C9h

PORT R1 MODE REG.

PMR1

00000000b

00CAh

INT. MODE REG.

R/W

IMOD

-0000000b

00CBh

EXT. INT. EDGE SELECTION

IEDS

00000000b

00CCh

INT. ENABLE REG. LOW

R/W

IENL

-00-----b

00CDh

INT. REQUEST FLAG REG. LOW

R/W

IRQL

-00-----b

00CEh

INT. ENABLE REG. HIGH

R/W

IENH

000-000-b

00CFh

INT. REQUEST FLAG REG. HIGH

R/W

IRQH

000-000-b

00D0h

TIMER0 (16bit) MODE REG.

R/W

TM0

00000000b

00D1h

TIMER1 (8bit) MODE REG.

R/W

TM1

00000000b

00D2h

TIMER2 (8bit) MODE REG.

R/W

TM2

00000000b

00D3h

TIMER0 HIGH-MSB DATA REG.

T0HMD

undefined

00D4h

TIMER0 HIGH-LSB DATA REG.

T0HLD

undefined

00D5h

TIMER0 LOW-MSB DATA REG.

T0LMD

undefined

TIMER0 HIGH-MSB COUNT REG.

undefined

00D6h

TIMER0 LOW-LSB DATA REG.

T0LLD

undefined

TIMER0 LOW-LSB COUNT REG.

undefined

00D7h

TIMER1 HIGH DATA REG.

T1HD

undefined

00D8h

TIMER1 LOW DATA REG.

T1LD

undefined

TIMER1 LOW COUNT REG.

undefined

00D9h

TIMER2 DATA REG.

T2DR

undefined

TIMER2 COUNT REG.

undefined

00DAh

TIMER0 / TIMER1 MODE REG.

R/W

TM01

00000000b

00DBh

Reserved

00DCh

STANDBY MODE RELEASE REG0

SMPR0

00000000b

00DDh

STANDBY MODE RELEASE REG0

SMPR1

00000000b

00DEh

PORT R1 OPEN DRAIN ASSIGN REG.

R1ODC

00000000b

00DFh

PORT R2 OPEN DRAIN ASSIGN REG.

R2ODC

00000000b

00E0h

PORT R3 OPEN DRAIN ASSIGN REG.

R3ODC

00000000b

00E1h

PORT R4 OPEN DRAIN ASSIGN REG.

R4ODC

- - - - - - - 0b

00E2h

Reserved

00E3h

Reserved

00E4h

PORT R0 OPEN DRAIN ASSIGN REG.

R0ODC

00000000b

00E5h

PORT R3 DATA REG.

R/W

undefined

00E6h

PORT R3 DATA DIRECTION REG.

R3DD

00000000b

HYUNDAI

GMS81C50 Series

00E7h

PORT R4 DATA REG.

R/W

- - - - - - - Xb

00E8h

PORT R4 DATA DIRECTION REG.

R4DD

- - - - - - - 0b

00E9h

Reserved

00EAh

Reserved

00EBh

Reserved

00ECh

Reserved

00EDh

Reserved

00EEh

Reserved

00EFh

LOW VOLTAGE INDICATION REG.

LVIR

- - - - - - 00b

00F0h

SLEEP MODE REG.

SLPM

- - - - - - - 0b

00F1h

Reserved

00F2

Reserved

00F3h

Reserved

00F4h

Reserved

00F5h

Reserved

00F6h

STANDBY RELEASE LEVEL CONT. REG. 0

SRLC0

00000000b

00F7h

STANDBY RELEASE LEVEL CONT. REG. 1

SRLC1

00000000b

00F8h

PORT R0 PULL-UP REG. CONT. REG.

R0PC

00000000b

00F9h

PORT R1 PULL-UP REG. CONT. REG.

R1PC

00000000b

00FAh

PORT R2 PULL-UP REG. CONT. REG.

R2PC

00000000b

00FBh

PORT R3 PULL-UP REG. CONT. REG.

R3PC

00000000b

00FCh

PORT R4 PULL-UP REG. CONT. REG.

R4PC

- - - - - - - 0b

00FDh

Reserved

00FEh

Reserved

00FFh

Reserved

GMS81C50 Series

HYUNDAI

8.4 Addressing Mode

The GMS81C50 Series uses six addressing modes;

· Register addressing

· Immediate addressing

· Direct page addressing

· Absolute addressing

· Indexed addressing

· Register-indirect addressing

(1) Register Addressing

(2) Immediate Addressing

#imm

In this mode, second byte (operand) is accessed as a data
immediately.

Example:

0435

ADC

#35H

When G-flag is 1, then RAM address is difined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.

Example: G=1, RPR=0CH

E45535

LDM

35H,#55H

(3) Direct Page Addressing

In this mode, a address is specified within direct page.

Example; G=0

C535

LDA

35H

RAM[35H]

(4) Absolute Addressing

!abs

Absolute addressing sets corresponding memory data to
Data , i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY

Example;

0735F0

ADC

!0F035H

ROM[0F035H]

A+35H+C

MEMORY

0F100

data

55H

data

0C35

0F102

0F101

data

0E551

data

0E550

0F100

data

0F035

0F102

0F101

A+data+C

address: 0F035

HYUNDAI

GMS81C50 Series

The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

regard-

less of G-flag and RPR.

983501

INC

!0135H

ROM[135H]

(5) Indexed Addressing

X indexed direct page (no offset)

{X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15

, G=1, RPR=01

LDA

{X}

;ACC

RAM[X].

X indexed direct page, auto increment

{X}+

In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.

LDA, STA

Example; G=0, X=35

LDA

{X}+

X indexed direct page (8 bit offset)

dp+X

This address value is the second byte (Operand) of com-
mand plus the data of

-register. And it assigns the mem-

ory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5

C645

LDA

45H+X

0F100

data

135

0F102

0F101

data+1

data

address: 0135

data

115

0E550

data

36H

data

0E551

data

0E550

45H+0F5H=13AH

GMS81C50 Series

HYUNDAI

Y indexed direct page (8 bit offset)

dp+Y

This address value is the second byte (Operand) of com-
mand plus the data of Y-register, which assigns Memory in
Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute

!abs+Y

Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify mem-
ory in whole area.

Example; Y=55

D500FA

LDA

!0FA00H+Y

(6) Indirect Addressing

Direct page indirect

[dp]

Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.

JMP, CALL

Example; G=0

3F35

JMP

[35H]

X indexed indirect

[dp+X]

Processes memory data as Data, assigned by 16-bit pair
m e m o r y w h i c h i s d e t e r m i n e d b y p a i r d a t a
[dp+X+1][dp+X] Operand plus

X-register data in Direct

page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10

1625

ADC

[25H+X]

0F100

data

0FA55

0FA00H+55H=0FA55H

0F102

0F101

jump to address 0E30A

0FA00

0E30A

0E005

0FA00

0E005

data

A + data + C

25 + X(10) = 35

HYUNDAI

GMS81C50 Series

Y indexed indirect

[dp]+Y

Processes momory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Di-
rect page

plus Y-register data.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, Y=10

1725

ADC

[25H]+Y

Absolute indirect

[!abs]

The program jumps to address specified by 16-bit absolute
address.

JMP

Example; G=0

1F25E0

JMP

[!0C025H]

0E005

+ Y(10) = 0E015

0FA00

0E015

data

A + data + C

0E025

jump to

0FA00

0E026

0E725

PROGRAM MEMORY

address 0E30A

GMS81C50 Series

HYUNDAI

9. I/O PORTS

The GMS81C50 Series has 33 I/O ports which are
PORT0(8 I/O), PORT1 (8 I/O), PORT2 (8 I/O), PORT3 (8
I/O), PORT4 (1 I/O). Pull-up resistor of each port can be
selectable by program. Each port contains data direction
register which controls I/O and data register which stores
port data.

9.1 R0 Ports

R0 is an 8-bit CMOS bidirectional I/O port (address
0C0

). Each I/O pin can independently used as an input or

an output through the R0DD register (address 0C1

R0 has internal pull-ups that is independently connected or
disconnected by R0PC. The control registers for R0 are
shown below.

(1) R0 I/O Data Direction Register (R0DD)

R0 I/O Data Direction Register (R0DD) is 8-bit register,
and can assign input state or output state to each bit. If
R0DD is ``1``, port R0 is in the output state, and if ``0``, it
is in the input state. R0DD is write-only register. Since
R0DD is initialized as ``00 h`` in reset state, the whole port
R0 becomes input state.

(2) R0 Data Register (R0)

R0 data register (R0) is 8-bit register to store data of port
R0. When set as the output state by R0DD, and data is writ-
ten in R0, data is outputted into R0 pin. When set as the in-
put state, input state of pin is read. The initial value of R0
is unknown in reset state.

(3) R0 Open drain Assign Register (R0ODC)

R0 Open Drain Assign Register (R0ODC) is 8bit register,
and can assign R0 port as open drain output port each bit,
if corresponding port is selected as output. If R0ODC is
selected as ``1``, port R0 is open drain output, and if select-
ed as ``0``, it is push-pull output. R0ODC is write-only
register and initialized as ``00 h`` in reset state.

(4) R0 Pull-up Resistor Control Register (R0PC)

R0 pull-up resistor control register (R0PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R0PC is selected as ``1``, pull-
up ia disabled and if selected as ``0``, it is enabled. R0PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if correspond-
ing port is selected as output.

9.2 R1 Ports

R1 is an 8-bit CMOS bidirectional I/O port (address
0C2

). Each I/O pin can independently used as an input or

an output through the R1DD register (address 0C3

R1 has internal pull-ups that is independently connected or
disconnected by register R1PC. The control registers for
R1 are shown below.

R0 Data Register (R/W)

ADDRESS : 0C0

RESET VALUE : Undefined

R07 R06 R05 R04 R03 R02 R01 R00

Port Direction

R0 Direction Register (W)

R0DD

ADDRESS : 0C1

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R0 Pull-up Selection Register (W)

R0PC

ADDRESS :0F8

RESET VALUE : 00

0: Without pull-up
1: With pull-up

Open drain select

R0 Open drain Assign Register (W)

R0ODC

ADDRESS :0E4

RESET VALUE : 00

0: Push-pull
1: Open drain

HYUNDAI

GMS81C50 Series

(1) R1 I/O Data Direction Register (R1DD)

R1 I/O Data Direction Register (R1DD) is 8-bit register,
and can assign input state or output state to each bit. If
R1DD is ``1``, port R1 is in the output state, and if ``0``, it
is in the input state. R1DD is write-only register. Since
R1DD is initialized as ``00 h`` in reset state, the whole port
R1 becomes input state.

(2) R1 Data Register (R1)

R1 data register (R1) is 8-bit register to store data of port
R1. When set as the output state by R1DD, and data is writ-
ten in R1, data is outputted into R1 pin. When set as the in-
put state, input state of pin is read. The initial value of R1
is unknown in reset state.

(3) R1 Mode Register (PMR1)

R1 Port Mode Register (PMR1) is 8-bit register, and can
assign the selection mode for each bit. When set as ``0``,
corresponding bit of PMR1 acts as port R1 selection mode,
and when set as ``1``, it becomes function selection mode.

PMR1 is write-only register and initialized as ``00 h`` in
reset state. Therefore, becomes Port selection mode. Port
R1 can be I/O port by manipulating each R1DD bit, if cor-
responding PMR1 bit is selected as ``0``.

Table 9-1

Selection mode of PMR1

(4) R1 Pull-up Resistor Control Register (R1PC)

R1 pull-up resistor control register (R1PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R1PC is selected as ``1``, pull-
up ia disabled and if selected as ``0``, it is enabled. R1PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if correspond-
ing port is selected as output.

R1 Data Register (R/W)

ADDRESS : 0C2

RESET VALUE : Undefined

R17 R16 R15 R14 R13 R12 R11 R10

Port Direction

R1 Direction Register (W)

R1DD

ADDRESS : 0C3

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R1 Pull-up Selection Register (W)

R1PC

ADDRESS : 0F9

RESET VALUE : 00

0: Without pull-up
1: With pull-up

Open drain select

R1 Open drain Assign Register (W)

P1ODC

ADDRESS : 0DE

RESET VALUE : 00

0: Push-pull
1: Open drain

Mode select

R1 Port Mode Register (W)

PMR1

ADDRESS : 0C9

RESET VALUE : 00

0: Port R1 selection
1: Function selection

Pin Name

PMR1

Selection

Mode

Remarks

T0S

R17 (I/O)

T0 (O)

Timer0

T1S

R16 (I/O)

T1 (O)

Timer1

T2S

R15 (I/O)

T2 (O)

Timer2

ECS

R14 (I/O)

/EC (I)

Timer0 Event

INT2S

R12 (I/O)

INT2 (I)

Timer0 Input

Capture

INT1S

R11 (I/O)

INT1 (I)

GMS81C50 Series

HYUNDAI

9.3 R2 Port

R2 is an 8-bit CMOS bidirectional I/O port (address
0C4

). Each I/O pin can independently used as an input or

an output through the R2DD register (address 0C5

R2 has internal pujll-ups that is independently connected
or disconnected by R2PC (address 0FA

). The control reg-

isters for R2 are shown as below.

(1) R2 I/O Data Direction Register (R2DD)

R2 I/O Data Direction Register (R2DD) is 8-bit register,
and can assign input state or output state to each bit. If
R2DD is ``1``, port R2 is in the output state, and if ``0``, it
is in the input state. R2DD is write-only register. Since
R2DD is initialized as ``00 h`` in reset state, the whole port
R2 becomes input state.

(2) R2 Data Register (R2)

R2 data register (R2) is 8-bit register to store data of port
R2. When set as the output state by R2DD, and data is writ-
ten in R2, data is outputted into R2 pin. When set as the in-
put state, input state of pin is read. The initial value of R2
is unknown in reset state.

(3) R2 Open drain Assign Register (R2ODC)

R2 Open Drain Assign Register (R2ODC) is 8bit register,
and can assign R2 port as open drain output port each bit,
if corresponding port is selected as output. If R2ODC is
selected as ``1``, port R2 is open drain output, and if select-
ed as ``0``, it is push-pull output. R2ODC is write-only
register and initialized as ``00 h`` in reset state.

(4) R2 Pull-up Resistor Control Register (R2PC)

R2 pull-up resistor control register (R2PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R2PC is selected as ``1``, pull-
up ia disabled and if selected as ``0``, it is enabled. R2PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if correspond-
ing port is selected as output.

R2 Data Register (R/W)

ADDRESS : 0C4

RESET VALUE : Undefined

R27 R26 R25 R24 R23 R22 R21 R20

Port Direction

R2 Direction Register (W)

R2DD

ADDRESS : 0C5

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R2 Pull-up Selection Register (W)

R2PC

ADDRESS :0FA

RESET VALUE : 00

0: Without pull-up
1: With pull-up

Open drain select

R2 Open drain Assign Register (W)

R2ODC

ADDRESS :0DF

RESET VALUE : 00

0: Push-pull
1: Open drain

HYUNDAI

GMS81C50 Series

R3 Port

R3 is an 8-bit CMOS bidirectional I/O port (address
0E5

). Each I/O pin can independently used as an input or

an output through the R3DD register (address 0E6

R3 has internal pull-ups that is independently connected or
disconnected by R3PC (address 0FB

). The control regis-

ters for R3 are shown as below.

(1) R3 I/O Data Direction Register (R3DD)

R3 I/O Data Direction Register (R3DD) is 8-bit register,
and can assign input state or output state to each bit. If
R3DD is ``1``, port R3 is in the output state, and if ``0``, it
is in the input state. R3DD is write-only register. Since
R3DD is initialized as ``00 h`` in reset state, the whole port
R3 becomes input state.

(2) R3 Data Register (R3)

R3 data register (R3) is 8-bit register to store data of port
R3. When set as the output state by R3DD, and data is writ-
ten in R3, data is outputted into R3 pin. When set as the in-
put state, input state of pin is read. The initial value of R3
is unknown in reset state.

(3) R3 Open drain Assign Register (R3ODC)

R3 Open Drain Assign Register (R3ODC) is 8bit register,
and can assign R3 port as open drain output port each bit,
if corresponding port is selected as output. If R3ODC is
selected as ``1``, port R3 is open drain output, and if select-
ed as ``0``, it is push-pull output. R3ODC is write-only
register and initialized as ``00 h`` in reset state.

(4) R3 Pull-up Resistor Control Register (R3PC)

R3 pull-up resistor control register (R3PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R3PC is selected as ``1``, pull-
up ia disabled and if selected as ``0``, it is enabled. R3PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if correspond-
ing port is selected as output.

R3 Data Register (R/W)

ADDRESS : 0E5

RESET VALUE : Undefined

R37 R36 R35 R34 R33 R32 R31 R30

Port Direction

R3 Direction Register (W)

R3DD

ADDRESS : 0E6

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R3 Pull-up Selection Register (W)

R3PC

ADDRESS :0FB

RESET VALUE : 00

0: Without pull-up
1: With pull-up

Open drain select

R3 Open drain Assign Register (W)

R3ODC

ADDRESS :0E0

RESET VALUE : 00

0: Push-pull
1: Open drain

GMS81C50 Series

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R4 Port

R4 is an 1-bit CMOS bidirectional I/O port (address
0E7

). Each I/O pin can independently used as an input or

an output through the R4DD register (address 0E8

R3 has internal pull-ups that is independently connected or
disconnected by R4PC (address 0FC

). The control regis-

ters for R4 are shown as below.

(1) R4 I/O Data Direction Register (R4DD)

R4 I/O Data Direction Register (R4DD) is 1-bit register,
and can assign input state or output state to each bit. If
R4DD is ``1``, port R4 is in the output state, and if ``0``, it
is in the input state. R4DD is write-only register. Since
R4DD is initialized as ``00 h`` in reset state, the whole port
R4 becomes input state.

(2) R4 Data Register (R4)

R4 data register (R4) is 1-bit register to store data of port
R4. When set as the output state by R4DD, and data is writ-
ten in R4, data is outputted into R4 pin. When set as the in-
put state, input state of pin is read. The initial value of R4
is unknown in reset state.

(3) R4 Open drain Assign Register (R4ODC)

R4 Open Drain Assign Register (R4ODC) is 1-bit register,
and can assign R4 port as open drain output port each bit,
if corresponding port is selected as output. If R4ODC is
selected as ``1``, port R4 is open drain output, and if select-
ed as ``0``, it is push-pull output. R4ODC is write-only
register and initialized as ``00 h`` in reset state.

(4) R4 Pull-up Resistor Control Register (R4PC)

R4 pull-up resistor control register (R4PC) is 1-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R4PC is selected as ``1``, pull-
up ia disabled and if selected as ``0``, it is enabled. R4PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if correspond-
ing port is selected as output.

R4 Data Register (R/W)

ADDRESS : 0E7

RESET VALUE : Undefined

R40

Port Direction

R4 Direction Register (W)

R4DD

ADDRESS : 0E8

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R4 Pull-up Selection Register (W)

R4PC

ADDRESS :0FC

RESET VALUE : 00

0: Without pull-up
1: With pull-up

Open drain select

R4 Open drain Assign Register (W)

R4ODC

ADDRESS :0E1

RESET VALUE : 00

0: Push-pull
1: Open drain

HYUNDAI

GMS81C50 Series

10. CLOCK GENERATOR

Clock generating circuit consists of Clock Pulse Generator
(C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch

Dog Timer. The clock applied to the Xin pin divided by
two is used as the internal system clock.

Figure 10-1 Block Diagram of Clock Generator

Prescaler consists of 12-bit binary counter. The clock sup-
plied from oscillation circuit is input to prescaler (fex).

The divided output from each bit of prescaler is provided
to peripheral hardware.

Figure 10-2 Block diagram of Prescaler

PRESCALER

C.P.G

MUX

WDT (6)

COMPARATOR

Internal Data Bus

WDTON

To Reset

Circuit

IFWDT

WDTCL

IFBIT

fcpu

fex

PS1

ENPCK

Peripheral

CKCTLR

BTCL

OSC

Circuit

B.I.T (8)

WDTR

Internal System Clock

B.I.T

Peripheral

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS10 PS11

PS12

fex

ENPCK

fcpu

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS10

PS11

PS12

GMS81C50 Series

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Table 10-1 ps output period

Clock to peripheral hardware can be stopped by bit4 (EN-
PCK) of CKCTLR Register. ENPCK is set to ``1`` in reset

state.

Figure 10-3 Clock Control Register

fex (MHz)

4 MHz

2 MHz

frequency

period

frequency

period

ps 0
ps 1
ps 2
ps 3
ps 4
ps 5
ps 6
ps 7
ps 8
ps 9
ps 10
ps 11
ps 12

4 MHz
2 MHz
1 MHz

500 KHz
250 KHz
125 KHz

62.5 KHz

31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz

250 ns
500 ns

1 us
2 us
4 us
8 us

16 us
32 us
64 us

128 us
256 us
512 us

1024 us

2 MHz
1 MHz

500 KHz
250 KHz
125 KHz

62.5 KHz

31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz
0.488 KHz

500 ns

1 us
2 us
4 us
8 us

16 us
32 us
64 us

128 us
256 us
512 us

1024 us
2048 us

WDTON

ENPCK

BTCL

BTS2

BTS1

BTS0

W <00C7 h>

CKCTLR

Clock Control Register

ENPCK

Periphral clock

stopped

provided

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GMS81C50 Series

10.1 Operation Mode

The system clock controller starts or stops the main-fre-
quency clock oscillator. Figure 10-2 shows the operating
mode transition diagram.

Main-clock operating mode

This mode is fast-frequency operating mode.
The CPU and the peripheral hardwares are operated on the
high-frequency clock. At reset release, this mode is in-

voked.

STOP mode

In this mode, the system operations are all stopped, holding
the internal states valid immediately before the stop at the
low power consumption level

Figure 10-4 Operating Mode

STOP

Mode

RESET

Operation

Main: Stopped

Main: Oscillating

Main - Oscillating

NOTE:

Refer to 14.3 context

Reset

efe

r to

ote

SLEEP

Mode

Main

Operating

Reset

r t

egi

ster

ttin

Release

Instruction

GMS81C50 Series

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11. TIMER

11.1 Basic Interval Timer

The GMS81C50 Series has one 8-bit Basic Interval Timer
that is free-run and can not stop. Block diagram is shown
in Figure 11-1 .

The Basic Interval Timer generates the time base for key
scanning, watchdog timer counting, and etc. It also pro-
vides a Basic interval timer interrupt (IFBIT). As the count
overflow from FF

to 00

, this overflow causes the inter-

rupt to be generated.

-8bit binary counter

-Use the bit output of prescaler as input to secure the oscil-
lation stabilization time after power-on

-Secures the oscillation stabilization time in standby mode
(stop mode) release

-Contents of B.I.T can be read

-Provides the clock for watch dog timer.

Figure 11-1 Block Diagram of Basic Interval Timer

(1) Control of B.I.T

The Basic Interval Timer is controlled by the clock control
register (CKCTLR) shown in Figure 11-2 . If bit3(BTCL)
of CKCTLR is set to ``1``, B.I.T is cleared, and then, after

one machine cycle, BTCL becomes ``0``, and B.I.T starts
counting. BTCL is set to ``0`` in reset state.

MUX

BITR

IFBIT

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS10

DATA BUS

WDTON

ENPCK

BTCL

BTS2

BTS1

BTS0

CKCTLR

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

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GMS81C50 Series

Figure 11-2 BTCL mode of B.I.T

(2) Input clock selection of B.I.T

The input clock of B.I.T can be selected from the prescaler
within a range of 2us to 256us by clock input selection bits
(BTS2~BTS0). (at fex = 4MHz). In reset state, or power
on reset, BTS2=``1``, BTS1=``1``, BTS0=``1`` to secure
the longest oscillation stabilization time. B.I.T can gener-

ate the wide range of basic interval time interrupt request
(IFBIT) by selecting prescaler output. Interrupt interval
can be selected to kinds of interval time as shown in

Figure 11-3 .

Figure 11-3 Basic Interval Timer Interrupt Time

(3) Reading Basic Interval Timer

By reading of the Basic Interval Timer Register (BITR),
we can read counter value of B.I.T. Because B.I.T can be

cleared or read, the spending time up to maximum 65.5ms
can be available. B.I.T is read-only register. If B.I.T reg-

WDTON

ENPCK

BTCL

BTS2

BTS1

BTS0

W <00C7 h>

CKCTLR

Clock Control Register

BTCL

Periphral clock

free-run

Automatically cleared, after one cycle

512 us

1,024 us

2,048 us

4,096 us

8,192 us

16,384 us

32,768 us

65,536 us

WDTON

ENPCK

BTCL

BTS2

BTS1

BTS0

W <00C7 h>

CKCTLR

Clock Control Register

BTS0

B.I.T. Input clock

BTS1

BTS2

Standby release time

PS3 (2us)

PS4 (4us)

PS5 (8us)

PS6 (16us)

PS7 (32us)

PS8 (64us)

PS9 (128us)

PS10 (256us)

GMS81C50 Series

HYUNDAI

ister is written, then CKCTLR register with same address

is written.

11.2 Timer0, Timer1, Timer2

(1) Timer Operation Mode

Timer consists of 16bit binary counter Timer0 (T0), 8bit
binary Timer1 (T1), Timer2 (T2), Timer Data Register,
Timer Mode Register (TM01, TM0, TM1, TM2) and con-
trol circuit. Timer Data Register Consists of Timer0 High-
MSB Data Register (T0HMD), Timer0 High-LSB Data
Register (T0HLD), Timer0 Low-MSB Data Register
(T0LMD), Timer0 Low-LSB Data Register (T0LLD),

Timer1 High Data Register (T1HD), Timer1 Low Data
Register (T1LD), Timer2 Data Register (T2DR). Any of
the PS0 ~ PS5, PS11 and external event input EC can be
selected as clock source for T0. Any of the PS0 ~ PS3, PS7
~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12
can be selected as clock source for T2.

* Relevant Port Mode Register (PMR1 : 00C9 h) value
should be assigned for event counter,

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

R <00C7 h>

BITR

Basic Interval Timer Register

Timer0

- 16-bit Interval Timer
- 16-bit Event Counter
- 16-bit Input Capture
- 16-bit rectangular-wave output

- Single/Modulo-N Mode
- Timer Output Initial Value Setting
- Timer0~Timer1 combination Logic Output
- One Interrupt Generating Every 2nd
Counter Overflow

Timer1

- 8-bit Interval Timer
- 8-bit rectangular-wave output

Timer2

- 8-bit Interval Timer
- 8-bit rectangular-wave output
- Modulo-N Mode

HYUNDAI

GMS81C50 Series

Figure 11-4 Timer / Counter Block diagram

(2) Function of Timer & Counter

T2 OUT / R15

TIMER0 (16 BIT)

Polarity

Selection

T0HMD

T0HLD

T0LMD

T0LLD

Tout LOGIC

T1HD

T1LD

TIMER1 (8 BIT)

EDGE

Selection

T1 OUT / R16

REMOUT

T0 OUT / R17

EC / R14

INT2 / R12
(Capture
Signal)

TIMER2 (8 BIT)

T2DR

PS0 ( 0.25 us)

16,384 us

PS0 ( 0.25 us)

64 us

PS5 ( 8 us)

2.048 us

PS1 ( 0. 5 us)

32,768 us

PS1 ( 0.5 us)

128 us

PS6 ( 16 us)

4,096 us

PS2 ( 1 us)

65,536 us

PS2 ( 1 us)

256 us

PS7 ( 32 us)

8,192 us

PS3 ( 2 us)

131,072 us

PS3 ( 2 us)

512us

PS8 ( 64 us)

16,384 us

PS4 ( 4 us)

262,144 us

PS7 ( 32 us)

8,192 us

PS9 ( 128 us)

32,768 us

PS5 ( 8 us)

524,288 us

PS8 ( 64 us)

16,384 us

PS10 ( 256 us)

65,536 us

PS11 ( 512 us)

33,554,432 us

PS9 ( 128 us)

32,768 us

PS11 ( 512 us)

131,072 us

PS10 ( 256 us)

65,536 us

PS12 (1,024 us)

262,144 us

fex = 4MHz

16bit Timer (T0)

8bit Timer (T1)

8bit Timer (T2)

Resolution (CK)

Max. Count

Resolution (CK)

Max. Count

Resolution (CK)

Max. Count

HYUNDAI

GMS81C50 Series

Figure 11-8 Timer0 / Timer1 Mode Register

TOUTS

TOUTB

T0OUTP

T0INIT

T1INIT

TOUT1

TOUT0

R / W <00DA h>

TM01

Timer0 / Timer1 Mode Register

TOUT0

TOUT1

TOUT LOGIC

T1INIT

Timer1 Output Initial Value

T0INIT

T0OUTP

T0OUT Polarity Selection

TOUTB

REMOUT Port Bit Control

TOUTS

REMOUT Port Output Selection

(TOUT logic or TOUTB)

AND of T0 OUTPUT and T1 OUTPUT

NAND of T0 OUTPUT and T1 OUTPUT

OR of T0 OUTPUT and T1 OUTPUT

NOR of T0 OUTPUT and T1 OUTPUT

Timer1 output low

Timer1 output high

Timer0 Output Initial Value

Timer0 Output Low

Timer0 Output High

T0OUT polarity equal to TOUT logic input signal

T0OUT polarity reverse to TOUT logic input signal

REMOUT output low

REMOUT output high

Bit (TOUTB) output through REMOUT

TOUT logic output through REMOUT

GMS81C50 Series

HYUNDAI

Figure 11-9 Timer0 Mode Register

CAP0

T0ST

T0CN

T0MOD

T0IFS

T0SL2

T0SL1

T0SL0

R / W <00D0 h>

TM0

Timer0 Mode Register

T0SL2

T0SL1

Input clock selection

T0IFS

Timer0 Interrupt Selection

T0SL0

Notes

PS0 (250ns)

PS1 (500ns)

PS2 ( 1us)

PS3 ( 2us)

PS4 ( 4us)

PS5 ( 8us)

PS11 (512us)

Event

Counter

Interrupt every counter overflow

Interrupt every 2nd counter overflow

T0MOD

Timer0 Single/Modulo-N Selection

Modulo-N

Single

T0CN

Timer0 Counter Continuation/Pause Control

Count pause

Count contination

T0ST

Timer0 Start/Stop Control

Timer0 Stop

Timer Start after clear

CAP0

Timer0 Interrupt Selection

Timer/Counter

Input capture *

* PS1 : not supporting input capture.

HYUNDAI

GMS81C50 Series

Figure 11-10 Timer1 Mode Register

T1ST

T1CN

T1MOD

T1IFS

T1SL2

T1SL1

T1SL0

R / W <00D1 h>

TM1

Timer1 Mode Register

T1SL2

T1SL1

Input clock selection

T1IFS

Timer1 Interrupt Selection

T1SL0

PS0 (250ns)

PS1 (500ns)

PS2 ( 1us)

PS3 ( 2us)

PS7 ( 32us)

PS8 ( 64us)

PS9 (128us)

Interrupt every counter overflow

Interrupt every 2nd counter overflow

T1MOD

Timer1 Single/Modulo-N Selection

Modulo-N

Single

T1CN

Timer1 Counter Continuation/Pause Control

Count pause

Count contination

T1ST

Timer1 Start/Stop Control

Timer1 Stop

Timer1 Start after clear

PS10 (256us)

GMS81C50 Series

HYUNDAI

Figure 11-11 Timer2 Mode Register

Figure 11-12 External Interrupt Signal Edge Selection Register

T2ST

T2CN

T2SL2

T2SL1

T2SL0

R / W <00D2 h>

TM2

Timer2 Mode Register

T2SL2

T2SL1

Input clock selection

T2SL0

PS5 ( 8us)

PS6 ( 16us)

PS7 ( 32us)

PS8 ( 64us)

PS9 ( 128us)

PS10 ( 256us)

PS11 ( 512us)

T2CN

Timer2 Counter Continuation/Pause Control

Count pause

Count contination

T2ST

Timer2 Start/Stop Control

Timer2 Stop

Timer2 Start after clear

PS12 (1024us)

IED*H

IED*L

INT*

IED2H

IED2L

IED1H

IED1L

W <00CB h>

IEDS

External Interrupt Signal Edge Selection Register

Falling Edge Selection

Rising Edge Selection

Both Edge Selection

HYUNDAI

GMS81C50 Series

(3) Timer0, Timer1

TIMER0 and TIMER1 have an up-counter. When value of
the up-counter reaches the content of Timer Data Register

(TDR), the up-counter is cleared to ``00 h``, and interrupt
(IFT0, IFT1) is occured at the next clock.

Figure 11-13 Operatiion of Timer0

For Timer0, the internal clock (PS) and the external clock
(EC) can be selected as counter clock. But Timer1 and
Timer2 use only internal clock. As internal clock. Timer0
can be used as internal-timer which period is determined
by Timer Data Register (TDR). Chosen as external
clock, Timer0 executes as event-counter. The counter ex-
ecution of Timer0 and Timer1 is controlled by T0CN,
T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0
and TM1. T0CN, T1CN are used to stop and start Timer0
and Timer1 without clearing the counter. T0ST, T1ST is
used to clear the counter. For clearing and starting the
counter, T0ST or T1ST should be temporarily set to ``0``
and then set to ``1``. T0CN, T1CN, T0ST and T1ST
should be set ``1``, when Timer counting-up. Controlling
of CAP0 enables Timer0 as input capture. By program-
ming of CAP0 to ``1``, the period of signal from INT2 can
be measured and then, event counter value for INT2 can
be read. During counting-up, value of counter can be read.

Timer execution is stopped by the reset signal (RESET

= ``L``)

Note: In the process of reading 16-bit Timer Data, first
read the upper 8-bit data. Then read the lower 8-bit data,
and read the upper 8-bit data again. If the earlier read up-
per 8-bit data are matched with the later read upper 8-bit
data, read 16-bit data are correct. If not, caution should be
taken in the selection of upper 8-bit data.

(Example)

1) Upper 8-bit Read 0A 0A

2) Lower 8-bit Read FF 01

3) Upper 8-bit Read 0B 0B

=====================

- -

0AFF 0B01

Concurrence

CLEAR

T0 Data

Registers

Value

T0 Value

INTERRUPT

Interval period

IFT0

HYUNDAI

GMS81C50 Series

* Single/Modulo-N Mode

Timer0 (Timer1) can select initial (T0INIT, T1INIT of
TM01) output level of Timer Output port. If initial level is
``L``, Low-Data Register value of Timer Data Register is
transferred to comparator and T0OUT (T1OUT) is to be
``Low``, if initial level is High? High -Data Register is
transferred and to be ``High``. Single Mode can be set by
Mode Select bit (T0MOD, T1MOD) of Timer Mode Reg-
ister (TM0, TM1) to ``1`` When used as Single Mode,
Timer counts up and compares with value of Data Regis-
ter. If the result is same, Time Out interrupt occurs and
level of Timer Output port toggle, then counter stops as re-
set state. When used as Modulo-N Mode, T0MOD
(T1MOD) should be set ``0``. Counter counts up until the

value of Data Register and occurs Time-out interrupt. The
level of Timer Output port toggle and repeats process of

counting the value which is selected in Data Register.
During Modulo-N Mode, If interrupt select bit (T0IFS,
T1IFS) of Mode Register is ``0``, Interrupt occurs on ev-
ery Time-out. If it is ``1``, Interrupt occurs every second
time-out.

Note: (*note. Timer Output is toggled whenever time
out happen)

Figure 11-16 Operation Diagram for Single/Modulo-N Mode

(4) Timer 2

Timer2 operates as a up-counter. The content of T2DR are
compared with the contents of up-counter. If a match is
found. Timer2 interrupt (IFT2) is generated and the up-
counter is cleared to ``00 h``. Therefore, Timer2 executes
as a interval timer. Interrupt period is determined by the
count source clock for the Timer2 and content of T2DR.

When T2ST is set to ``1``, count value of Timer 2 is
cleared and starts counting-up. For clearing and starting
the Timer2. T2ST have to set to ``1`` after set to ``0``. In
order to write a value directly into the T2DR, T2ST should
be set to ``0``. Count value of Timer2 can be read at any
time.

8bit / 16bit
counting

Timer Enable initial.

value toggle.

Timer-output toggle.

interrupt occurs.

count stop.

Timer Enable initial.

value toggle.

Timer-Output Toggle.

Int occurs (IFS = 1) Each 2nd time out.

Int occurs (IFS = 0) When Time out.

[ Single Mode ]

[ Modulo-N Mode ]

HYUNDAI

GMS81C50 Series

12. INTERRUPTS

The GMS81C50 Series interrupt circuits consist of Inter-
rupt Mode Register (MOD), Interrupt enable register
(IENH, IENL), Interrupt request flags of IRQH, IRQL,
Priority circuit and Master enable flag ("I" flag of PSW). 8
interrupt sources are provided. The configuration of inter-
rupt circuit is shown in Figure 12-1 .

The GMS81C50 Series contains 8 interrupt sources; 3 ex-
ternals and 5 internals. Nested interrupt services with pri-
ority control is also possible. Software interrupt is non-
maskable interrupt, the others are all maskable interrupts.

- 8 interrupt source (2Ext, 3Timer, BIT, WDT and Key
Scan)

- 8 interrupt vector

- Nested interrupt control is possible

- Programmable interrupt mode

- Hardware accept mode

- Software selection accept mode

- Read and write of interrupt request flag are possible.

- In interrupt accept, request flag is automatically cleared.

Figure 12-1 Block Diagram of Interrupt

12.1 Interrupt priority and sources.

Each interrupt vector is independent and has its own prior-
ity. Software interrupt (BRK) is also available. Interrupt

source classification is shown in Table 12-1.

Internal Data Bus

KSCNR

INT1R

INT2R

T0R

T1R

T2R

WDTR

BITR

PRIORITY

CONTROL

IENL

IENH

IMOD

IRQ

KSCN

INT1

INT2

IFT0

IFT1

IFT2

IFWDT

IFBIT

INT.

VECTOR

ADDR.

BRK

Standby Mode Release

GMS81C50 Series

HYUNDAI

Table 12-1 Interrupt Priority & Source

12.2 INTERRUPT CONTROL REGISTER

I flag of PSW is a interrupt mask enable flag. When I flag
= ``0``, all interrupts become disable. When I flag = ``1``,
interrupts can be selectively enabled and disabled by con-
tents of corresponding Interrupt Enable Register. When in-
terrupt is occured, interrupt request flag is set, and
Interrupt request is detected at the edge of interrupt signal.
The accepted interrupt request flag is automatically cleared

during interrupt cycle process. The interrupt request flag
maintains ``1`` until the interrupt is accepted or is cleared
in program. In reset state, interrupt request flag register
(IRQH, IRQL) is cleared to ``0``. It is possible to read the
state of interrupt register and to mainpulate the contents of
register and to generate interrupt. (Refer to software inter-
rupt).

Mask

Priority

Interrupt Source

INT Vector High

INT Vector Low

Hardwar

Interrupt

INT2R (External Interrupt2)

non-maskable

maskable

INT1R (External Interrupt1)

WDTR (Watctdog Timer)

BITR (Basic Interval Timer)

RST (RESET pin)

KSCNR (Key Scan)

T0R (Timer0)

T1R (Timer1)

T2R (Timer2)

BRK instruction

FFFF

FFFE

FFFB

FFFA

FFF9

FFF8

FFF7

FFF6

FFF3

FFF2

FFF1

FFF0

FFEF

FFEE

FFE9

FFE8

FFE7

FFE6

FFDF

FFDE

WDTR

BITE

KSCNE

INT1E

INT2E

T0E

T1E

T2E

WDTR

BITE

KSCNE

INT1R

INT2R

T0R

T1R

T2R

IRQL

IRQH

R/W <00CFh>

R/W <00CDh>

R/W <00CEh>

R/W <00CCh>

IENH

IE N L

IENL : INTERRUPT ENABLE REGISTER LOW

IENH : INTERRUPT ENABLE REGISTER HIGH

IRQL : INTERRUPT REQUEST REGISTER LOW

IRQH : INTERRUPT REQUEST REGISTER HIGH

HYUNDAI

GMS81C50 Series

12.3 INTERRUPT ACCEPT MODE

The interrupt priority order is determined by bit (IM1,

IM0) of IMOD register.

(1) Selection of Interrupt by IP3-IP0

The condition allow for accepting interrupt is set state of
the interrupt mask enable flag and

the interrupt enable bit must be ``1``. In Reset state, these
IP3 - IP0 registers become all ``0``.

Table 12-2 Interrupt Selection by IP3 - IP0

IM1

IM0

IP3

IP2

IP1

IP0

R/W <00CA h>

IMOD

Interrupt Mode Register

IM1

IM0

Priority

fixed by hardware

changeable by IP3~ IP0

Interrupt is inhibited

Assigning by interrupt accept mode bit

KSCNR (Key Scan)

INT1R (External interrupt 1)

INT2R (External interrupt 2)

Reserved

T0R (Timer 0)

T1R (Timer 1)

T2R (Timer 2)

Reserved

WDTR (Watch Dog Timer)

BITR (Basic Interval Timer)

Reserved

IP3

IP2

IP1

IP0

Selection Interrupt

GMS81C50 Series

HYUNDAI

(2) Interrupt Timing

Figure 12-2 Interrupt Enable Accept Timing

*Interrupt Request sampling time

-Maximum 12 machine cycle (When execute DIV

instruction)

-Minimum 0 machine cycle

*Interrupt preprocess step is 8 machine cycle

*Interrupt overhead

-Maximum 1 + 12 + 8 = 21 machine cycle

-Minimum 1 + 0 + 8 = 9 machine cycle

(3) The valid timing after executing Interrupt control instructions

I flag is valid just after executing of EI/DI on the contrary.
Interrupt Enable register is valid one instruction after con-

trolling interrupt Enable Register.

12.4 INTERRUPT PROCESSING SEQUENCE

When an interrupt is accepted, the on-going process is
stopped and the interrupt service routine is executed. After
the interrupt service routine is completed it is necessary to
restore everything to the state before the interrupt oc-
cured.As soon as an interrupt is accepted, the content of the
program counter and PSW are savedin the stack area. At
the same time, the content of the vector address corre-
sponding to the accepted interrupt, which is in the interrupt
vector table, enters into the program counter and interrupt
service is executed. In order to execute the interrupt ser-
vice routine, it is necessary to write the jump addresses in
the vector table (FFE0 h ~ FFFF h) corresponding to each
interrupt

* Interrupt Processing Step

1) Store upper byte of Program Counter, SP <= SP

2) Store lower byte of Program Counter, SP <= SP - 1

3) Store Program Status Word, SP <= SP - 2

4) After resetting of I-flag, clear accepted Interrupt Re-
quest Flag. (Set B-flag for BRK Instruction)

5) Call Interrupt service routine

CLOCK

SYNC

A command before interrupt

interrupt process step

Interrupt Request Sampling

HYUNDAI

GMS81C50 Series

Figure 12-3 Interrupt Procesing Step Timing

12.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction)

S o f t w a r e i n t e r r u p t i s a v a i l a b l e j u s t b y w r i t i n g
``Break(BRK)`` instruction. The values of PC and PSW is

stacked by BRK instruction and then B flag of PSW is set
and I flag is reset.

Interrupt vector of BRK instruction is shared by vector of
Table Call (TCALL0). When both instruction of BRK and
TCALL0 are used, as shown in Figure 12-4 each process-

ing routine is judged by contents of B flag. There is no in-
struction to reset directly B flag.

*1 ISR

: Interrupt Service
Routine

*2 LVA

: Low Vector Address

*3 HVA

: High Vector Address

CODE

Interrupt Process Step

ISR

SP-1

SP-2

LVA

HVA

new PC

CODE

PCH

PCL

PSW

``L``

vector

``H``

vector

clock

SYNC

R/W

internal

addr bus

internal

data bus

internal

READ

internal

WRITE

set

reset

(Right after BRK execution)

PSW

Flag change by BRK execution

PSW

GMS81C50 Series

HYUNDAI

Figure 12-4 Execution of BRK or TCALL0

12.6 MULTIPLE INTERRUPT

If there is an interrupt, Interrupt Mask Enable Flag is auto-
matically cleared before entering the Interrupt Service
Routine. After then, no interrupt is accepted. If EI instruc-
tion is executed, interrupt mask enable bit becomes ``1``,

and each enable bit can accept interrupt request. When two
or more interrupts are generated simultaneously, the high-
est priority interrupt set by Interrupt Mode Register is ac-
cepted.

12.7 Key Scan Input Processing

(1) Standby Mode Release Register (SMRR)

Key Scan Interrupt is generated by detecting low or high
Input from each Input pin (R0, R1) is one of the sources
which release standby (SLEEP, STOP) mode. Key Scan
ports are all 16bit which are controlled by Standby Mode
Release Register (SMRR0, SMRR1). Key Input is consid-
ered as Interrupt, therefore, KSCNE bit of IEHN should be

set for correct interrupt executing, SLEEP mode and STOP
mode, the rest of executing is the same as that of external
Interrupt. Each SMRR Register bit is allowed for each port
(for Bit= ``0``, no Key Input, for Bit= ``1``, Key Input
available). At reset, SMRR becomes ``00 h``. So, there is
no Key Input source.

B flag

BRK INTERRUPT ROUTINE

TCALL0 ROUTINE

RETI

RET

BRK or

TCALL0

GMS81C50 Series

HYUNDAI

(2) Standby Release Level Control Register (SRLC)

Standby release level control register (SRLC) can select
the key scan input level ``L`` or ``H`` for standby release
by each bit pin (R0, R1). Standby release level control reg-

ister (SRLC) is write-only register and initialized as ``00
h`` in reset state.

SMRR0

KR07

Key Input Selection

no select

select

SMRR1

KR17

KR06

no select

select

KR16

KR05

no select

select

KR15

KR04

no select

select

KR14

KR03

no select

select

KR13

KR02

no select

select

KR12

KR01

no select

select

KR11

KR00

no select

select

KR10

KLR07

KLR06

KLR05

KLR04

KLR03

KLR02

KLR01

KLR00

W <00F6 h>

SRLC0

SRLC0 Register

KLR17

KLR16

KLR15

KLR14

KLR13

KLR12

KLR11

KLR10

W <00F7 h>

SRLC1

SRLC1 Register

GMS81C50 Series

HYUNDAI

13. WATCH DOG TIMER

Watch Dog Timer (WDT) consists of 6-bit binary counter,
6-bit comparator, and Watch Dog Timer Register

(WDTR).

Figure 13-1 Block diagram of Watch Dog Timer

13.1 Control of WDT

Watch Dog Timer can be used 6-bit general Timer or spe-
cific Watch dog timer by setting

bit5 (WDTON) of Clock Control Register (CKCTLR).

By assigning bit6(WDTCL) of WDTR, 6-bit counter can

be cleared.

IFBIT

6BIT COMPARATOR

WDTR

W <00C8 h>

IF WDT

CLR

WDTON

To Reset circuit

Internal Data Bus

WDT0

WDT1

WDT2

WDT3

WDT4

WDT5

WDTR0

WDTR1

WDTR2

WDTR3

WDTR4

WDTR5

WDTCL

WDTON

ENPCK

BTCL

BTS2

BTS1

BTS0

W <00C7 h>

CKCTLR

Clock Control Register

WDTON

Watch Dog Timer Function Control

6-bit Timer

Watch Dog Timer

HYUNDAI

GMS81C50 Series

13.2 WDT Interrupt Interval

WDT Interrupt (IFWDT) interval is determined by the in-
terrupt IFBIT interval of Basic Interval Timer and the val-
ue of WDT Register.

-Interval of IFWDT = (IFBIT interval) * (WDTR value)

-Interval of IFWDT : 512 us * 1 = 512 us (MIN>)

-65,536us * 63 = 4,128,768 us (MAX>)

As IFBIT (Basic Interval Timer Interrupt Request) is used
for input clock of WDT, Input clock cycle is possible from
512 us to 65,536 us by BTS. (at fex = 4MHz)

*At Hardware reset time ,WDT starts automatically.
Therefore, the user must select the CKCTLR, WDTR be-
fore WDT overflow.

-Reset WDTR value = 0F h,15

-interval of WDT = 65,536 * 15 = 983040 us

(about 1second )

Determine Interval of IFWDT
Interval of IFWDT = Value of WDTR

Interval of IFBIT

WDTCL

WDTR5

WDTR4

WDTR3

WDTR2

WDTR1

WDTR0

W <00C8 h>

WDTR

Watch DOG Timer Register

WDTCL

Watch Dog Timer Operation

free-run

Automatically cleared, after one machine cycle

HYUNDAI

GMS81C50 Series

14. STANDBY FUNCTION

To save power consumption, there is STOP modes. In this

modes, the execution of program stops.

14.1 Sleep Mode

SLEEP mode can be entered by setting the bit of SLEEP
mode register (SLPM). In the mode, CPU clock stops but
oscillator keeps running. B.I.T and a part of peripheral
hardware execute, but prescalerís output which provide
clock to peripherals can be stopped by program. (Except,
PS10 canít stopped.) In SLEEP mode, more consuming
power can be saved by not using other peripheral hardware
except for B.I.T. By setting ENPCK (peripheral clock con-
trol bit) of CKCTLR (clock control register) to ``0``, pe-
ripheral hardware halted, and SLEEP mode is entered. To

release SLEEP mode by BITR (basic interval timer inter-
rupt), bit10 of prescaler should be selected as B.I.T input
clock before entering SLEEP mode. ``NOP`` instruction
should be follows setting of SLEEP mode for rising pre-
charge time of data bus line.

(ex) setting of SLEEP mode : set the bit of SLEEP

; mode register (SLPM)

NOP : NOP instruction

14.2 STOP MODE

STOP mode can be entered by STOP instruction during
program. In STOP mode, oscillator is stopped to make all
clocks stop, which leads to less power consumption. All
registers and RAM data are preserved. ``NOP`` instruction
should be follows STOP instruction for rising precharge

time of Data Bus line.

(ex) STOP : STOP instruction execution

NOP : NOP instruction

SLPM0

W <00F0 h>

SLPM

SLEEP MODE CONTROL Register

SLPM0

condition

sleep mode release

sleep mode

WDTON

ENPCK

BTCL

BTS2

BTS1

BTS0

W <00C8 h>

CKCTLR

Colck Control Register

ENCPK

Peripheral Clock

stopped

provided

HYUNDAI

GMS81C50 Series

14.3 STANDBY MODE RELEASE

Release of STANDBY mode is executed by RESET input
and Interrupt signal. Register value is defined when Reset.
When there is a release signal of STOP mode (Interrupt,

RESET input), the instruction execution starts after stabi-
lization oscillation time is set by value of BTS2 ~ BTS0
and set ENPCK to ``1``.

Table 14-1 Standby Mode Register

Table 14-2 Standby Mode Release

Release Signal

KSCN (key input)

SLEEP

RESET

INT1 , INT2

B.I.T

STOP

Release Factor

KSCN

(key input)

Release Method

RESET

INT1
INT2

Basic Interval Timer

(IFBIT)

Standby mode is released by low input of selected pin by key scan Input
(SMRR0, SMRR1) In case of interrupt mask enable flag = ``0``,
program executes just after standby instruction,
if flag = ``1``, enters each interrupt service routine.

When external interrupt (INT1, INT2) enable flag is ``1``, standby mode is released
at the rising edge of each terminal. When Standby mode is released at interrupt.
Mask Enable flag = ``0``, program executes from the next instruction of standby
instruction. When ``1``, enters each interrupt service routine.

When B.I.T is executed only by bit10 of prescaler (PS10), SLEEP mode can be
release. Interrupt release SLEEP mode, when BIT interrupt enable flag is ``1``.
When standby mode is released at interrupt. Mask enable flag = ``0``,
program executes from the next instruction of SLEEP instruction.
When ``1``, enters each interrupt service routine.

By RESET Pin = Low level, Standby mode is release and system is initialized

GMS81C50 Series

HYUNDAI

Figure 14-3 Release Timing of Standby Mode

14.4 RELEASE OPERATION OF STANDBY MODE

After standby mode is released, the operation begins ac-
cording to content of related interrupt register just before
standby mode start (Figure 14-4 )

(1) Interrupt Enable Flag(I) of PSW = ``0``

Release by only interrupt which interrupt enable flag =
``1``, and starts to execute from next to standby instruction
(SLEEP or STOP).

(2) Interrupt Enable Flag(I) of PSW = ``1``

Released by only interrupt which each interrupt enable flag

= ``1``, and jump to the relevant interrupt service routine.

Note: When STOP instruction is used, B.I.T should guar-
antee the stabilization oscillation time. Thus, just before en-
tering STOP mode, clock of bit10 (PS10) of prescaler is
selected or peripheral hardware clock control bit (ENPCK)
to ``1``, Therefore the clock necessary for stabilization os-
cillation time should be input into B.I.T. otherwise, standby
mode is released by reset signal. In case of interrupt re-
quest flag and interrupt enable flag are both ``1``, standby
mode is not entered.

STOP Mode

Stable

OSC. time

Program Setting Time by

CKCTLR

Longer than

stable OSC. Time

Xin

Longer than

2 machine cycle

SLEEP Mode

SLEEP command

[ SLEEP MODE ]

[ STOP MODE ]

release by interrupt

RESET

clock

release by interrupt

RESET

HYUNDAI

GMS81C50 Series

Figure 14-4 Standby Mode Release Flow

Table 14-3 Operation State in Standby Mode

STOP Command

Standby Mode

Interrupt Request GEN.

IE Flag

Standby Mode Release

PSW

IE Flag

Interrupt Service Routine

Standby Next Command

Execution

Internal circuit

STOP mode

SLEEP mode

Oscillator

Internal CPU clock

RAM

I/O port

Prescaler

Basic Interval Timer

Watch Dog Timer

Timer

Address Bus, Data Bus

Active

Stop

Retained

Active

PS10 selected : Active
Others : Stop

Stop

Retained

Stop

Retained

Stop

Retained

GMS81C50 Series

HYUNDAI

15. OSCILLATION CIRCUIT

Oscillation circuit is designed to be used either with a ce-
ramic resonator or crystal oscillator. Fig. 4.2-(a) shows
circuit diagrams using a crystal (or ceramic) oscillator. As
shown in the diagram, oscillation circuits can be construct-
ed by connecting a oscillator between Xout and Xin.
Clock from oscillation circuit makes CPU clock via clock

pulse generator, and then enters prescaler to make periph-
eral hardware clock. Alternately, the oscillator may be
driven from an external source as shown is Fig. 4.2.-(b). In
the Standby (STOP) mode, oscillatiion stop, Xout state
goes to ``HIigh``, Xin state goes to ``Low``, and built-in
feed back resistor is disabled.

Figure 15-1 Oscillator configurations

* Recommendable resonator

* MC type is building in load capacitior.CCR type is chip type.

Cout

Cin

Xin

Xout

(b) External clock input circuit

Xin

Xout

External clock

(a) External Crystal (Ceramic) oscillator circuit

Frequency

Resonator Maker

Part Name

Load Capacitor

Operating Voltage

4.0 MHz

ZTA4.00MG

Cin=Cout=30pF

2.2 ~ 4.0V

TDK

FCR4.0MC5

Cin=Cout=open

2.2 ~ 4.0V

TDK

FCR4.0M5

Cin=Cout=33pF

2.2 ~ 4.0V

TDK

CCR4.0MC3

2.2 ~ 4.0V

HYUNDAI

GMS81C50 Series

16. RESET FUNCTION

16.1 EXTERNAL RESET

The RESET pin should be held at low for at least 2machine
cycles with the power supply voltage within the operating
voltage range and must be connected 0.1uF capacitor for

stable system initialization. The RESET pin contains a
Schmitt trigger with an internal pull-up resistor.

Figure 16-1

16.2 POWER ON RESET

Power On Reset circuit automatically detects the rise of
power voltage (the rising time should be within 50ms) the
power voltage reaches a certain level, RESET terminal is
maintained at °»L°» Level until a crystal ceramic oscillator
oscillates stably. After power applies and starting of oscil-
lation, this reset state is maintained for about oscillation
cycle of 219 (about 65.5ms : at 4MHz).The execution of
built-in Power On Reset circuit is as follows :

(1) Latch the pulse from Power On Detection Pulse Gener-
ator circuit, and reset Prescaler, B.I.T and B.I.T Overflow

detection circuit.

(2) Once B.I.T Overflow detection circuit is reset. Then,
Prescaler starts to count.

(3) Prescaler output is inputted into B.I.T and PS10 of
Prescaler output is automatically selected. If overflow of
B.I.T is detected, Overflow detection circuit is set.

(4) Reset circuit generates maximum period of reset pulse
from Prescaler and B.I.T.

Figure 16-2 Block Diagram of Power On Reset Circuit

RESET

0.1 uF Capacitor

RESET

Power On DET

Pulse GEN.

OSC.

CLR

Prescaler

CLR

Basic Interval

Tiemr

CLR

Basic Interval

Tiemr

XTAL

PS10

MSB

Internal Reset

VDD

VSS

0.1uF

Internal IC

GMS81C50 Series

HYUNDAI

Note: Notice ; When Power On Reset, oscillator stabiliza-
tion time doesn`t include OSC. Start time.

Figure 16-3 Oscillator stabilization diagram

Figure 16-4 Reset Timing by Diagram

16.3 Low Voltage Detection Mode

(1) Low voltage detection condition

An on board voltage comparator checks that VDD is at the
required level to ensure correct operation of the device. If
VDD is below a certain level, Low voltage detector forces
the device into low voltage detection mode.

(2) Low Voltage Detection Mode

There is no power consumption except stop current, stop
mode release function is disabled. All I/O port is config-
ured as input mode and Data memory is retained until volt-
age through external capacitor is worn out. In this mode,
all port can be selected with Pull-up resistor by Mask op-
tion. If there is no information on the Mask option sheet
,the default pull up option (all port connect to pull-up resis-

2 %1 %%,8,6@

$ 14$ 26%%1 %

RESET

ADDR. BUS

INTERNAL

DATA BUS

SP-1

SP-2

FFFE

FFFF

NEW PC

LSB

VECTOR

MSB
VECTOR

INTERNAL
RESET

GMS81C50 Series

HYUNDAI

Figure 16-6 Low Voltage Detection and Protection

(5) S/W flow chart example after Reset using SRAM Back-up

Figure 16-7 S/W Flow Chart Example for SRAM Back-up

3.0V

1.8V(TYP)
( 20

(

* SRAM Data Backup

User
Removes
Batteries

User
Replace
Batteries

Interrupt :

disable

Stop release

: disable

All I/O port

: input Mode

Remout port

: Low Level

OSC :

STOP

All I/O port pull-up ON (Mask Option )
SRAM Data retention

* The operation after Low voltage detection

about hours depend on Vcc-Gnd Capacitor

Low Voltage Detection

point

MCU OPR.
Voltage

Power On Reset

( SRAM unstable )

Power On Reset

( SRAM retention)

0.7V(V

RET

)

RESET

Stack Pointer initialize

SRAM DATA IS VALID?

Check the SRAM value

(RAM Pattern, Check sum..)

Clear All Ram area

Use saved SRAM

value

HYUNDAI

GMS81C50 Series

16.4 Low Voltage Indicator Register (LVIR)

Low Voltage Indication Register (LVIR) is read only Reg-
ister. It is useful to display the consumption of Batteries.
If VDD power level is below a cirtain level which is higher
than low voltage detection level ( refer to Figure 16-6 ) ,

The bit of LVIR register could be set according to the VDD
level sequentially. The VDD dection levels for Indication
are two , that is , Bit1 and Bit0 of LVIR Register. The de-
tection level of Bit0 is higer than Bit1.

LVIR1

LVIR0

<00EF h>

LVIR

bit

initial value

R / W

Appendix A. GMS800 Series Instruction

A-1

1. Instruction Map

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

000

SET1

dp.bit

BBS

A.bit,rel

BBS

dp.bit,rel

ADC

#imm

ADC

dp+X

ADC

!abs

ASL

TCALL

SETA1

.bit

BIT

POP

PUSH

BRK

001

CLRC

SBC

#imm

SBC

dp+X

SBC

!abs

ROL

TCALL

CLRA1

.bit

COM

POP

PUSH

BRA

rel

010

CLRG

CMP

#imm

CMP

dp+X

CMP

!abs

LSR

TCALL

NOT1

M.bit

TST

POP

PUSH

PCALL

Upage

011

#imm

dp+X

!abs

ROR

TCALL

OR1

OR1B

CMPX

POP

PSW

PUSH

PSW

RET

100

CLRV

AND

#imm

AND

dp+X

AND

!abs

INC

TCALL

AND1

AND1B

CMPY

CBNE

dp+X

TXSP

INC

101

SETC

EOR

#imm

EOR

dp+X

EOR

!abs

DEC

TCALL

EOR1

EOR1B

DBNE

XMA

dp+X

TSPX

DEC

110

SETG

LDA

#imm

LDA

dp+X

LDA

!abs

TXA

LDY

TCALL

LDC

LDCB

LDX

dp+Y

XCN

DAS

111

LDM

dp,#imm

STA

dp+X

STA

!abs

TAX

STY

TCALL

STC

M.bit

STX

dp+Y

XAS

STOP

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

000

BPL

rel

CLR1

dp.bit

BBC

A.bit,rel

BBC

dp.bit,rel

ADC

{X}

ADC

!abs+Y

ADC

[dp+X]

ADC

[dp]+Y

ASL

!abs

ASL

dp+X

TCALL

JMP

!abs

BIT

!abs

ADDW

LDX

#imm

JMP

[!abs]

001

BVC

rel

SBC

{X}

SBC

!abs+Y

SBC

[dp+X]

SBC

[dp]+Y

ROL

!abs

ROL

dp+X

TCALL

CALL

!abs

TEST

!abs

SUBW

LDY

#imm

JMP

[dp]

010

BCC

rel

CMP

{X}

CMP

!abs+Y

CMP

[dp+X]

CMP

[dp]+Y

LSR

!abs

LSR

dp+X

TCALL

MUL

TCLR1

!abs

CMPW

CMPX

#imm

CALL

[dp]

011

BNE

rel

{X}

!abs+Y

[dp+X]

[dp]+Y

ROR

!abs

ROR

dp+X

TCALL

DBNE

CMPX

!abs

LDYA

CMPY

#imm

RETI

100

BMI

rel

AND

{X}

AND

!abs+Y

AND

[dp+X]

AND

[dp]+Y

INC

!abs

INC

dp+X

TCALL

DIV

CMPY

!abs

INCW

INC

TAY

101

BVS

rel

EOR

{X}

EOR

!abs+Y

EOR

[dp+X]

EOR

[dp]+Y

DEC

!abs

DEC

dp+X

TCALL

XMA

{X}

XMA

DECW

DEC

TYA

110

BCS

rel

LDA

{X}

LDA

!abs+Y

LDA

[dp+X]

LDA

[dp]+Y

LDY

!abs

LDY

dp+X

TCALL

LDA

{X}+

LDX

!abs

STYA

XAY

DAA

111

BEQ

rel

STA

{X}

STA

!abs+Y

STA

[dp+X]

STA

[dp]+Y

STY

!abs

STY

dp+X

TCALL

STA

{X}+

STX

!abs

CBNE

XYX

NOP

LOW

HIGH

LOW

HIGH

Appendix A. GMS800 Series Instruction

A-2

2. Alphabetic order table of instruction

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

ADC #imm

Add with carry.

NV - - H - ZC

ADC dp

A + (M) + C

ADC dp + X

ADC !abs

ADC !abs+Y

ADC [dp+X]

ADC [dp]+Y

ADC {X}

ADDW dp

16-bits add without carry : YA

YA + (dp+1)(dp)

NV - - H - ZC

AND #imm

Logical AND

N - - - - - Z -

AND dp

A ^ (M)

AND dp + X

AND !abs

AND !abs+Y

AND [dp+X]

AND [dp] + Y

AND {X}

AND1 M.bit

Bit AND C-flag : C

C ^ (M.bit)

- - - - - - - C

AND1B M.bit

Bit AND C-flag and NOT : C

C ^ ~(M.bit)

- - - - - - - C

ASL A

Arithmetic shift left

N - - - - - ZC

ASL dp

ASL dp + X

ASL !abs

BBC A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBC dp.bit,rel

5/7

if(bit) = 0, then PC

PC + rel

BBS A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBS dp.bit,rel

5/7

if(bit) = 1, then PC

PC + rel

BCC rel

2/4

Branch if carry bit clear :
if(C) = 0, then PC

PC + rel

MM - - - - Z -

BCS rel

2/4

Branch if carry bit set : If (C) =1, then PC

PC + rel

- - - - - - - -

BEQ rel

2/4

Branch if equal : if (Z) = 1, then PC

PC + rel

- - - - - - - -

BIT dp

Bit test A with memory :

MM - - - - Z -

BIT !abs

A ^ M, N

), V

)

BMI rel

2/4

Branch if munus : if (N) = 1, then PC

PC + rel

- - - - - - - -

BNE rel

2/4

Branch if not equal : if (Z) = 0, then PC

PC + rel

- - - - - - - -

BPL rel

2/4

Branch if not minus : if (N) = 0, then PC

PC + rel

- - - - - - - -

BRA rel

Branch always : PC

PC + rel

- - - - - - - -

BRK

Software interrupt:

- - - 1 - 0 - -

"1", M(SP)

(PC

), SP

SP - 1,

M(s)

(PC

), SP

S - 1, M(SP)

PSW,

SP - 1, PC

(0FFDE

), PC

(0FFDF

)

BVC rel

2/4

Branch if overflow bit clear :

- - - - - - - -

If (V) = 0, then PC

PC + rel

BVS rel

2/4

Branch if overflow bit set :

- - - - - - - -

If (V) = 1, then PC

PC + rel

C 7 6 5 4 3 2 1 0

Appendix A. GMS800 Series Instruction

A-3

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

CALL !abs

Subroutine call

- - - - - - - -

CALL [dp]

M(SP)

(PC

), SP

SP-1, M(SP)

(PC

), SP

SP-1

if !abs, PC

abs ; if [dp], PC

(dp), PC

(dp+1)

CBNE dp,rel

5/7

Compare and branch if not equal ;

- - - - - - - -

CBNE dp + X, rel

6/8

If A

(M), then PC

PC + rel.

CLR1 dp.bit

Clear bit : (M.bit)

"0"

- - - - - - - -

CLR1A A.bit

Clear A.bit : (A.bit)

"0"

- - - - - - - -

CLRC

Clear C-flag : C

"0"

- - - - - - - 0

CLRG

Clear G-flag : G

"0"

- - 0 - - - - -

CLRV

Clear V-flag : V

"0"

- 0 - - 0 - - -

CMP #imm

Compare accumulator contents with memory contents

N - - - - - ZC

CMP dp

A - (M)

CMP dp + X

CMP !abs

CMP !abs + Y

CMP [dp + X]

CMP [dp] + Y

CMP {X}

CMPW dp

Compare YA contents with memory pair contents :

N - - - - - ZC

YA - (dp+1)(dp)

CMPX #imm

Compare X contents with memory contents

N - - - - - ZC

CMPX dp

X - (M)

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

N - - - - - ZC

CMPY dp

Y - (M)

CMPY !abs

COM dp

1's complement : (dp)

~(dp)

N - - - - - Z -

DAA

Decimal adjust for addition

N - - - - - ZC

DAS

Decimal adjust for substraction

N - - - - - ZC

DBNE dp,rel

5/7

Decrement and branch if not equal :

- - - - - - - -

DBNE Y,rel

4/6

if (M)

0, then PC

PC + rel.

DEC A

Decrement

N - - - - - Z -

DEC dp

M - 1

DEC dp + X

DEC !abs

DEC X

DEC Y

DECW dp

Decrement memory pair : (dp+1)(dp)

{(dp+1)(dp)} - 1

N - - - - - Z -

Disable interrupts : I

"0"

- - - - - 0 - -

DIV

Divide : YA/X

Q:A, R:Y

NV - - H - Z -

Enable interrupts : I

"1"

- - - - - 1 - -

Appendix A. GMS800 Series Instruction

A-4

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

EOR #imm

Exclusive OR

N - - - - - Z -

EOR dp

(M)

EOR dp + X

EOR !abs

EOR !abs + Y

EOR [ dp + X]

EOR [dp] + Y

EOR {X}

EOR1 M.bit

Bit exclusive-OR C-flag : C

(M.bit)

- - - - - - - C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

(M.bit)

- - - - - - - C

INC A

Increment

N - - - - - ZC

INC dp

(M)

(M) + 1

N - - - - - Z -

INC dp + X

INC !abs

INC X

INC Y

INCW dp

Increment memory pair : (dp+1)(dp)

{(dp+1)(dp)} + 1

N - - - - - Z -

JMP !abs

Unconditional jump

- - - - - - - -

JMP [!abs]

jump address

JMP [dp]

LDA #imm

Load accumulator

N - - - - - Z -

100

LDA dp

(M)

101

LDA dp + X

102

LDA !abs

103

LDA !abs + Y

104

LDA [dp + X]

105

LDA [dp]+Y

106

LDA {X}

107

LDA {X}+

X-register auto-increment : A

(M), X

X + 1

108

LDC M.bit

Load C-flag : C

(M.bit)

- - - - - - - C

109

LDCB M.bit

Load C-flag with NOT : C

~(M.bit)

- - - - - - - C

110

LDM dp,#imm

Load memory with immediate data : (M)

imm

- - - - - - - -

111

LDX #imm

Load X-register

N - - - - - Z -

112

LDX dp

(M)

113

LDX dp + Y

114

LDX !abs

115

LDY #imm

Load X-register

N - - - - - Z -

116

LDY dp

(M)

117

LDY dp + Y

118

LDY !abs

119

LDYA dp

Load YA : YA

(dp+1)(dp)

N - - - - - Z -

120

LSR A

Logical shift right

N - - - - - ZC

121

LSR dp

122

LSR dp + X

123

LSR !abs

7 6 5 4 3 2 1 0 C

Appendix A. GMS800 Series Instruction

A-5

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

124

MUL

Multiply : YA

Y x A

N - - - - - Z -

125

NOP

No operation

- - - - - - - -

126

NOT1 M.bit

Bit complement : (M.bit)

~(M.bit)

- - - - - - - -

127

OR #imm

Logical OR

N - - - - - Z -

128

OR dp

A V (M)

129

OR dp + X

130

OR !abs

131

OR !abs + Y

132

OR [dp +X}

133

OR [dp] + Y

134

OR {X}

135

OR1 M.bit

Bit OR C-flag : C

C V (M.bit)

- - - - - - - C

136

OR1B M.bit

Bit OR C-flag and NOT : C

C V ~(M.bit)

- - - - - - - C

137

PCALL

U-page call : M(SP)

(PC

), SP

SP -1,

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

(upage), PC

"OFF

138

POP A

Pop from stack

- - - - - - - -

139

POP X

SP + 1, Reg.

M(SP)

140

POP Y

141

POP PSW

(restored)

142

PUSH A

Push to stack

- - - - - - - -

143

PUSH X

M(SP)

Reg. SP

SP - 1

144

PUSH Y

145

PUSH PSW

146

RET

Return from subroutine :

- - - - - - - -

SP+1, PC

M(SP), SP

SP+1, PC

M(SP)

147

RETI

Return from interrupt :

(restored)

SP+1, PSW

M(SP), SP

SP+1,PC

M(SP),

SP+1, PC

M(SP)

148

ROL A

Rotate left through carry

N - - - - - ZC

149

ROL dp

150

ROL dp + X

151

ROL !abs

152

ROR A

Rotate right through carry

N - - - - - ZC

153

ROR dp

154

ROR dp + X

155

ROR !abs

156

SBC #imm

Substract with carry

NV - - HZC

157

SBC dp

A - (M) - ~(C)

158

SBC dp + X

159

SBC !abs

160

SBC !abs + Y

161

SBC [dp + X]

162

SBC [dp] + Y

163

SBC {X}

C 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 C

Appendix A. GMS800 Series Instruction

A-6

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

164

SET1 dp.bit

Set bit : (M.bit)

"1"

- - - - - - - -

165

SETA1 A.bit

Set A.bit : (A.bit)

"1"

- - - - - - - -

166

SETC

Set C-flag : C

"1"

- - - - - - - 1

167

SETG

Set G-flag : G

"1"

- - 1 - - - - -

168

STA dp

Store accumulator contents in memory

- - - - - - - -

169

STA dp + X

(M)

170

STA !abs

171

STA !abs + Y

172

STA [dp + X]

173

STA [dp] + Y

174

STA {X}

175

STA {X}+

X-register auto-increment : (M)

A, X

X + 1

176

STC M.bit

Store C-flag : (M.bit)

- - - - - - - -

177

STOP

Stop mode (halt CPU, stop oscillator)

- - - - - - - -

178

STX dp

Store X-register contents in memory

- - - - - - - -

179

STX dp + Y

(M)

180

STX !abs

181

STY dp

Store Y-register contents in memory

- - - - - - - -

182

STY dp + X

(M)

183

STY !abs

184

STYA dp

Store YA : (dp+1)(dp)

- - - - - - - -

185

SUBW dp

16-bits substract without carry : YA

YA - (dp+1)(dp)

NV - - H - ZC

186

TAX

Transfer accumulator contents to X-register : X

N - - - - - Z -

187

TAY

Transfer accumulator contents to Y-register : Y

N - - - - - Z -

188

TCALL n

Table call :

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

M(SP)

(PC

), SP

SP -1

(Table vector L), PC

(Table vector H)

189

TCLR1 !abs

Test and clear bits with A :

N - - - - - Z -

A - (M), (M)

(M) ^ ~(A)

190

TSET1 !abs

Test and set bits with A :

N - - - - - Z -

A - (M), (M)

(M) V (A)

191

TSPX

Transfer stack-pointer contents to X-register : X

N - - - - - Z -

192

TST dp

Test memory contents for negative or zero : (dp) - 00

N - - - - - Z -

193

TXA

Transfer X-register contents to accumulator : A

N - - - - - Z -

194

TXSP

Transfer X-register contents to stack-pointer : SP

N - - - - - Z -

195

TYA

Transfer Y-register contents to accumulator : A

N - - - - - Z -

196

XAX

Exchange X-register contents with accumulator : X

- - - - - - - -

197

XAY

Exchange Y-register contents with accumulator : Y

- - - - - - - -

198

XCN

Exchange nibbles within the accumulator:

N - - - - - Z -

~ A

199

XMA dp

Exchange memory contents with accumulator

N - - - - - Z -

200

XMA dp + X

(M)

201

XMA {X}

202

XYX

Exchange X-register contents with Y-register : X

- - - - - - - -

Appendix A. GMS800 Series Instruction

A-7

2.1 Instruction Table by Function

1. Arithmetic/Logic Operation

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

ADC #imm

Add with carry.

NV - - H - ZC

ADC dp

A + (M) + C

ADC dp + X

ADC !abs

ADC !abs+Y

ADC [dp+X]

ADC [dp]+Y

ADC {X}

AND #imm

Logical AND

N - - - - - Z -

AND dp

A ^ (M)

AND dp + X

AND !abs

AND !abs+Y

AND [dp+X]

AND [dp] + Y

AND {X}

ASL A

Arithmetic shift left

N - - - - - ZC

ASL dp

ASL dp + X

ASL !abs

CMP #imm

Compare accumulator contents with memory contents

N - - - - - ZC

CMP dp

A - (M)

CMP dp + X

CMP !abs

CMP !abs + Y

CMP [dp + X]

CMP [dp] + Y

CMP {X}

CMPX #imm

Compare X contents with memory contents

N - - - - - ZC

CMPX dp

X - (M)

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

N - - - - - ZC

CMPY dp

Y - (M)

CMPY !abs

COM dp

1's complement : (dp)

~(dp)

N - - - - - Z -

DAA

Decimal adjust for addition

N - - - - - ZC

DAS

Decimal adjust for substraction

N - - - - - ZC

DEC A

Decrement

N - - - - - Z -

DEC dp

M - 1

DEC dp + X

DEC !abs

DEC X

DEC Y

DIV

Divide : YA/A

Q:A, R:Y

NV - - H - Z -

C 7 6 5 4 3 2 1 0

Appendix A. GMS800 Series Instruction

A-8

EOR #imm

Exclusive OR

N - - - - - Z -

EOR dp

(M)

EOR dp + X

EOR !abs

EOR !abs + Y

EOR [ dp + X]

EOR [dp] + Y

EOR {X}

INC A

Increment

N - - - - - ZC

INC dp

(M)

(M) + 1

N - - - - - Z -

INC dp + X

INC !abs

INC X

INC Y

LSR A

Logical shift right

N - - - - - ZC

LSR dp

LSR dp + X

LSR !abs

MUL

Multiply : YA

Y x A

N - - - - - Z -

OR #imm

Logical OR

N - - - - - Z -

OR dp

A V (M)

OR dp + X

OR !abs

OR !abs + Y

OR [dp +X}

OR [dp] + Y

OR {X}

ROL A

Rotate left through carry

N - - - - - ZC

ROL dp

ROL dp + X

ROL !abs

ROR A

Rotate right through carry

N - - - - - ZC

ROR dp

ROR dp + X

ROR !abs

SBC #imm

Substract with carry

NV - - HZC

SBC dp

A - (M) - ~(C)

SBC dp + X

SBC !abs

SBC !abs + Y

SBC [dp + X]

SBC [dp] + Y

SBC {X}

TST dp

Test memory contents for negative or zero : (dp) - 00

N - - - - - Z -

XCN

Exchange nibbles within the accumulator:

N - - - - - Z -

~ A

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

7 6 5 4 3 2 1 0 C

C 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 C

Appendix A. GMS800 Series Instruction

A-9

2. Register / Memory Operation

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

LDA #imm

Load accumulator

N - - - - - Z -

LDA dp

(M)

LDA dp + X

LDA !abs

LDA !abs + Y

LDA [dp + X]

LDA [dp]+Y

LDA {X}

LDA {X}+

X-register auto-increment : A

(M), X

X + 1

LDM dp,#imm

Load memory with immediate data : (M)

imm

- - - - - - - -

LDX #imm

Load X-register

N - - - - - Z -

LDX dp

(M)

LDX dp + Y

LDX !abs

LDY #imm

Load X-register

N - - - - - Z -

LDY dp

(M)

LDY dp + Y

LDY !abs

STA dp

Store accumulator contents in memory

- - - - - - - -

STA dp + X

(M)

STA !abs

STA !abs + Y

STA [dp + X]

STA [dp] + Y

STA {X}

STA {X}+

X-register auto-increment : (M)

A, X

X + 1

STX dp

Store X-register contents in memory

- - - - - - - -

STX dp + Y

(M)

STX !abs

STY dp

Store Y-register contents in memory

- - - - - - - -

STY dp + X

(M)

STY !abs

TAX

Transfer accumulator contents to X-register : X

N - - - - - Z -

TAY

Transfer accumulator contents to Y-register : Y

N - - - - - Z -

TSPX

Transfer stack-pointer contents to X-register : X

N - - - - - Z -

TXA

Transfer X-register contents to accumulator : A

N - - - - - Z -

TXSP

Transfer X-register contents to stack-pointer : SP

N - - - - - Z -

TYA

Transfer Y-register contents to accumulator : A

N - - - - - Z -

XAX

Exchange X-register contents with accumulator : X

- - - - - - - -

XAY

Exchange Y-register contents with accumulator : Y

- - - - - - - -

XMA dp

Exchange memory contents with accumulator

N - - - - - Z -

XMA dp + X

(M)

XMA {X}

XYX

Exchange X-register contents with Y-register : X

- - - - - - - -

Appendix A. GMS800 Series Instruction

A-10

3. 16-Bit Operation

4. Bit Manipulation

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

ADDW dp

16-bits add without carry : YA

YA + (dp+1)(dp)

NV - - H - ZC

CMPW dp

Compare YA contents with memory pair contents :

N - - - - - ZC

YA - (dp+1)(dp)

DECW dp

Decrement memory pair : (dp+1)(dp)

{(dp+1)(dp)} - 1

N - - - - - Z -

INCW dp

Increment memory pair : (dp+1)(dp)

{(dp+1)(dp)} + 1

N - - - - - Z -

LDYA dp

Load YA : YA

(dp+1)(dp)

N - - - - - Z -

STYA dp

Store YA : (dp+1)(dp)

- - - - - - - -

SUBW dp

16-bits substract without carry : YA

YA - (dp+1)(dp)

NV - - H - ZC

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

AND1 M.bit

Bit AND C-flag : C

C ^ (M.bit)

- - - - - - - C

AND1B M.bit

Bit AND C-flag and NOT : C

C ^ ~(M.bit)

- - - - - - - C

BIT dp

Bit test A with memory :

MM - - - - Z -

BIT !abs

A ^ M, N

), V

)

CLR1 dp.bit

Clear bit : (M.bit)

"0"

- - - - - - - -

CLR1A A.bit

Clear A.bit : (A.bit)

"0"

- - - - - - - -

CLRC

Clear C-flag : C

"0"

- - - - - - - 0

CLRG

Clear G-flag : G

"0"

- - 0 - - - - -

CLRV

Clear V-flag : V

"0"

- 0 - - 0 - - -

EOR1 M.bit

Bit exclusive-OR C-flag : C

(M.bit)

- - - - - - - C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

(M.bit)

- - - - - - - C

LDC M.bit

Load C-flag : C

(M.bit)

- - - - - - - C

LDCB M.bit

Load C-flag with NOT : C

~(M.bit)

- - - - - - - C

NOT1 M.bit

Bit complement : (M.bit)

~(M.bit)

- - - - - - - -

OR1 M.bit

Bit OR C-flag : C

C V (M.bit)

- - - - - - - C

OR1B M.bit

Bit OR C-flag and NOT : C

C V ~(M.bit)

- - - - - - - C

SET1 dp.bit

Set bit : (M.bit)

"1"

- - - - - - - -

SETA1 A.bit

Set A.bit : (A.bit)

"1"

- - - - - - - -

SETC

Set C-flag : C

"1"

- - - - - - - 1

SETG

Set G-flag : G

"1"

- - 1 - - - - -

STC M.bit

Store C-flag : (M.bit)

- - - - - - - -

TCLR1 !abs

Test and clear bits with A :

N - - - - - Z -

A - (M), (M)

(M) ^ ~(A)

TSET1 !abs

Test and set bits with A :

N - - - - - Z -

A - (M), (M)

(M) V (A)

Appendix A. GMS800 Series Instruction

A-11

5. Branch / Jump Operation

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

BBC A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBC dp.bit,rel

5/7

if(bit) = 0, then PC

PC + rel

BBS A.bit,rel

4/6

Branch if bit clear :

- - - - - - - -

BBS dp.bit,rel

5/7

if(bit) = 1, then PC

PC + rel

BCC rel

2/4

Branch if carry bit clear :
if(C) = 0, then PC

PC + rel

MM - - - - Z -

BCS rel

2/4

Branch if carry bit set : If (C) =1, then PC

PC + rel

- - - - - - - -

BEQ rel

2/4

Branch if equal : if (Z) = 1, then PC

PC + rel

- - - - - - - -

BMI rel

2/4

Branch if munus : if (N) = 1, then PC

PC + rel

- - - - - - - -

BNE rel

2/4

Branch if not equal : if (Z) = 0, then PC

PC + rel

- - - - - - - -

BPL rel

2/4

Branch if not minus : if (N) = 0, then PC

PC + rel

- - - - - - - -

BRA rel

Branch always : PC

PC + rel

- - - - - - - -

BVC rel

2/4

Branch if overflow bit clear :

- - - - - - - -

If (V) = 0, then PC

PC + rel

BVS rel

2/4

Branch if overflow bit set :

- - - - - - - -

If (V) = 1, then PC

PC + rel

CALL !abs

Subroutine call

- - - - - - - -

CALL [dp]

M(SP)

(PC

), SP

SP-1, M(SP)

(PC

), SP

SP-1

if !abs, PC

abs ; if [dp], PC

(dp), PC

(dp+1)

CBNE dp,rel

5/7

Compare and branch if not equal ;

- - - - - - - -

CBNE dp + X, rel

6/8

If A

(M), then PC

PC + rel.

DBNE dp,rel

5/7

Decrement and branch if not equal :

- - - - - - - -

DBNE Y,rel

4/6

if (M)

0, then PC

PC + rel.

JMP !abs

Unconditional jump

- - - - - - - -

JMP [!abs]

jump address

JMP [dp]

PCALL

U-page call : M(SP)

(PC

), SP

SP -1,

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

(upage), PC

"OFF

TCALL n

Table call :

- - - - - - - -

M(SP)

(PC

), SP

SP -1,

M(SP)

(PC

), SP

SP -1

(Table vector L), PC

(Table vector H)

Appendix A. GMS800 Series Instruction

A-12

6. Control Operation & etc.

NO.

MNENONIC

CODE

BYTE

NO.

CYCLE

OPERATION

FLAG

NVGBHIZC

BRK

Software interrupt:

- - - 1 - 0 - -

"1", M(SP)

(PC

), SP

SP - 1,

M(s)

(PC

), SP

S - 1, M(SP)

PSW,

SP - 1, PC

(0FFDE

), PC

(0FFDF

)

Disable interrupts : I

"0"

- - - - - 0 - -

Enable interrupts : I

"1"

- - - - - 1 - -

NOP

No operation

- - - - - - - -

POP A

Pop from stack

- - - - - - - -

POP X

SP + 1, Reg.

M(SP)

POP Y

POP PSW

(restored)

PUSH A

Push to stack

- - - - - - - -

PUSH X

M(SP)

Reg. SP

SP - 1

PUSH Y

PUSH PSW

RET

Return from subroutine :

- - - - - - - -

SP+1, PC

M(SP), SP

SP+1, PC

M(SP)

RETI

Return from interrupt :

(restored)

SP+1, PSW

M(SP), SP

SP+1,PC

M(SP),

SP+1, PC

M(SP)

STOP

Stop mode (halt CPU, stop oscillator)

- - - - - - - -

Appendix B. Programmer's guide

B-1

1. General Circuit Diagram of GMS81C50 series

OSC

TR1

GMS 81

C50

GND

0.1uF

20u

0.1

i
c

a
to

r L

VCC

vcc

Infrared LED

4MHz

Filter for Vcc-GND

noise

R00

R01

R02

R03

R04

R05

R06

R07

XIN

R10

R11

R12

R13

TEST

R34

R35

VDD

R36

R37

XOUT

R27

R26

R25

R24

R23

R22

R21

R20

R16

R40

REMOUT

R15

R14

RESET

R33

VSS

R32

R31

R30

R17

VCC

R15

R14

R13

R12

R10

R30

R00

R01

R02

R03

R04

R05

R06

R07

R16

R23

R22

R21

R20

R17

113

114

115

116

117

118

119

120

R26

121

122

123

124

125

126

127

128

R27

100

101

102

103

104

R24

105

106

107

108

109

110

111

112

R25

Appendix B. Programmer's guide

B-3

2. Mask Option List Example Refer to Circuit B-1

Note: Caution: When the power to the MCU would be de-
creased under LVD, all I/O ports are changed to input ports
with pull up resistor. In below cases, you must take care of
selecting the pull up in LVD.. You must detach the pull up
of I/O port at thease cases.
Case1 : When any I/O port is connected to GND, the cur-

rent will flow from the Pull up to GND. It cause the large
power consumption and RAM would not be retained
enough to satisfy your want.
Case2 : The case of using any I/O port for controlling PNP
TR., The TR is always turn on by the Pull up of I/O port in
LVD mode

< Case 1 >

< Case 2 >

GMS81C50 MASK OPTION LIST

LG Semicon Co., Ltd.
M/L Application Team.

Code Name : GMS81C5016 - Uxxx

1. Device & Package

Date :

Company Name :

Section Name :

Signature :

28PIN : SOP 28 PIN : Skinny DIP
40PIN : PDIP

44PIN : MQFP

Y : Yes N : No

- R0 PORT

< NOTICE >
. *1 : is not available for 28PIN & 40PIN. So, Default option is Pull-Up.
. *2 : is not available for 28PIN. So, Default Option is Pull-Up.
. *3 : is for selecting Pull-up in LVD mode.

GMS81C5008
GMS81C5016

GMS81C5004

GMS81C5032

GMS81C5024

44PIN : PLCC

3. Low Voltage Detection
(Means RAM retention)

Y/N

Port

R00

Y/N

R01

R02

R03

R04

R05

R06

R07

- R1 PORT

Port

R10

Y/N

R11

R12

R13

R14

R15

R16

R17

- R2 PORT

Port

R20

Y/N

R21

R22

R23

R24

R25 *2

R26 *2

R27 *2

- R3 PORT

Port

R30 *2

Y/N

R31 *2

R32 *2

R33 *2

R34 *2

R35 *2

R36 *2

R37 *2

- R4 PORT

Port

R40 *2

Y/N

Y : Yes N : No

Y/N*3

R00

Indi

a
tor LED

PNP

Appendix B. Programmer's guide

B-4

3. Key Scan

To secure the key board scanning , read the input port after
minimum 60uS delay time from output port set to `Low `.
This time delay is for the port rising time depend on the in-
put pull-up resistor .

; program example ,See the Figure B-1 circuit.
ldm R1,#1111_1110b ;R10 port set to LOW
call delay_60uS ;60uS time delay routine
lda R0 ;R0 port Read

< Fig B-2 , Input with pull-up port read time method >

* Current Consumption

The current consumption during the Pulse transmission de-
pends on the external circuit and each Protocol. Normally
, if you used Fig B-1 circuit., the operation current is 15mA

~ 25mA (Max 45mA). But this value is normal case. Some
special protocol can be possible to consume more larger
current.

R10

R11

60uS

R0 port Read timing

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81C50

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81C50