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Version 2.01

Published by
MCU Application Team

Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Representatives listed
at address directory.

Hynix semiconductor reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconductor is in no way responsible
for any violations of patents or other rights of the third party generated by the use of this manual.

REVISION HISTORY

VERSION 2.01 (APR., 2001) This book

Delete product of 52SDIP package also, no longer produce 52pin MCU.
The compay name Hyundai Electronics Industires Co., Ltd. changed to Hynix Semiconductor Inc.

VERSION 2.00 (FEB., 2001)

Delete product of 52LQFP package.
Fixed some errata that pin number 25 and 26 on 52SDIP package are reversed.

VERSION 1.02 (NOV., 2000)

Fixed the name of LCR register on page 39 and 75, the BUR register on page 66.

VERSION 1.01 (SEP., 2000) sticker

Correct the bit LVDE of LVDR register on page 91.

GMS81C7008/7016/7108/7116

APR., 2001 Ver 2.01

Table of Contents

1. OVERVIEW............................................1

Description .........................................................1

Features .............................................................1

Development Tools ............................................2

Ordering Information ..........................................2

2. BLOCK DIAGRAM .................................3

3. PIN ASSIGNMENT ................................4

4. PACKAGE DIMENSION ........................5

5. PIN FUNCTION......................................6

6. PORT STRUCTURES............................9

7. ELECTRICAL CHARACTERISTICS ....11

Absolute Maximum Ratings .............................11

Recommended Operating Conditions ..............11

DC Electrical Characteristics ...........................11

A/D Converter Characteristics .........................13

AC Characteristics ...........................................13

Serial Interface Timing Characteristics ............15

Typical Characteristics .....................................16

8. MEMORY ORGANIZATION.................18

Registers ..........................................................18

Program Memory .............................................21

Data Memory ...................................................24

List of Control Registers ...................................25

Addressing Mode .............................................28

9. I/O PORTS ...........................................32

Registers for Port .............................................32

I/O Ports Configuration ....................................33

10. CLOCK GENERATOR .......................37

11. OPERATION MODE ..........................39

Operation Mode Switching ...............................40

12. BASIC INTERVAL TIMER..................42

13. TIMER/EVENT COUNTER ................44

8-bit Timer / Counter Mode ..............................47

16-bit Timer / Counter Mode ............................51

8-bit Capture Mode ..........................................52

16-bit Capture Mode ........................................53

Timer output port mode ....................................53

PWM Mode ......................................................54

14. ANALOG DIGITAL CONVERTER .....57

15. SERIAL COMMUNICATION ..............59

Transmission/Receiving Timing ...................... 60

The method of Serial I/O ................................. 61

The Method to Test Correct Transmission ...... 61

16. BUZZER FUNCTION .........................62

17. INTERRUPTS ....................................64

Interrupt Sequence .......................................... 66

BRK Interrupt .................................................. 67

Multi Interrupt .................................................. 67

External Interrupt ............................................. 68

Key Scan Interrupt .......................................... 68

18. LCD DRIVER .....................................70

LCD Control Registers .................................... 70

Duty and Bias Selection of LCD driver ............ 72

Selecting Frame Frequency ............................ 72

LCD Display Memory ...................................... 75

Control Method of LCD Driver ......................... 76

19. WATCH / WATCHDOG TIMER .........78

Watch Timer .................................................... 78

Watchdog Timer .............................................. 78

20. POWER DOWN OPERATION...........81

SLEEP Mode ................................................... 81

STOP Mode .................................................... 82

21. OSCILLATOR CIRCUIT.....................85

22. RESET ...............................................86

External Reset Input ........................................ 86

Watchdog Timer Reset ................................... 86

23. POWER FAIL PROCESSOR.............87

24. DEVELOPMENT TOOLS...................89

OTP Programming .......................................... 89

Emulator EVA. Board Setting .......................... 90

Appendix

A. MASK ORDER SHEET .......................... i

B. INSTRUCTION ...................................... ii

Terminology List .................................................ii

Instruction Map .................................................. iii

GMS81C7008/7016

APR., 2001 Ver 2.01

GMS81C7008/16

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

WITH LCD DRIVER & A/D CONVERTER

1. OVERVIEW

1.1 Description

The GMS81C7008/7016 is advanced CMOS 8-bit microcontrollers with 8K/16K bytes of ROM. There are a powerful microcontroller
which provides a highly flexible and cost effective solution to many LCD applications. These provide the following standard features:16K/
8K bytes of mask type ROM or 16K bytes OTP ROM, 448 bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10 bit high speed PWM
Output, programmable buzzer driving port, 8-bit basic interval timer, watch dog timer, serial peripheral interface, on chip oscillator and
clock circuitry. They also come with 4com/24seg LCD driver. In addition, it support power saving mode to reduce power consumption.

1.2 Features

· 8K/16K Bytes On-chip Programmable ROM

· 448 Bytes of On-chip Data RAM

(Included stack area and 27 nibbles LCD Display
RAM)

· Instruction Execution Time

s at 4MHz (2cycle NOP Instruction)

· One 8-bit Basic Interval Timer

· One Watch Timer

· One Watchdog Timer

· Four 8-bit Timer/Event Counter

(or Two 16-bit Timer/Event Counter)

· Two channel 10-bit High Speed PWM Output

· Three External Interrupt input ports

· One Programmable 6-bit Buzzer Driving port

- 500Hz ~ 250kHz@4MHz

· 49 I/O Ports

· Eight channel 8-bit A/D converter

· One 8-bit Serial Communication Interface

· LCD Display/ Controller

- Static Mode (27SEG x 1COM, Static)
- 1/2 Duty Mode (26SEG x 2COM, 1/2 or 1/3 Bias)
- 1/3 Duty Mode (25SEG x 3COM, 1/3 Bias)
- 1/4 Duty Mode (24SEG x 4COM, 1/3 Bias)

- Internal Built-in Resistor Circuit for Bias

· Thirteen Interrupt sources

- Basic Interval Timer: 1
- External input: 3
- Timer/Event counter: 4
- ADC: 1
- Serial Interface: 1
- WT:1
- WDT: 1
- Key Scan: 1

· Main Clock Oscillation (1.0~4.5MHz)

- Crystal
- Ceramic Resonator
- External R Oscillator (Built-in Capacitor)

· Sub Clock Oscillation

- 32.768kHz Crystal Oscillator

· Power Saving Operation Mode

- Main / Sub Active mode changeable
- 2/8/16/64 divided system clock selectable

· Power Down Mode

- STOP mode
- SLEEP mode
- Sub active Mode

· 2.7V to 5.5V Wide Operating Voltage Range

· Noise Immunity Circuit for EMS

Device name

ROM Size

RAM Size

I/O

OTP

Package

GMS81C7008

8K bytes

448 bytes

GMS87C7016

64SDIP, 64MQFP

GMS81C7016

16K bytes

448 bytes

GMS87C7016

GMS81C7008/7016

APR., 2001 Ver 2.01

- Power fail processor
- Built in Noise filter

· 64SDIP, 64LQFP package types

· Available 16K bytes OTP version

1.3 Development Tools

Note: There are several setting switches in the Emulator.
User should read carefully and do setting properly before
developing the program refer to "24.2 Emulator EVA. Board
Setting" on page 90. Otherwise, the Emulator may not work
properly.

The GMS81C7008/16 is supported by a full-featured macro as-
sembler, an in-circuit emulator CHOICE-Dr.

and OTP pro-

grammers. There are two different type programmers, one is
single type, another is gang type. For more detail, refer to OTP
Programming chapter. Macro assembler operates under the MS-

Windows 95/98

Please contact sales part of Hynix semiconductor.

1.4 Ordering Information

Software

- MS- Window base assembler
- Linker / Editor / Debugger

Hardware
(Emulator)

- CHOICE-Dr.
- CHOICE-Dr. EVA 81C51/81C7X B/D

OTP program-
mer

- CHOICE-SIGMA (Single type)
- CHOICE-GANG4 (4-gang type)

Device name

ROM Size (bytes)

RAM size

Package

Mask ROM version

GMS81C7008 K
GMS81C7016 K
GMS81C7008 Q
GMS81C7016 Q

8K bytes
16K bytes
8K bytes
16K bytes

448 bytes
448 bytes
448 bytes
448 bytes

64SDIP
64SDIP
64MQFP
64MQFP

OTP ROM version

GMS87C7016 K
GMS87C7016 Q

16K bytes OTP
16K bytes OTP

448 bytes
448 bytes

64SDIP
64MQFP

GMS81C7008/7016

APR., 2001 Ver 2.01

2. BLOCK DIAGRAM

GMS81C7008/7016

ALU

LCD Controller / Driver (LCDC)

Accumulator

Stack Pointer

Interrupt Controller

Data

Memory

LCD Display

Memory

Program

Memory

Data Table

8-bit Basic

Interval Tim er

High Speed

Buzzer

Driver

PSW

System controller

Timing generator

System

Clock Controller

Clock

Generator

High freq.

Low freq.

RESET

XIN

XOUT

SXIN

SXOUT

Common Drive Output

COM0

R00 / INT0
R01 / INT1
R02 / INT2
R03 / EC0
R04 / EC2
R05 / SCK
R06 / SO
R07 / SI

R10
R11

R30 / BUZ

VDD
VSS

Power
Supply

VCL0
VCL1
VCL2

COM1/SEG26
COM2/SEG25
COM3/SEG24

LCD Power

Control Circuit

AVDD
AVSS

Power

Supply

Circuit

BIAS

R20 / AN0

R31 / PWM0 / T1O
R32 / PWM1 / T3O
R33

R21 / AN1
R22 / AN2
R23 / AN3

8-bit

A /D C onverter

PWM

8-bit

Tim er/C ounter

SIO

R24 / AN4
R25 / AN5
R26 / AN6
R27 / AN7

R34 / WDTO

Watch/

Timer

R35 / SXOUT

R36 / SXIN

Segment Drive Output

SEG0 ~ SEG23

R40-R47

Watchdog

Key

Scan

R50-R56

R60-R67

LCD Power
Supply

GMS81C7008/7016

APR., 2001 Ver 2.01

3. PIN ASSIGNMENT

VCL0
VCL1
VCL2
AV

R20
R21
R22
R23

BIAS

OUT

RESET

R36
R35

AN0
AN1
AN2
AN3

PWM1 / T3O

PWM0 / T1O

BUZ

WDTO

R24
R25
R26
R27
R07
R06
R05
R04
R03
R02
R01
R00
R11
R10
R34
R33

EC2
EC0

INT2
INT1
INT0

COM3
COM2
COM1
COM0

R67
R66
R65
R64
R63
R62
R61
R60
R57
R56
R55
R54
R53
R52
R51
R50
R47
R46
R45
R44
R43
R42
R41
R40

R30
R31
R32

R21

R66
R67

COM0
COM1
COM2
COM3

VCL0
VCL1
VCL2
AV

R20

AN1

SEG22

R02

R42
R41
R40

R30
R31
R32
R33
R34
R10
R11
R00
R01

INT2

INT0
INT1

RESET

AN2

AN4

AN5

AN6

AN7

SCK

AN3

EC2

EC0

32
31
30
29
28
27
26
25
24
23
22
21
20

52
53
54
55
56
57
58
59
60
61
62
63
64

64MQFP

64SDIP

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

GMS

1C
7

008

/70

GMS81C7008/7016

(Top View)

AN4
AN5
AN6
AN7

OUT

SCK

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG26

SEG25

SEG24

WDTO

PWM1/T3O

PWM0/T1O

BUZ

SEG0

SEG1

SEG2

SEG

SEG23

AN0

SEG26
SEG25
SEG24

KS1
KS0

KS0
KS1

GMS81C7008/7016

APR., 2001 Ver 2.01

5. PIN FUNCTION

: Supply voltage.

: Circuit ground.

RESET: Reset the MCU.

: Supply voltage to the ladder resistor of ADC circuit. To

enhance the resolution of analog to digital converter, use inde-
pendent power source as well as possible, other than digital pow-
er source.

: ADC circuit ground.

: Input to the inverting oscillator amplifier and input to the in-

ternal main clock operating circuit.

OUT

: Output from the inverting oscillator amplifier.

BIAS: LCD bias voltage input pin.

VCL0~VCL2: LCD driver power supply pins. The voltage on
each pin is VCL2

VCL1

VCL0. For details, Refer to "18. LCD

DRIVER" on page 70.

COM0~COM3: LCD common signal output pins. Also, the pins
of COM1,COM2 and COM3 are shared with LCD segment sig-
nal outputs of SEG26, SEG25, SEG24 as application require-
ment.

: Input to the internal subsystem clock operating circuit. In

addition, SX

is shared with the R36 which is selected by the

software option.

OUT

: Output from the inverting subsystem oscillator amplifi-

er. In addition, SX

OUT

is shared with the R35 which is selected

by the software option.

R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1
or 0 written to the Port Direction Register can be used as outputs
or schmitt trigger inputs. Also, pull-up resistors and open-drain
outputs are software assignable.

In addition, R0 serves the functions of the various following spe-
cial features.

R10~R11: R1 is a 2-bit CMOS bidirectional I/O port. R1 pins 1
or 0 written to the Port Direction Register can be used as outputs
or inputs. Also, pull-up resistors and open-drain outputs are soft-

ware assignable. These pins are not served on 81C71XX.

In addition, R0 serves the functions of the various following spe-
cial features.

R20~R27: R2 is an 8-bit CMOS bidirectional I/O port. R2 pins 1
or 0 written to the Port Direction Register can be used as outputs
or inputs. Also, pull-up resistors and open-drain outputs are soft-
ware assignable.R24~R27 are not served on 81C71XX.

In addition, R2 is shared with the ADC input.

R30~R36: R3 is a 7-bit CMOS bidirectional I/O port. R3 pins 1
or 0 written to the Port Direction Register can be used as outputs
or inputs. Also, pull-up resistors and open-drain outputs are soft-
ware assignable. R33, R34 are not served on 81C71XX.

In addition, R3 serves the functions of the various follow-
ing special features.

SEG0~SEG7: These pins generate LCD segment signal output.
Every LCD segment pins are shared with normal R4 input/output
port. R4 is an 8-bit CMOS bidirectional I/O port. R4 pins 1 or 0
written to the Port Direction Register can be used as outputs or in-

Port pin

Alternate function

R00
R01
R02
R03
R04
R05
R06
R07

INT0 (External interrupt 0)
INT1 (External interrupt 1)
INT2 (External interrupt 2)
EC0 (Event counter input 0)
EC2 (Event counter input 2)
SCK (Serial clock)
SO (Serial data output)
SI (Serial data input)

Port pin

Alternate function

R00
R01

KS0 (Key scan 0)
KS1 (Key scan 1)

Port pin

Alternate function

R20
R21
R22
R23
R24
R25
R26
R27

AN0 (Analog Input 0)
AN1 (Analog Input 1)
AN2 (Analog Input 2)
AN3 (Analog Input 3)
AN4 (Analog Input 4)
AN5 (Analog Input 5)
AN6 (Analog Input 6)
AN7 (Analog Input 7)

Port pin

Alternate function

R30
R31

R32

R33
R34
R35
R36

BUZ (Buzzer driving output)
PWM0 / T1O (PWM 0 output
/ Timer 1 output)
PWM1 /T3O (PWM 1 output
/ Timer 3 output)
-
WDTO (Watchdog timer output)
SX

OUT

(Sub clock output)

(Sub clock input)

GMS81C7008/7016

APR., 2001 Ver 2.01

puts.

SEG8~SEG15: These pins generate LCD segment signal output.
Every LCD segment pins are shared with normal R5 input/output
port. R5 is an 8-bit CMOS bidirectional I/O port. R5 pins 1 or 0
written to the Port Direction Register can be used as outputs or in-
puts.

SEG16~SEG23: These pins generate LCD segment signal out-
put.
Every LCD segment pins are shared with normal R6 input/output
port. R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0
written to the Port Direction Register can be used as outputs or in-
puts.

LCD pin function

Port pin

SEG0 (LCD segment 0 signal output)
SEG1 (LCD segment 1 signal output)
SEG2 (LCD segment 2 signal output)
SEG3 (LCD segment 3 signal output)
SEG4 (LCD segment 4 signal output)
SEG5 (LCD segment 5 signal output)
SEG6 (LCD segment 6 signal output)
SEG7 (LCD segment 7 signal output)

R40
R41
R42
R43
R44
R45
R46
R47

LCD pin function

Port pin

SEG8 (LCD segment 8 signal output)
SEG9 (LCD segment 9 signal output)
SEG10 (LCD segment 10 signal output)
SEG11 (LCD segment 11 signal output)
SEG12 (LCD segment 12 signal output)
SEG13 (LCD segment 13 signal output)
SEG14 (LCD segment 14 signal output)
SEG15 (LCD segment 15 signal output)

R50
R51
R52
R53
R54
R55
R56
R57

LCD pin function

Port pin

SEG16 (LCD segment 16 signal output)
SEG17 (LCD segment 17 signal output)
SEG18 (LCD segment 18 signal output)
SEG19 (LCD segment 19 signal output)
SEG20 (LCD segment 20 signal output)
SEG21 (LCD segment 21 signal output)
SEG22 (LCD segment 22 signal output)
SEG23 (LCD segment 23 signal output)

R60
R61
R62
R63
R64
R65
R66
R67

GMS81C7008/7016

APR., 2001 Ver 2.01

PIN NAME

(Alternate)

In/Out

(Alternate)

Function

Basic

Alternate

Supply voltage

Circuit ground

RESET

Reset signal input

Supply voltage input pin for ADC

Ground level input pin for ADC

Oscillation input

OUT

Oscillation output

BIAS

LCD bias voltage input

VCL0~VCL2

LCD driver power supply

COM0

LCD common signal output

COM1(SEG26)

O(O)

LCD common signal output

LCD segment signal output

COM2(SEG25)

O(O)

COM3(SEG24)

O(O)

R00 (INT0)

I/O (I)

8-bit general I/O ports

External interrupt 0 input

R01 (INT1)

I/O (I)

External interrupt 1 input

R02 (INT2)

I/O (I)

External interrupt 2 input

R03 (EC0)

I/O (I)

Timer/Counter 0 external input

R04 (EC2)

I/O (I)

Timer/Counter 1 external input

R05 (SCK)

I/O (I/O)

Serial clock I/O

R06 (SO)

I/O (O)

Serial data output

R07 (SI)

I/O (I)

Serial data input

R10, R11(KS0, KS1)

I/O (I)

2-bit general I/O ports

Key scan input

R20~R27(AN0~AN7)

I/O(I)

8-bit general I/O ports

Analog voltage input

R30(BUZ)

I/O(O)

7-bit general I/O ports

Buzzer driving output

R31(PWM0 / T1O)

I/O(O)

PWM 0 output / Timer 1 output

R32(PWM1 / T3O)

I/O(O)

PWM 1 output / Timer 2 output

R33

I/O

R34(WDTO)

I/O(O)

Watchdog timer output

R35(SX

OUT

)

I/O(O)

Sub clock output

R36(SX

)

I/O(I)

Sub clock input

SEG0 ~ SEG7
(R40~R47)

O (I/O)

LCD segment signal output

8-bit general I/O ports

SEG8 ~ SEG15
(R50~R57)

O (I/O)

LCD segment signal output

8-bit general I/O ports

SEG16 ~ SEG23
(R60~R67)

O (I/O)

LCD segment signal output

8-bit general I/O ports

Table 5-1 Port Function Description

GMS81C7008/7016

APR., 2001 Ver 2.01

6. PORT STRUCTURES

R00/INT0, R01/INT1, R02/INT2, R03/EC0,
R04/EC2, R05/SCK, R07/S

R30/BUZ, R31/PWM0/T1O, R32/PWM1/T3O,
R34/WDTO, R06

R20/AN0~R27/AN7

R10~R11, R33, R35, R36

RESET

SXIN, SXOUT

Data Reg.

Dir. Reg.

Noise

Canceller

INT0 ~ INT2

Pull up

Reg.

M U X

Pull-up Tr.

EC0,EC2

Open Drain

Reg.

SI,SCK

Tr.: Transistor
Reg.: Register

Data Reg.

Dir. Reg.

Pull up

Reg.

M U X

Pull-up Tr.

Open Drain

Reg.

BUZ,SO,WDTO

PWM0,PWM1

Data Reg.

Dir. Reg.

Analog

Switch

AN0 ~ AN 7

P ull up

Reg.

M U X

Pull-up Tr.

Open Drain

Reg.

ta B

Data Reg.

Dir. Reg.

Pull up

Reg.

M U X

Pull-up Tr.

Open Drain

Reg.

RESET

Noise

Canceller

Internal RESET

High Voltage On(OTP)

OTP MCU :disconnected
Mask MCU :connected

OTP MCU :connected
Mask MCU :disconnected

SXOUT

Internal

SXIN

Sub clock OFF

(R35)

(R36)

System Clock

LCR.7=0

GMS81C7008/7016

APR., 2001 Ver 2.01

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage ........................................... -0.3 to +6.0 V

Storage Temperature ................................-40 to +125

Voltage on any pin with respect to Ground (V

)

............................................................... -0.3 to V

+0.3

Maximum current out of V

pin ........................100 mA

Maximum current into V

pin ............................80 mA

Maximum current sunk by (I

per I/O Pin) ........20 mA

Maximum output current sourced by (I

per I/O Pin)

...............................................................................15 mA

Maximum current (

) .................................... 100 mA

Maximum current (

)...................................... 60 mA

Note: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.

7.2 Recommended Operating Conditions

7.3 DC Electrical Characteristics

=-20~85

C, V

=2.7~5.5V)

Parameter

Symbol

Condition

Specifications

Unit

Min.

Max.

Supply Voltage

XIN

=4.19MHz

SXIN

=32.768kHz

2.7

5.5

Operating Frequency

XIN

=2.7~5.5V

4.5

MHz

Sub Operating Frequency

SXIN

=2.7~5.5V

kHz

Operating Temperature

OPR

-20

+85

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

Input High Voltage

IH1

RESET, R0 (except R06)

0.8 V

IH2

Other pins

0.7 V

Input Low Voltage

IL1

RESET, R0 (except R06)

0.2 V

IL2

Other pins

0.3 V

Output High Voltage

OH1

R0,R1,R2,R3 I

OH1

=-0.5mA

-0.1

OH2

SEG, COM I

OH2

=-30

0.4

Output Low Voltage

OL1

R0,R1,R2,R3 I

OL1

=0.4mA

0.2

OL2

SEG, COM I

OL2

=30

-0.2

Input High
Leakage Current

IH1

, All input pins except X

, SX

IH2

DD,

, SX

GMS81C7008/7016

APR., 2001 Ver 2.01

Input Low
Leakage Current

IL1

=0, All input pins except X

, SX

-1

IL2

, SX

-20

Pull-up Resistor

PORT

=0V, V

=5.5V, R0, R1, R2

160

350

LCD Voltage Dividing
Resistor

LCD

=5.5V

Voltage Drop
|V

-COM

n| , n=0~3

=2.7 ~ 5.5V

-15

A per common pin

120

Voltage Drop
|V

-SEG

n| , n=0~26

=2.7 ~ 5.5V

-15

A per segment pin

120

CL2

Output Voltage

CL2

=2.7 ~ 5.5V, 1/3 bias

BIAS pin and VCL2 pin are shorted

-0.3

+0.3

CL1

Output Voltage

CL1

0.66V

-0.2

0.66V

+0.3

CL0

Output Voltage

CL0

0.33V

-0.3

0.33V

+0.3

RC Oscillation Fre-
quency

R=60k

, V

= 5V

MHz

Supply Current

( ) means at 3V opera-
tion

DD1

Main clock operation mode

=5.5V

10%, X

=4MHz, S

XIN

=32kHz

2.9

(1.3)

7.0

(3.0)

DD2

Sleep mode (Main active)

=5.5V

10%, X

=4MHz, S

XIN

=32kHz

0.4

(0.1)

1.7

(1.0)

DD3

Stop mode

=5V

10%, X

= 0Hz, S

XIN

=32kH z

2.0

(1.0)

(5)

DD4

Sub clock operation mode

=5.5V

10%, X

=0Hz, S

XIN

=32kHz

350

(70)

500

(200)

DD5

Sleep mode (Sub active)

=3V

10%, X

= 0Hz, S

XIN

=32kH z

(3)

(20)

DD6

Stop mode

=5V

10%, X

= 0Hz, S

XIN

=0H z

XIN

, SXOUT are used as R35, R36.

1.0

(0.5)

(5)

1. Supply current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, comparator volt-

age divide resistor, LVD circuit and output port drive currents.

2. This mode set System Clock Mode Register(SCMR) to xxxx0000

that is f

XIN

3. This mode set SCMR to xxxx0000

XIN

/2) and set SMR to "1".

4. Main-frequency clock stops and sub-frequency clock in not used and set SCMR to xxxx0011

5. Main-frequency clock stops and sub-frequency clock in not used, set SCMR to xxxx0011

and set SMR to "1".

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

GMS81C7008/7016

APR., 2001 Ver 2.01

7.4 A/D Converter Characteristics

=25

C, V

=0V, V

=5.0V, AV

=5.0V @f

XIN

=4MHz)

7.5 AC Characteristics

=-20~+85

C, V

=5V

10%

=0V)

Parameter

Symbol

Test Condition

Specifications

Unit

Min.

Typ.

1. Data in "Typ" column is at 25

C unless otherwise stated. These parameters are for design guidance only and are not tested.

Max.

Analog Input Voltage Range

AIN

=AV

=5.0V

-0.3

+0.3

Non-linearity Error

NLE

1.0

±1.5

LSB

Differential Non-linearity Error

DNLE

1.0

±1.5

LSB

Zero Offset Error

ZOE

0.5

±1.5

LSB

Full Scale Error

FSE

0.25

±0.5

LSB

Gain Error

1.0

±1.5

LSB

Overall Accuracy

ACC

1.0

±1.5

LSB

Input Current

REF

200

Conversion Time

CONV

Analog Power Supply Input Range

=5.0V

=3.0V

3.0
2.7

Parameter

Symbol

Pins

Specifications

Unit

Min.

Typ.

Max.

Operating Frequency

MAIN

0.455

4.2

MHz

SUB

32.768

kHz

External Clock Pulse Width

MCPW

SCPW

14.7

External Clock Transition Time

MRCP,

MFCP

SRCP,

SFCP

Main oscillation Stabilizing
Time

MST

, X

OUT

at 4MHz

Sub oscillation Stabilizing Time

SST

, SX

OUT

0.5

Interrupt Pulse Width

INT0, INT1, INT2

SYS

RESET Input Width

RST

RESET

SYS

Event Counter Input Pulse
Width

ECW

EC0, EC2

SYS

1. t

SYS

is one of 2/f

MAIN

or 8/f

MAIN

or 16/f

MAIN

or 64/f

MAIN

in the main clock operation mode,

SYS

is one of 2/f

SUB

or 8/f

SUB

or 16/f

SUB

or 64/f

SUB

in the sub clock operation mode.

GMS81C7008/7016

APR., 2001 Ver 2.01

7.6 Serial Interface Timing Characteristics

=-20~+85

C, V

=2.7~5.5V, V

=0V, f

XIN

=4MHz)

Figure 7-2 Serial I/O Timing Chart

Parameter

Symbol

Pins

Specifications

Unit

Min.

Typ.

Max.

Serial Input Clock Pulse

SCYC

SCK

SYS

+200

Serial Input Clock Pulse Width

SCKW

SCK

SYS

+70

SIN Input Setup Time (External SCK)

SUS

SIN

100

SIN Input Setup Time (Internal SCK)

SUS

SIN

200

SIN Input Hold Time

SIN

SYS

+70

Serial Output Clock Cycle Time

SCYC

SCK

SYS

16t

SYS

Serial Output Clock Pulse Width

SCKW

SCK

SYS

-30

Serial Output Clock Pulse Transition
Time

FSCK

RSCK

SCK

Serial Output Delay Time

OUT

100

SCLK

SIN

0.2V

SOUT

0.2V

0.8V

SCYC

SCKW

RSCK

FSCK

0.8V

SUS

0.2V

0.8V

GMS81C7008/7016

APR., 2001 Ver 2.01

7.7 Typical Characteristics

This graphs and tables provided in this section are for de-
sign guidance only and are not tested or guaranteed.

In some graphs or tables the data presented are out-
side specified operating range (e.g. outside specified
V

range). This is for information only and devices

are guaranteed to operate properly only within the
specified range.

The data presented in this section is a statistical summary
of data collected on units from different lots over a period
of time. "Typical" represents the mean of the distribution
while "max" or "min" represents (mean + 3

) and (mean

) respectively where

is standard deviation

-
-
-
-

, V

=5.5V

(mA)

(V)

-
-
-
-

, V

=3.0V

(mA)

0.5

1.0 1.5

2.0

2.5

(V)

-
-
-
-

, V

=5.0V

-20

-15

-10

-5

(mA)

(V)

-
-
-
-

, V

=3.0V

-8

-6

-4

-2

(mA)

0.5

1.0 1.5

2.0

2.5

(V)

Ta=25

R0,R1,R2,R3 pin

200

100

)

-20

(

XIN

=4MHz

-
-
-
-

IH1

(V)

IH1

(V)

-
-
-
-

IH2

(V)

IH2

(V)

Ta=25

XIN

=4MHz

Ta=25

R0 (except R06)

R1~R6 pin

(include R06)

XIN

=4MHz

-
-
-
-

IH3

(V)

IH1

(V)

Ta=25

, SX

R = 6.2k

(MHz)

XIN

(V)

Ta=25

R = 20k

R = 180k

R = 60k

XIN

-
-
-
-

Ta=25

-
-
-
-

, V

=5.0V

GMS81C7008/7016

APR., 2001 Ver 2.01

STOP

(
(
(
(

DD6

)

-
-
-
-

STOP Mode

DD1

-
-
-
-

(mA)

(V)

Normal Operation (Main opr.)

DD4

-
-
-
-

400

300

200

100

(

(V)

Normal Mode (Sub opr.)

SLEEP

DD5

)

-
-
-
-

SLEEP Mode (Sub opr.)

SLEEP

DD2

)

-
-
-
-

XIN

=4MHz

-
-
-
-

IL1

(V)

IH1

(V)

-
-
-
-

IL2

(V)

IH2

(V)

Ta=25

XIN

=4MHz

Ta=25

R0 (except R06)

R1~R6 pin
(include R06)

XIN

=4MHz

-
-
-
-

IL3

(V)

IH1

(V)

Ta=25

, SX

SLEEP Mode (Main opr.)

SXIN

=32kHz

Ta=25

400

300

200

100

(

(V)

(

(V)

SXIN

=32kHz

Ta=25

STOP

DD3

)

-
-
-
-

STOP Mode

(

(V)

XIN

=0Hz

Ta=25

XIN

=4MHz

Ta=25

XIN

=4MHz

Ta=25

(

(V)

SXIN

=0Hz

Ta=25

GMS81C7008/7016

APR., 2001 Ver 2.01

8. MEMORY ORGANIZATION

The GMS81C7008/16 has separate address spaces for Program
memory and Data Memory. Program memory can only be read,
not written to. It can be up to 8K/16K bytes of Program memory.

Data memory can be read and written to up to 448 bytes including
the stack area and the LCD display RAM area.

8.1 Registers

This device has six registers that are the Program Counter (PC),
a Accumulator (A), two index registers (X, Y), the Stack Pointer
(SP), and the Program Status Word (PSW). The Program Counter
consists of 16-bit register.

Figure 8-1 Configuration of Registers

Accumulator: The Accumulator is the 8-bit general purpose reg-
ister, used for data operation such as transfer, temporary saving,
and conditional judgement, etc.

The Accumulator can be used as a 16-bit register with Y Register
as shown below.

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers: In the addressing mode which uses these index
registers, the register contents are added to the specified address,
which becomes the actual address. These modes are extremely ef-
fective for referencing subroutine tables and memory tables. The
index registers also have increment, decrement, comparison and
data transfer functions, and they can be used as simple accumula-
tors.

Stack Pointer: The Stack Pointer is an 8-bit register used for oc-
currence interrupts and calling out subroutines. Stack Pointer
identifies the location in the stack to be access (save or restore).

Generally, SP is automatically updated when a subroutine call is
executed or an interrupt is accepted. However, if it is used in ex-

cess of the stack area permitted by the data memory allocating
configuration, the user-processed data may be lost.

The stack can be located at any position within 011B

to 01FF

of the internal data memory. The SP is not initialized by hard-
ware, requiring to write the initial value (the location with which
the use of the stack starts) by using the initialization routine. Nor-
mally, the initial value of "FF

" is used.

Note: The Stack Pointer must be initialized by software be-
cause its value is undefined after RESET.

Example: To initialize the SP

LDX

#0FFH

TXSP

; SP

FFH

Program Counter: The Program Counter is a 16-bit wide which
consists of two 8-bit registers, PCH and PCL. This counter indi-
cates the address of the next instruction to be executed. In reset
state, the program counter has reset routine address (PC

:0FF

:0FE

Program Status Word: The Program Status Word (PSW) con-
tains several bits that reflect the current state of the CPU. The
PSW is described in Figure 8-3. It contains the Negative flag, the
Overflow flag, the Break flag the Half Carry (for BCD opera-
tion), the Interrupt enable flag, the Zero flag, and the Carry flag.

[Carry flag C]

This flag stores any carry or not borrow from the ALU of CPU
after an arithmetic operation and is also changed by the Shift In-
struction or Rotate Instruction.

[Zero flag Z]

This flag is set when the result of an arithmetic operation or data
transfer is "0" and is cleared by any other result.

ACCUMULATOR

X REGISTER

Y REGISTER

STACK POINTER

PROGRAM COUNTER

PROGRAM STATUS

WORD

PCL

PSW

PCH

Two 8-bit Registers can be used as a "YA" 16-bit Register

Stack Area (100

~ 1FF

)

Bit 15

Bit 0

8 7

Hardware fixed

~FF

LCD display RAM area is located in 100

~11A

SP (Stack Pointer) could be in 00

~FF

User must have concerning that Stack data does not
cross over LCD RAM area.

GMS81C7008/7016

APR., 2001 Ver 2.01

Figure 8-3 PSW (Program Status Word) Register

[Interrupt disable flag I]

This flag enables/disables all interrupts except interrupt caused
by Reset or software BRK instruction. All interrupts are disabled
when cleared to "0". This flag immediately becomes "0" when an
interrupt is served. It is set by the EI instruction and cleared by
the DI instruction.

[Half carry flag H]

After operation, this is set when there is a carry from bit 3 of ALU
or there is no borrow from bit 4 of ALU. This bit can not be set
or cleared except CLRV instruction with Overflow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish BRK
from TCALL instruction with the same vector address.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In the di-
rect addressing mode, addressing area is from zero page 00

0FF

when this flag is "0". If it is set to "1", addressing area is

assigned by RPR register (address 0F3

). It is set by SETG in-

struction and cleared by CLRG.

When content of RPR is above 2, malfunction will be occurred.

[Overflow flag V]

This flag is set to "1" when an overflow occurs as the result of an
arithmetic operation involving signs. An overflow occurs when
the result of an addition or subtraction exceeds +127(7F

) or -

128(80

). The CLRV instruction clears the overflow flag. There

is no set instruction. When the BIT instruction is executed, bit 6
of memory is copied to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the result of
a data or arithmetic operation. When the BIT instruction is exe-
cuted, bit 7 of memory is copied to this flag.

NEGATIVE FLAG

MSB

LSB

RESET VALUE: 00

PSW

OVERFLOW FLAG

BRK FLAG

CARRY FLAG RECEIVES

ZERO FLAG

INTERRUPT ENABLE FLAG

CARRY OUT

HALF CARRY FLAG RECEIVES

CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS

SELECT DIRECT PAGE

when G=1, page is selected to "page 1"

RAM Page

Instruction

Bit1 of

RPR

Bit0 of

RPR

0 page

CLRG

0 page

SETG

1 page

SETG

Reserved

SETG

Reserved

SETG

GMS81C7008/7016

APR., 2001 Ver 2.01

8.2 Program Memory

A 16-bit program counter is capable of addressing up to 64K
bytes, but this device has 8K/16K bytes program memory space
only physically implemented. Accessing a location above FFFF

will cause a wrap-around to 0000

Figure 8-5, shows a map of Program Memory. After reset, the
CPU begins execution from reset vector which is stored in ad-
dress FFFE

and FFFF

as shown in Figure 8-6.

As shown in Figure 8-5, each area is assigned a fixed location in
Program Memory. Program Memory area contains the user pro-
gram.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to reduce
program byte length by using 2 bytes PCALL instead of 3 bytes
CALL instruction. If it is frequently called, it is more useful to

save program byte length.

Table Call (TCALL) causes the CPU to jump to each TCALL ad-
dress, where it commences the execution of the service routine.
The Table Call service area spaces 2-byte for every TCALL:
0FFC0

for TCALL15, 0FFC2

for TCALL14, etc., as shown in

Figure 8-7.

Example: Usage of TCALL

The interrupt causes the CPU to jump to specific location, where
it commences the execution of the service routine. The External
interrupt 0, for example, is assigned to location 0FFFA

. The in-

terrupt service locations spaces 2-byte interval: 0FFF8

and

0FFF9

for External Interrupt 1, 0FFFA

and 0FFFB

for Exter-

nal Interrupt 0, etc.

Any area from 0FF00

to 0FFFF

, if it is not going to be used,

its service location is available as general purpose Program Mem-
ory.

Figure 8-6 Interrupt Vector Area

Interrupt

Vector Area

C000

FEFF

FF00

FFC0

FFDF

FFE0

FFFF

LL are

E000

TCALL area

701

K RO

0FFE0

Address

Vector Area Memory

Timer/Counter 3
Timer/Counter 2

Watch Timer

A/D Converter

External Interrupt 0

Timer/Counter 1

Basic Interval Timer

Key Scan

RESET

Watchdog Timer

Serial Peripheral Interface

"-" means reserved area.

NOTE:

External Interrupt 2

External Interrupt 1

Timer/Counter 0

GMS81C7008/7016

APR., 2001 Ver 2.01

Example: The usage software example of Vector address for GMS81C7016.

ORG

0FFE0H

TIMER3

; Timer-3

TIMER2

; Timer-2

WATCH_TIMER

; Watch Timer

ADC

; ADC

SIO

; Serial Interface

NOT_USED

; -

NOT_USED

; -

INT2

; Int.2

TIMER1

; Timer-1

TIMER0

; Timer-0

INT1

; Int.1

INT0

; Int.0

WD_TIMER

; Watchdog Timer

BIT_TIMER

; Basic Interval Timer

KEYSCAN

; Key Scan Timer

RESET

; Reset

ORG

0C000H

; in case of 16K ROM Start address

;

ORG

0E000H

; in case of 8K ROM Start address

;*******************************************
;

MAIN PROGRAM *

;*******************************************
;
RESET:

LDM

SCMR,#0

;When main clock mode

;Disable All Interrupts

LDM

WDTR,#0

;Disable Watch Dog Timer

LDM

RPR,#1

CLRG
LDX

RAM_CLR: LDA

;RAM Clear(!0000H ~ !00BFH)

STA

{X}+

CMPX

#0C0H

BNE

RAM_CLR

SETG
LDX

RAM_CLR1:

LDA

STA

{X}+

CMPX

#1BH

;DISPLAY RAM Clear(!0100H ~ !011AH)

BNE

RAM_CLR1

CLRG

;

LDX

#0FFH

;Stack Pointer Initialize

TXSP

;

LDM

R0, #0

;Normal Port 0

LDM

R0DD,#82H

;Normal Port Direction

LDM

R0PU,#0

;Normal Pull Up

:
:
:
LDM

TDR0,#250

;8us x 250 = 2000us

LDM

TM0,#0000_1111B

;Start Timer0, 8us at 4MHz

LDM

IRQH,#0

LDM

IRQL,#0

LDM

IENH,#0000_1110B

;Enable INT0, INT1, Timer0

LDM

IENL,#0

LDM

IEDS,#15H

;Select falling edge detect on INT pin

LDM

PMR,#3H

;Set external interrupt pin(INT0, INT1)

;Enable master interrupt

GMS81C7008/7016

APR., 2001 Ver 2.01

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space available. Data
Memory is divided into four groups, a user RAM, control regis-
ters, Stack, and LCD memory.

Figure 8-8 Data Memory Map

User Memory

The both GMS81C7008/16 has 448

8 bits for the user memory

(RAM).

There are two page internal RAM. Page is selected by G-flag and
RAM page selection register RPR. When G-flag is cleared to "0",
always page 0 is selected regardless of RPR value. If G-flag is set
to "1", page will be selected according to RPR value.

Figure 8-9 RAM page configuration

Control Registers

The control registers are used by the CPU and Peripheral function
blocks for controlling the desired operation of the device. There-
fore these registers contain control and status bits for the interrupt
system, the timer/ counters, analog to digital converters and I/O
ports. The control registers are in address range of 0C0

to 0FF

Note that unoccupied addresses may not be implemented on the
chip. Read accesses to these addresses will in general return ran-
dom data, and write accesses will have an indeterminate effect.

More detailed informations of each register are explained in each
peripheral section.

Note: Write only registers can not be accessed by bit ma-
nipulation instruction (SET1, CLR1). Do not use read-mod-
ify-write instruction. Use byte manipulation instruction, for
example "LDM".

Example; To write at CKCTLR

LDM

CKCTLR,#09H

;Divide ratio(

16)

Stack Area

The stack provides the area where the return address is saved be-
fore a jump is performed during the processing routine at the ex-
ecution of a subroutine call instruction or the acceptance of an
interrupt.

When returning from the processing routine, executing the sub-
routine return instruction [RET] restores the contents of the pro-
gram counter from the stack; executing the interrupt return
instruction [RETI] restores the contents of the program counter
and flags.

The save/restore locations in the stack are determined by the
stack pointed (SP). The SP is automatically decreased after the
saving, and increased before the restoring. This means the value
of the SP indicates the stack location number for the next save.
Refer to Figure 8-4 on page 20.

User Memory

Control

Registers

or Stack Area

0000

00BF

00C0

00FF

0100

01FF

PAGE0

User Memory

PAGE1

LCD display RAM

(27 Nibbles)

011A

011B

(192 Bytes)

(229 Bytes)

Page 0

Page 0: 00~FF

Page 1

Page 1: 100~1FF

RPR=1, G=1

G=0

GMS81C7008/7016

APR., 2001 Ver 2.01

8.4 List of Control Registers

Address

Register Name

Symbol

R/W

Initial Value

Page

7 6 5 4 3 2 1 0

00C0

R0 port data register

R/W

0 0 0 0 0 0 0 0

page 33

00C1

R1 port data register

R/W

- - - - - - 0 0

page 33

00C2

R2 port data register

R/W

0 0 0 0 0 0 0 0

page 33

00C3

R3 port data register

R/W

- 0 0 0 0 0 0 0

page 33

00C4

R4 port data register

R/W

0 0 0 0 0 0 0 0

page 34

00C5

R5 port data register

R/W

0 0 0 0 0 0 0 0

page 34

00C6

R6 port data register

R/W

0 0 0 0 0 0 0 0

page 35

00C8

R0 port I/O direction register

R0DD

0 0 0 0 0 0 0 0

page 35

00C9

R1 port I/O direction register

R1DD

- - - - - - 0 0

page 36

00CA

R2 port I/O direction register

R2DD

0 0 0 0 0 0 0 0

page 36

00CB

R3 port I/O direction register

R3DD

- 0 0 0 0 0 0 0

page 35

00CC

R4 port I/O direction register

R4DD

0 0 0 0 0 0 0 0

page 36

00CD

R5 port I/O direction register

R5DD

0 0 0 0 0 0 0 0

page 36

00CE

R6 port I/O direction register

R6DD

0 0 0 0 0 0 0 0

page 36

00D0

R0 port pull-up register

R0PU

0 0 0 0 0 0 0 0

page 33

00D1

R1 port pull-up register

R1PU

- - - - - - 0 0

page 33

00D2

R2 port pull-up register

R2PU

0 0 0 0 0 0 0 0

page 33

00D3

R3 port pull-up register

R3PU

- 0 0 0 0 0 0 0

page 33

00D4

R0 port open drain control register

R0CR

0 0 0 0 0 0 0 0

page 33

00D5

R1 port open drain control register

R1CR

- - - - - - 0 0

page 33

00D6

R2 port open drain control register

R2CR

0 0 0 0 0 0 0 0

page 33

00D7

R3 port open drain control register

R3CR

- 0 0 0 0 0 0 0

page 33

00D8

Ext. interrupt edge selection register

IEDS

R/W

- - 0 0 0 0 0 0

page 69

00D9

Port mode register

PMR

R/W

0 0 0 0 0 0 0 0 page 62, page 69

00DA

Interrupt enable lower byte register

IENL

R/W

0 - - 0 0 0 0 0

page 65

00DB

Interrupt enable upper byte register

IENH

R/W

- 0 0 0 0 0 0 0

page 65

00DC

Interrupt request flag lower byte register

IRQL

R/W

0 - - 0 0 0 0 0

page 64

00DD

Interrupt request flag upper byte register

IRQH

R/W

- 0 0 0 0 0 0 0

page 64

00DE

Sleep mode register

SMR

- - - - - - - 0

page 81

00DF

Watch dog timer register

WDTR

R/W

- - 0 1 0 0 1 0

page 79

00E0

Timer0 mode register

TM0

R/W

- - 0 0 0 0 0 0

page 45

00E1

Timer0 counter register

0 0 0 0 0 0 0 0

page 45

Timer0 data register

TDR0

1 1 1 1 1 1 1 1

page 45

Timer0 input capture register

CDR0

0 0 0 0 0 0 0 0

page 45

00E2

Timer1 mode register

TM1

R/W

0 0 0 0 0 0 0 0

page 45

Table 8-1 Control Registers

GMS81C7008/7016

APR., 2001 Ver 2.01

00E3

Timer1 data register

TDR1

1 1 1 1 1 1 1 1

page 45

PWM0 pulse period register

T1PPR

1 1 1 1 1 1 1 1

page 54

00E4

Timer1 counter register

0 0 0 0 0 0 0 0

page 45

Timer1 input capture register

CDR1

0 0 0 0 0 0 0 0

page 45

Timer1 pulse duty register

T1PDR

R/W

0 0 0 0 0 0 0 0

page 54

00E5

PWM0 high register

PWM0HR

- - - - 0 0 0 0

page 54

00E6

Timer2 mode register

TM2

R/W

- - 0 0 0 0 0 0

page 46

00E7

Timer2 counter register

0 0 0 0 0 0 0 0

page 46

Timer2 data register

TDR2

1 1 1 1 1 1 1 1

page 46

Timer2 input capture register

CDR2

0 0 0 0 0 0 0 0

page 46

00E8

Timer3 mode register

TM3

R/W

0 0 0 0 0 0 0 0

page 46

00E9

Timer3 data register

TDR3

1 1 1 1 1 1 1 1

page 46

PWM1 pulse period register

T3PPR

1 1 1 1 1 1 1 1

page 54

00EA

Timer3 counter register

0 0 0 0 0 0 0 0

page 46

Timer3 input capture register

CDR3

0 0 0 0 0 0 0 0

page 46

Timer3 pulse duty register

T3PDR

R/W

0 0 0 0 0 0 0 0

page 46

00EB

PWM1 high register

PWM1HR

- - - - 0 0 0 0

page 54

00EC

A/D converter mode register

ADCM

R/W

- 0 0 0 0 0 0 1

page 58

00ED

A/D converter data register

ADR

Undefined

page 58

00EF

Watch timer mode register

WTMR

R/W

- 0 - - 0 0 0 0

page 79

00F0

Key scan port mode register

KSMR

R/W

- - - - - - 0 0

page 69

00F1

LCD control register

LCR

R/W

0 0 0 0 0 0 0 0

page 71

00F2

LCD port mode register high

LPMR

R/W

- - 0 0 0 0 0 0

page 71

00F3

RAM paging register

RPR

R/W

- - - - - - 0 0 page 24, page 71

00F4

Basic interval timer register

BITR

0 0 0 0 0 0 0 0

page 43

Clock control register

CKCTLR

- - - 0 0 1 1 1

page 43

00F5

System clock mode register

SCMR

R/W

0 0 0 0 0 0 0 0

page 38

00FB

LVD register

LVDR

R/W

0 0 0 0 0 - - -

page 87

00FD

Buzzer data register

BUR

0 0 0 0 0 0 0 0

page 62

00FE

Serial I/O mode register

SIOM

R/W

0 0 0 0 0 0 0 1

page 59

00FF

Serial I/O Data register

SIOR

R/W

Undefined

page 59

Address

Register Name

Symbol

R/W

Initial Value

Page

7 6 5 4 3 2 1 0

Table 8-1 Control Registers

Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation

Registers are controlled by both bit and byte manipulation instruction.

R/W

instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.

- : this bit location is reserved.

GMS81C7008/7016

APR., 2001 Ver 2.01

8.5 Addressing Mode

The GMS800 series MCU uses six addressing modes;

· Register addressing

· Immediate addressing

· Direct page addressing

· Absolute addressing

· Indexed addressing

· Register-indirect addressing

(1) Register Addressing

(2) Immediate Addressing

#imm

In this mode, second byte (operand) is accessed as a data imme-
diately.

Example:

0435

ADC

#35H

When G-flag is 1, then RAM address is defined by 16-bit address
which is composed of 8-bit RAM paging register (RPR) and 8-bit
immediate data.

Example: G=1, RPR=01

E45535

LDM

35H,#55H

(3) Direct Page Addressing

In this mode, a address is specified within direct page.

Example; G=0

C535

LDA

35H

RAM[35H]

A+35H+C

MEMORY

0F100H

data

55H

data

0135H

0F102H

0F101H

data

35H

0E551H

data

0E550H

GMS81C7008/7016

APR., 2001 Ver 2.01

(4) Absolute Addressing

!abs

Absolute addressing sets corresponding memory data to Data, i.e.
second byte (Operand I) of command becomes lower level ad-
dress and third byte (Operand II) becomes upper level address.
With 3 bytes command, it is possible to access to whole memory
area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR,
SBC, STA, STX, STY

Example;

0735F0

ADC

!0F035H

ROM[0F035H]

The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

regardless of

G-flag.

983501

INC

!0135H

ROM[135H]

(5) Indexed Addressing

X indexed direct page (no offset)

{X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15

, G=1

LDA

{X}

;ACC

RAM[X]

X indexed direct page, auto increment

{X}+

In this mode, a address is specified within direct page by the X
register and the content of X is increased by 1.

LDA, STA

Example; G=0, X=35

LDA

{X}+

X indexed direct page (8 bit offset)

dp+X

This address value is the second byte (Operand) of command plus
the data of

-register. And it assigns the memory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY,
XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5

0F100H

data

0F035H

0F102H

0F101H

A+data+C

address: 0F035

0F100H

data

135H

0F102H

0F101H

data+1

data

address: 0135

data

115H

0E550H

data

35H

data

36H

GMS81C7008/7016

APR., 2001 Ver 2.01

C645

LDA

45H+X

Y indexed direct page (8 bit offset)

dp+Y

This address value is the second byte (Operand) of command plus
the data of Y-register, which assigns Memory in Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute

!abs+Y

Sets the value of 16-bit absolute address plus Y-register data as
Memory.This addressing mode can specify memory in whole ar-
ea.

Example; Y=55

D500FA

LDA

!0FA00H+Y

(6) Indirect Addressing

Direct page indirect

[dp]

Assigns data address to use for accomplishing command which
sets memory data (or pair memory) by Operand.
Also index can be used with Index register X,Y.

JMP, CALL

Example; G=0

3F35

JMP

[35H]

X indexed indirect

[dp+X]

Processes memory data as Data, assigned by 16-bit pair memory
which is determined by pair data [dp+X+1][dp+X] Operand plus
X-register data in Direct page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10

1625

ADC

[25H+X]

Y indexed indirect

[dp]+Y

Processes memory data as Data, assigned by the data [dp+1][dp]
of 16-bit pair memory paired by Operand in Direct page

plus Y-

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, Y=10

data

3AH

0E551H

data

0E550H

45H+0F5H=13AH

0F100H

data

0FA55H

0FA00H+55H=0FA55H

0F102H

0F101H

35H

jump to

0FA00H

36H

0E30AH

address 0E30AH

35H

0E005H

0FA00H

36H

0E005H

data

A + data + C

25 + X(10) = 35H

GMS81C7008/7016

APR., 2001 Ver 2.01

9. I/O PORTS

The GMS81C7008/16 has seven ports (R0, R1, R2, R3, R4, R5
and R6), and LCD segment port SEG0~SEG23, and LCD com-
mon p ort C OM 0~C OM3, wh ich ar e mul ti plex ed wit h
SEG24~SEG26.

These ports pins may be multiplexed with an alternate function
for the peripheral features on the device. In general, in a initial re-
set state, R0,R1,R2, R3 ports are used as a general purpose input
port and R4, R5, R6 and R7 ports are used as LCD segment drive
output port.

9.1 Registers for Port

Port Data Registers

The Port Data Registers in I/O buffer in each seven ports
(R0,R1,R2,R3,R4,R5,R6) are represented as a Type D flip-flop,
which will clock in a value from the internal bus in response to a
"write to data register" signal from the CPU. The Q output of the
flip-flop is placed on the internal bus in response to a "read data
register" signal from the CPU. The level of the port pin itself is
placed on the internal bus in response to "read data register" sig-
nal from the CPU. Some instructions that read a port activating
the "read register" signal, and others activating the "read pin" sig-
nal

Port Direction Registers

All pins have data direction registers which can define these ports
as output or input. A "1" in the port direction register configure
the corresponding port pin as output. Conversely, write "0" to the
corresponding bit to specify it as input pin. For example, to use
the even numbered bit of R0 as output ports and the odd num-
bered bits as input ports, write "55

" to address 0C8

(R0 port

direction register) during initial setting as shown in Figure 9-1.

Figure 9-1 Example of port I/O assignment

All the port direction registers in the MCU have 0 written to them
by reset function. On the other hand, its initial status is input.

Pull-up Control Registers

The R0, R1, R2 and R3 ports have internal pull-up resistors.
Figure 9-2 shows a functional diagram of a typical pull-up port.
It is connected or disconnected by Pull-up Control register
(PURn). The value of that resistor is typically 180k

When a port is used as input, input logic is firmly either low or
high, therefore external pull-down or pull-up resisters are re-
quired practically. The GMS81C7008/16 has internal pull-up, it
can be logic high by pull-up that can be able to configure either
connect or disconnect individually by pull-up control registers
R0PU, R1PU, R2PU and R3PU.

When ports are configured as inputs and pull-up resistor is select-
ed by software, they are pulled to high.

Figure 9-2 Pull-up Port Structure

Open drain port Registers

The R0, R1, R2 and R3 ports have open drain port resistors
R0CR~R3CR.
Figure 9-3 shows a open drain port configuration by control reg-
ister. It is selected as either push-pull port or open-drain port by
R0CR, R1CR, R2CR and R3CR.

Figure 9-3 Open-drain Port Structure

I : INPUT PORT

WRITE "55

" TO PORT R0 DIRECTION REGISTER

R0 DATA

R0 DIRECTION

R1 DATA

R1 DIRECTION

0C0H

0C1H

0C8H

0C9H

BIT

PORT

O : OUTPUT PORT

PULL-UP RESISTOR

PORT PIN

1: Connect

0: Disconnect

Pull-up control bit

VDD

GND

VDD

Typ. 160k

PORT PIN

1: Open drain

0: Push-pull

Open drain port selection bit

GND

GMS81C7008/7016

APR., 2001 Ver 2.01

9.2 I/O Ports Configuration

R0 and R0DD register: R0 is an 8-bit CMOS bidirectional I/O
port (address 0C0

). Each I/O pin can independently used as an

input or an output through the R0DD register (address 0C8

Each port also can be set individually as pull-up port through the
R0PU (address 0D0

), and as open drain register through the

R0CR (address 0D4

In addition, port R0 is multiplexed with various special features.
The control register through the PMR (address 0D9

) and the

SIOM (address 0FE

) control the selection of alternate function.

After reset, this value is "0", port may be used as normal I/O port.
To use alternate function such as external interrupt, event counter
input, serial interface data input, serial interface data output or se-
rial interface clock, write "1" in the corresponding bit of PMR
(address 0D9

) and SIOM (address 0FE

Regardless of the direction register R0DD, the control registers of
PMR and SIOM are selected to use as alternate functions, port pin
can be used as a corresponding alternate features

R1 and R1DD register: R1 is an 2-bit CMOS bidirectional I/O
port (address 0C1

). Each I/O pin can independently used as an

input or an output through the R1DD register (address 0C9

Each port also can be set individually as pull-up port through the
R1PU (address 0D1

), and as open drain register through the

R1CR (address 0D5

Port pin

Alternate function

R00
R01
R02
R03
R04
R05
R06
R07

R0 Data Register

ADDRESS: 0C0

RESET VALUE: 00

R07 R06 R05 R04 R03 R02 R01 R00

Port Direction

R0 Direction Register

R0DD

ADDRESS: 0C8

RESET VALUE: 00

0: Input
1: Output

Input / Output data

Port Mode Register

PMR

ADDRESS: 0D9

RESET VALUE: 00

0: R00
1: INT0

0: R01
1: INT1

0: R02
1: INT2

0: R03
1: EC0

0: R04
1: EC2

0: R30
1: BUZ

0: R31
1: PWM0/T1O

0: R32
1: PWM1/T3O

Edge Detection Register

IEDS

ADDRESS: 0D8

RESET VALUE: 00

INT0

INT1

INT2

External Interrupt Edge Select
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)

R1 Data Register

ADDRESS: 0C1

RESET VALUE: 00

R01 R00

Port Direction

R1 Direction Register

R1DD

ADDRESS: 0C9

RESET VALUE: 00

0: Input
1: Output

Input / Output data

GMS81C7008/7016

APR., 2001 Ver 2.01

R2 and R2DD register: R2 is an 8-bit CMOS bidirectional I/O
port (address 0C2

). Each I/O pin can independently used as an

input or an output through the R2DD register (address 0CA

Each port also can be set individually as pull-up port through the
R2PU (address 0D2

), and as open drain register through the

R2CR (address 0D6

In addition, port R2 is multiplexed with analog input port.

Port pin

Alternate function

R20
R21
R22
R23
R24
R25
R26
R27

AN0 (Analog Input 0)
AN1 (Analog Input 1)
AN2 (Analog Input 2)
AN3 (Analog Input 3)
AN4 (Analog Input 4)
AN5 (Analog Input 5)
AN6 (Analog Input 6)
AN7 (Analog Input 7)

Port Pull-up

R1 Pull-up Register

R1PU

ADDRESS: 0D1

RESET VALUE: 00

0: Pull-up resistor Off
1: Pull-up resistor On

Port Open drain

R1 Open drain control Register

R1CR

ADDRESS: 0D5

RESET VALUE: 00

0: Push Pull
1: Open drain

R2 Data Register

ADDRESS: 0C2

RESET VALUE: 00

R07 R06 R05 R04 R03 R02 R01 R00

Port Direction

R2 Direction Register

R2DD

ADDRESS: 0CA

RESET VALUE: 00

0: Input
1: Output

Input / Output data

Port Pull-up

R2 Pull-up Register

R2PU

ADDRESS: 0D2

RESET VALUE: 00

0: Pull-up resistor Off
1: Pull-up resistor On

Port Open drain

R2 Open drain control Register

R2CR

ADDRESS: 0D6

RESET VALUE: 00

0: Push Pull
1: Open drain

GMS81C7008/7016

APR., 2001 Ver 2.01

R3 and R3DD register: R3 is an 8-bit CMOS bidirectional I/O
port (address 0C3

). Each I/O pin can independently used as an

input or an output through the R3DD register (address 0CB

Each port also can be set individually as pull-up port through the
R3PU (address 0D3

), and as open drain register through the

R3CR (address 0D7

In addition, port R3 is multiplexed with various special features.

Port pin

Alternate function

R30
R31

R32

R33
R34
R35
R36

BUZ (Buzzer driving output)
PWM0 / T1O (PWM 0 output
/ Timer 1 output)
PWM1 /T3O (PWM 1 output
/ Timer 3 output)
-
WDTO (Watchdog timer output)
SX

OUT

(Sub clock output)

(Sub clock input)

R3 Data Register

ADDRESS: 0C3

RESET VALUE: 00

Port Direction

R3 Direction Register

R3DD

ADDRESS: 0CB

RESET VALUE: 00

0: Input
1: Output

Input / Output data

Port Pull-up

R3 Pull-up Register

R3PU

ADDRESS: 0D3

RESET VALUE: 00

0: Pull-up resistor Off
1: Pull-up resistor On

Port Open drain

R3 Open drain control Register

R3CR

ADDRESS: 0D7

RESET VALUE: 00

0: Push Pull
1: Open drain

R06 R05 R04 R03 R02 R01 R00

Port Selection Register

PMR

ADDRESS: 0D9

RESET VALUE: 00

0: R00
1: INT0

0: R01
1: INT1

0: R02
1: INT2

0: R03
1: EC0

0: R04
1: EC2

0: R30

1: BUZ

0: R31
1: PWM0/T1O

0: R32
1: PWM1/T3O

Watch Dog Timer Register

WDTR

ADDRESS: 0DF

RESET VALUE: --01_0010

WDCLR

WDOM

WDCK0

WDCK1

WDEN

WDOE

LCD Control Register

LCR

ADDRESS: 0F1

RESET VALUE: 00

LCK0

LCK1

DTY0

DTY1

BRC

LCDEN

BTC

S U BM

0: R34
1: WDTO

0: SX

OUT

, SX

(Sub Clock Oscillation)

1: R35, R36(Sub Clock Disable)

GMS81C7008/7016

APR., 2001 Ver 2.01

R4 and R4DD register: R4 is an 8-bit CMOS bidirectional I/O
port (address 0C4

). Each I/O pin can independently used as an

input or an output through the R4DD register (address 0CC

A f ter R e s e t , R 4 p o rt i s u s e d a s L C D s e g m e n t o ut p u t
SEG0~SEG7. To use general I/O ports user should be written ap-
propriate value into the LPMR (0F3

R5 and R5DD register: R5 is an 8-bit CMOS bidirectional I/O
port (address 0C5

). Each I/O pin can independently used as an

input or an output through the R4DD register (address 0CD

A f ter R e s e t , R 5 p o rt i s u s e d a s L C D s e g m e n t o ut p u t
SEG8~SEG15. To use general I/O ports user should be written
appropriate value into the LPMR (0F3

R6 and R6DD register: R6 is an 8-bit CMOS bidirectional I/O
port (address 0C6

). Each I/O pin can independently used as an

input or an output through the R6DD register (address 0CE

Af t er Re set, R 6 p or t is u s ed a s LC D s eg m en t outpu t
SEG16~SEG23. To use general I/O ports user should be written
appropriate value into the LPMR (0F3

LCD pin function

Port pin

R40
R41
R42
R43
R44
R45
R46
R47

LCD pin function

Port pin

R50
R51
R52
R53
R54
R55
R56
R57

R4 Data Register

ADDRESS: 0C4

RESET VALUE: 00

R47 R46 R45 R44 R43 R42 R41 R40

Port Direction

R4 Direction Register

R4DD

ADDRESS: 0CC

RESET VALUE: 00

0: Input
1: Output

Input / Output data

LCD pin function

Port pin

R60
R61
R62
R63
R64
R66
R66
R67

R5 Data Register

ADDRESS: 0C5

RESET VALUE: 00

R57 R56 R55 R54 R53 R52 R51 R50

Port Direction

R5 Direction Register

R5DD

ADDRESS: 0CD

RESET VALUE: 00

0: Input
1: Output

Input / Output data

R6 Data Register

ADDRESS: 0C6

RESET VALUE: 00

R67 R66 R65 R64 R63 R62 R61 R60

Port Direction

R6 Direction Register

R6DD

ADDRESS: 0CE

RESET VALUE: 00

0: Input
1: Output

Input / Output data

GMS81C7008/7016

APR., 2001 Ver 2.01

10. CLOCK GENERATOR

As shown in Figure 10-1, the clock generator produces the basic
clock pulses which provide the system clock to be supplied to the
CPU and the peripheral hardware. It contains two oscillators: a
main-frequency clock oscillator and a sub-frequency clock oscil-
lator. Power consumption can be reduced by switching them to
the low power operation frequency clock can be easily obtained
by attaching a resonator between the X

and X

OUT

pin and the

and SX

OUT

pin, respectively. The system clock can also be

obtained from the external oscillator.

The clock generator produces the system clocks forming clock
pulse, which are supplied to the CPU and the peripheral hard-
ware. The internal system clock can be selected by bit2, and bit3
of the System Clock Mode Register(SCMR).

The register is shown in Figure 10-2.

To the peripheral block, the clock among the not-divided original
clocks, divided by 2

, 4,...,

up to 1024 can be provided. Peripheral

clock is enabled or disabled by STOP instruction.

Figure 10-1 Block Diagram of Clock Generator

CPU clock

Instruction cycle time

= 4MHz

= 32.768kHz

0.5 us

61 us

2.0 us

244 us

4.0 us

488 us

16.0 us

1953 us

Internal system clock (CPU clock)

PRESCALER

Peripheral clock

MUX

128

256

512

1024

select clock

SCS[1:0]

OSC Stop

SYCC<1>

SYCC<0>

STOP Mode

SLEEP Mode

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS10

K PUL

(MHz)

PS0

PS3

PS2

PS4

PS1

PS10

PS9

PS5

PS6

PS7

Frequency

period

500K

250K

125K

62.5K

250n

500n

16u

32u

64u

256u

128u

3.906K

7.183K

15.63K

31.25K

PS8

LCR<7>

OSC Stop

RAT

GMS81C7008/7016

APR., 2001 Ver 2.01

11. OPERATION MODE

The system clock controller starts or stops the main-frequency
clock oscillator and switches between the sub frequency clock.
The operating mode is generally divided into the main-clock
mode and the sub-clock mode, which are controlled by System
clock mode register (SCMR). Figure 11-1shows the operating
mode transition diagram.

System clock control is performed by the system clock mode reg-
ister, SCMR. During reset, this register is initialized to "0" so that
the main-clock operating mode is selected.

Main-clock operating mode

This mode is fast-frequency operating mode.
The CPU and the peripheral hardwares are operated on the high-
frequency clock. At reset release, this mode is invoked.

Sub-clock operating mode

This mode is low-frequency operating mode
In this mode, the high-frequency clock oscillation is stops and
low-frequency clock oscillation is active to operate the CPU and
the peripheral hardware on the low-frequency clock, thereby re-
ducing power consumption

SLEEP mode

In this mode, the CPU clock stops while peripherals and the os-
cillation source continue to operate normally.

STOP mode

In this mode, the system operations are all stopped, holding the
internal states valid immediately before the stop at the low power
consumption level.

Figure 11-1 Operating Mode

Main-clock

Mode

STOP

Mode

RESET

Operation

set

Main: According to SCMR
Sub: Oscillating

Main: Stopped
Sub: Oscillating

Main: Oscillating
Sub: Oscillating

SLEEP

Mode

set

str

cti

r t

Main
Sub - Oscillating

- Oscillating

Main
Sub - Oscillating

- According to SCMR

Sub-clock

Mode

Instruction

NOTE1:

RESET
Key Scan Int.
Watch Timer Int.
Timer interrupt (EC0, EC2)
External Int.

NOTE2:

RESET
All Int.

CPU stops,
Peripherals are operate.

CPU and Peripherals are stops,

SIO Int.
Watchdog Timer Int.

GMS81C7008/7016

APR., 2001 Ver 2.01

11.1 Operation Mode Switching

In the Main-clock operation mode, only the high-frequency clock
oscillator is used.

In the Sub-clock operation mode, the high-frequency clock oscil-
lation stops, enabling the low power voltage operation or the low
power consumption operation. Instruction execution does not
stop when the operation speed switching is performed. However,
some peripheral hardware capabilities may be affected. For de-
tails, refer to the description of the relevant operation.

The following describes the switching between the Main-clock
and the Sub-clock operations. During reset, the system clock
mode register is initialized at the Main-clock mode. It must be set
to the Sub-clock operation for the low-power consumption mode.

Switching from main clock operation to sub-
clock operation

First, write "10

" into lower 2 bits of SCMR to switch the main

system clock to the sub-frequency clock.
Next, write "11

" to turn off main frequency oscillation.

Example:

:
:
MOV

SCMR,#0000_XX10B

;

Switch to sub mode

MOV

SCMR,#0000_XX11B

;

Turn off main clock

:
:

Returning from sub clock operation to main
clock operation

First, write "10

" into lower 2 bits of the SCMR to turn on the

main-frequency oscillation, when the stabilization (warm-up) has
been taken by the software delay routine. Sub clock operation
mode can also be released by setting the RESET pin to low,
which immediately performs the reset operation. After reset, the
GMS81C7008/16 is placed in main frequency operation mode.

Example:

:
:
:
MOV

SCMR,#0000_XX10B

;

Turn on main-clock

CALL DELAY

;

Wait until stable

MOV

SCMR,#0000_XX00B

;

Move to main mode

:
:
:

;20ms software delay at fXIN=4MHz

DELAY:

LDY

DLP0:

LDA

DLP1:

NOP
INC

BCC

DLP1

INC

CMPY

#20

BCC

DLP0

RET

Shifting from the Normal operation to the SLEEP
mode

By setting bit 0 of SMR, the CPU clock stops and the SLEEP
mode is invoked. The CPU stops while other peripherals are op-
erate normally.

The way of release from this mode is RESET and all available in-
terrupts.

For more detail, See "20.1 SLEEP Mode" on page 81

Shifting from the Normal operation to the STOP
mode

By executing STOP instruction, the main-frequency clock oscil-
lation stops and the STOP mode is invoked. But sub-frequency
clock oscillation is operated continuously.
After the STOP operation is released by reset, the operation mode
is changed to Main-clock mode.

The methods of release are RESET, Key scan interrupt, Watch
Timer interrupt, Timer/Event counter1 (EC0, EC2 pin), and Ex-
ternal Interrupt.

For more details, see "20.2 STOP Mode" on page 82.

Note: In the STOP and Sub clock operating modes, the
power consumed by the oscillator and the internal hard-
ware is reduced. However, the power for the pin interface
(depending on external circuitry and program) is not directly
associated with the low-power consumption operation. This
must be considered in system design as well as interface
circuit design.

GMS81C7008/7016

APR., 2001 Ver 2.01

12. BASIC INTERVAL TIMER

The GMS81C7008/16 has one 8-bit Basic Interval Timer that is
free-run and can not stop. Block diagram is shown in Figure 12-1.

In addition, the Basic Interval Timer generates the time base for
watchdog timer counting. It also provides a Basic interval timer
interrupt (BITIF). As the count overflow from FF

to 00

, this

overflow causes the interrupt to be generated. The Basic Interval

Timer is controlled by the clock control register (CKCTLR)
shown in Figure 12-2.

Source clock can be selected by lower 3 bits of CKCTLR.

The registers BITR and CKCTLR are located at same address,
and address 0F9

is read as a BITR, and written to CKCTLR.

Figure 12-1 Block Diagram of Basic Interval Timer

Table 12-1 Basic Interval Timer Interrupt Time

MUX

Basic Interval Timer Interrupt

Select Input clock 3

Basic Interval Timer

source
clock

8-bit up-counter

BTS[2:0]

BTCL

1024

512

256

128

To Watchdog timer (WDTCK)

CKCTLR

clear

overflow

Internal bus line

clock control register

[0F4

]

[0F9

]

BITIF

Read

esca

ler

BITR

XIN

SXIN

SCMR[1:0]

BTS[2:0]

CPU Source clock

Interrupt (overflow) Period (ms)

@ f

XIN

= 4MHz

@ f

SXIN

= 32.768kHz

000
001
010
011
100
101
110
111

128

256

512

1024

0.512
1.024
2.048
4.096
8.192

16.384
32.768
65.536

62.5ms

125ms
250ms
500ms

1000ms
2000ms
4000ms
8000ms

GMS81C7008/7016

APR., 2001 Ver 2.01

Figure 12-2 BITR: Basic Interval Timer Mode Register

Example 1:

Interrupt request flag is generated every 8.192ms at 4MHz.

:
LDM

CKCTLR,#0CH

SET1

BITE

EI
:

BTCL

BTS1

Basic Interval Timer source clock select
000: f

XIN

001: f

XIN

010: f

XIN

011: f

XIN

100: f

XIN

128

101: f

XIN

256

110: f

XIN

512

111: f

XIN

1024

Clear bit
0: Normal operation, free-run
1: Clear 8-bit counter (BITR) to "0" and count up again.

INITIAL VALUE: ---0 0111

ADDRESS: 0F4

CKCTLR

INITIAL VALUE: Undefined

ADDRESS: 0F4

BITR

Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.

Caution:

8-BIT FREE-RUN BINARY COUNTER

BTS0

BTS2

BTCL

or f

SXIN

or f

SXIN

or f

SXIN

or f

SXIN

or f

SXIN

128

or f

SXIN

256

or f

SXIN

512

or f

SXIN

1024

BCK

This bit becomes to "0" automatically after one machine cycle.

For the test purpose.
This bit must be cleared to "0" for normal operation,
otherwise BIT clock source is form sub-clock.

GMS81C7008/7016

APR., 2001 Ver 2.01

13. TIMER/EVENT COUNTER

The GMS81C7008/16 has four Timer/Event counters. Each mod-
ule can generate an interrupt to indicate that an event has occurred
(i.e. timer match).

Timer 0 and Timer 1 are can be used either two 8-bit Timer/
Counter or one 16-bit Timer/Counter with combine them. Also
Timer 2 and Timer 3 can be joined as a 16-bit Timer/Counter.

In the "timer" function, the register is increased every internal
clock input. Thus, one can think of it as counting internal clock
input. The count rate is 1/2 to 1/2048 of the oscillator frequency.

In the "counter" function, the register is incremented in response
to a 0-to-1 (rising edge) transition at its corresponding external
input pin, EC0 or EC2 pin.

In addition the "capture" function, the register is incremented in
response external or internal clock sources same with timer or
counter function. When external clock edge input, the count reg-
ister is captured into Capture data register correspondingly.

It has five operating modes: "8-bit timer/counter", "16-bit timer/
counter", "8-bit capture", "16-bit capture", "PWM mode" which
are selected by bit in Timer mode register TMn.

In operation of Timer 2, Timer 3, their operations are same with
Timer 0, Timer 1, respectively.

When programming the software, you may refer to following ex-
ample.

Example 1:

Timer 0 = 8-bit timer mode, 8ms interval at 4MHz
Timer 1 = 8-bit timer mode, 4ms interval at 4MHz
Timer 2 = 16-bit event counter mode

LDM

SCMR,#0

;Main clock mode

LDM

TDR0,#249

LDM

TM0,#0001_0011B

LDM

TDR1,#124

LDM

TM1,#0000_1111B

LDM

TDR2,#1FH

LDM

TDR3,#4CH

LDM

TM2,#0001_1111B

LDM

TM3,#0100_1100B

SET1

T0E

SET1

T2E

EI
:
:

Example 2:

Timer0 = 16-bit timer mode, 0.5s at 4MHz
Timer2 = 2ms 8-bit timer mode at 4MHz
Timer3 = 250us 8-bit timer mode at 4MHz

LDM

SCMR,#0

;Main clock mode

LDM

TDR0,#23H

LDM

TDR1,#0F4H

LDM

TM0,#0FH

;FXIN/32, 8us

LDM

TM1,#4CH

LDM

TDR2,#249

LDM

TDR3,#124

LDM

TM2,#0FH

;FXUN/32, 8us

LDM

TM3,#0DH

;FXIN/8, 2us

SET1

T0E

SET1

T2E

SET1

T3E

EI
:
:

Example 3:

Timer0 = 8-bit timer mode, 2ms interval at 4MHz
Timer1 = 8-bit capture mode, 2us sampling count.

LDM

TDR0,#249

;250x8=2000us

LDM

TM0,#0FH

;FXIN/32, 8us

LDM

IEDS,#XXXX_01XXB ;FALLING

LDM

PMR,#XXXX_XX1XB ;AS INT1

LDM

TDR1,#0FFH

LDM

TM1,#0001_1011B ;2us

SET1

T0E

;ENABLE TIMER 0

SET1

T1E

;ENABLE TIMER 1

SET1

INT1E

;ENABLE EXT. INT1

EI
:
:

X: don't care.

Example 4:

Timer0 = 8-bit timer mode, 2ms interval at 4MHz
Timer2 = 16-bit capture mode, 8us sampling count.

LDM

TDR0,#249

LDM

TM0,#0FH

LDM

IEDS,#XX11_XXXXB

LDM

PMR4,#XXXX_X1XXB

LDM

TDR2,#0FFH ;MAX

LDM

TDR3,#0FFH ;MAX

LDM

TM2,#XX10_1111B ;/32

LDM

TM3,#X10X_11XXB

SET1

T0E

;ENABLE TIMER 0

SET1

T2E

;ENABLE TIMER 2

SET1

INT2E

;ENABLE EXT. INT2

EI
:
:

X: don't care.

GMS81C7008/7016

APR., 2001 Ver 2.01

Figure 13-1 TM0, TM1, TDRn Registers

B TC L

C AP 0

T0C K1

INITIAL VALUE: 00

ADDRESS: 0E0

TM0

T 0C K0 T0C N

T0S T

INITIAL VALUE: 0FF

ADDRESS: 0E1

, 0E3

, 0E7

, 0E9

TDR0~TDR3

Compare data registers

R/W

T0C K2

Timer 0 mode register

Basic Interval Timer source clock select
000: f

XIN

001: f

XIN

010: f

XIN

011: f

XIN

100: f

XIN

128

101: f

XIN

512

110: f

XIN

2048

111: EC0 (External event input 0)

0: Disable count
1: Enable count

0: stop count
1: clearing the T0 counter and start count again

Timer/Counter 0 enable flag

Timer/Counter 0 start/stop control flag

0: Timer mode
1: Capture mode

Capture mode enable

B TC L

PW M E0

T1C K1

INITIAL VALUE: 00

ADDRESS: 0E2

TM1

T1C K0 T1C N

T 1S T

R/W

C A P1

Timer 1 mode register

Timer/Counter 1 source clock select
00: f

XIN

01: f

XIN

10: f

XIN

11: Timer 0 clock

0: Disable count
1: Enable count

0: stop count
1: clearing the T1 counter and start count again

Timer/Counter 1 enable flag

Timer/Counter 1 start/stop control flag

0: Timer mode
1: Capture mode

Capture mode enable

PO L0 16BIT 0

R/W

0: Disable
1: Enable

PWM enable bit

0: Active low
1: Active high

PWM duty control

0: 8-bit mode
1: 16-bit mode

Mode selection

or f

SXIN

or f

SXIN

or f

SXIN

(depend on SCMR)

or f

SXIN

or f

SXIN

or f

SXIN

or f

SXIN

or f

SXIN

128

or f

SXIN

512

or f

SXIN

2048

GMS81C7008/7016

APR., 2001 Ver 2.01

Figure 13-2 TM2, TM3 Registers

B TC L

C AP 2

T2C K1

INITIAL VALUE: 00

ADDRESS: 0E6

TM2

T 2C K0 T 2C N

T2S T

R/W

T2C K2

Timer 2 mode register

Timer/Counter 2 source clock select
000: f

XIN

001: f

XIN

010: f

XIN

011: f

XIN

100: f

XIN

128

101: f

XIN

512

110: f

XIN

2048

111: EC2 (External event input 2)

0: Disable count
1: Enable count

0: stop count
1: clearing the T0 counter and start count again

Timer/Counter 2 enable flag

Timer/Counter 2 start/stop control flag

0: Timer mode
1: Capture mode

Capture mode enable

B TC L

PW M E1

T3C K1

INITIAL VALUE: 00

ADDRESS: 0E8

TM3

T 3C K0 T3C N

T 3S T

R/W

C A P3

Timer 3 mode register

Timer/Counter 3 source clock selection

0: Disable count
1: Enable count

0: stop count
1: clearing the T3 counter and start count again

Timer/Counter 3 enable flag

Timer/Counter 3 start/stop control flag

0: Timer mode
1: Capture mode

Capture mode enable

PO L1 16B IT 1

R/W

0: Disable
1: Enable

PWM enable bit

0: Active low
1: Active high

PWM1 duty control

0: 8-bit mode
1: 16-bit mode

Mode selection

00: f

XIN

01: f

XIN

10: f

XIN

11: Timer 2 clock

or f

SXIN

or f

SXIN

or f

SXIN

(depend on SCMR)

or f

SXIN

or f

SXIN

or f

SXIN

or f

SXIN

or f

SXIN

128

or f

SXIN

512

or f

SXIN

2048

INITIAL VALUE: 00

ADDRESS: 0E1

, 0E4

, 0E7

, 0EA

T0~T3

Count registers

CDR0~CDR3

GMS81C7008/7016

APR., 2001 Ver 2.01

13.1 8-bit Timer / Counter Mode

The GMS81C7008/16 has four 8-bit Timer/Counters, Timer 0,
Timer 1, Timer 2, Timer 3 which are shown in Figure 13-3, Fig-
ure 13-4.

The "timer" or "counter" function is selected by control registers
TMn. To use as an 8-bit timer/counter mode, CAP0, CAP1,

16BIT0 and PWME bits should be cleared to "0". These timers
have each 8-bit count register and data register. The count register
is increased by every internal or external clock input. The internal
clock has a prescaler divide ratio option of 2~2048 selected by
control bits of register TMn (n=0,1,2,3).

Figure 13-3 8-bit Timer/Counter 0, 1

EC0 PIN

MUX

Pres

caler

T0IF

clear

0: Stop
1: Clear and start

000

001

010

TIMER 0
INTERRUPT

MUX

T1IF

clear

0: Stop
1: Clear and start

TIMER 1
INTERRUPT

TDR0 (8-bit)

T1 (8-bit)

TDR1 (8-bit)

T0 (8-bit)

Comparator

TIMER 0

TIMER 1

R31/T1O/PWM0

F/F

BTCL

CAP0

T0CK1

INITIAL VALUE: 00

ADDRESS: 0E0

TM0

T0CK0 T0CN T0ST

T0CK2

X means don't care

PIN

128

512

2048

011

100

101

110

111

BTCL

POL0

PW M E0

T1CK1

INITIAL VALUE: 00

ADDRESS: 0E2

TM1

T1CK0 T1CN T1ST

16BIT0

CAP1

Edge Detector

PMR.6

XIN

SXIN

SCMR[1:0]

T0CN

T0CK[2:0]

T0ST

T1ST

T1CN

T1CK[1:0]

[0D9

.6]

[0E1

]

[0E1

]

[0E4

]

[0E3

]

GMS81C7008/7016

APR., 2001 Ver 2.01

Note: The contents of Timer data register TDRx should be
initialized with 1

~FF

, not to 0

, because it is not to de-

fined before reset.

In the Timer 0, timer register T0 increments from 00

until it

matches with TDR0 and then reset to 00

. The match output of

Timer 0 generates Timer 0 interrupt (latched in T0IF bit)

As TDRx and Tx register are in same address, when reading it as
a Tx, written to TDRx.

In counter function, the counter is increased every 0-to-1 (rising
edge) transition of EC0 or EC2 pin. In order to use counter func-
tion, the bit 3 and bit 4 of the Port mode register PMR are set to
"1" by software. The Timer 0 can be used as a counter by pin EC0
input. Similarly, Timer 2 can be used by pin EC2 input.

Figure 13-4 8-bit Timer/Counter 2, 3

EC2 PIN

MUX

r
esca

ler

T2IF

clear

0: Stop
1: Clear and start

000

001

010

TIMER 2
INTERRUPT

MUX

T3IF

clear

0: Stop
1: Clear and start

TIMER 3
INTERRUPT

TDR2 (8-bit)

T3 (8-bit)

TDR3 (8-bit)

T2 (8-bit)

Comparator

TIMER 2

TIMER 3

R32/T3O/PWM0

F/F

BTCL

CAP2

T2CK1

INITIAL VALUE: 00

ADDRESS: 0E6

TM2

T2CK0 T2CN T2ST

T2CK2

X means don't care

PIN

128

512

2048

011

100

101

110

111

BTCL

POL1

PWME1

T3CK1

INITIAL VALUE: 00

ADDRESS: 0E8

TM3

T3CK0 T3CN T3ST

16BIT1

CAP3

Edge Detector

PMR.7

XIN

SXIN

SCMR[1:0]

T2CN

T2CK[2:0]

T2ST

T3ST

T3CN

T3CK[1:0]

[0D9

.7]

[0E7

]

[0E7

]

[0EA

]

[0E9

]

GMS81C7008/7016

APR., 2001 Ver 2.01

8-bit Timer Mode

In the timer mode, the internal clock is used for counting up.
Thus, you can think of it as counting internal clock input. The
contents of TDRn (n=0,1,2,3) are compared with the contents of
up-counter, Tn (n=0,1,2,3). If match is found, a timer 1 interrupt

(T1IF) is generated and the up-counter is cleared to 0. Counting
up is resumed after the up-counter is cleared.

As the value of TDRn can be re-written by software, time interval
is set as you want

Figure 13-5 Timer Mode Timing Chart

Figure 13-6 Timer Count Example

n-2

n-1

Source clock

Up-counter

TDR1

T1IF interrupt

Start count

Match
Detect

Counter
Clear

Timer 1 (T1IF)
Interrupt

TDR1

TIME

Occur interrupt

Interrupt period

up-

count

Count Pulse

= 8

s x 125

MATCH

Example: Make 1ms

interrupt using by Timer0 at 4MHz

LDM

TM0,#0FH

; divide by 32

LDM

TDR0,#124

; 8us x (124+1)= 1ms

SET1

T0E

; Enable Timer 0 Interrupt

; Enable Master Interrupt

Period

When

TDR0 = 124

= 7C

XIN

= 4 MHz

INTERRUPT PERIOD =

106 Hz

(124+1) = 1 ms

TM0 = 0000_1111

(8-bit Timer mode, Prescaler divide ratio

32)

(TDR0 = T0)

GMS81C7008/7016

APR., 2001 Ver 2.01

8-bit Event Counter Mode

In this mode, counting up is started by an external trigger. This
trigger means rising edge of the EC0 or EC2 pin input. Source
clock is used as an internal clock selected with timer mode regis-
ter TM0, TM1, TM2 or TM3. The contents of timer data register
TDRn (n = 0,1,2,3,........,FF) are compared with the contents of
the up-counter Tn. If a match is found, an timer interrupt request
flag TnIF is generated, and the counter is cleared to "0". The
counter is restart and count up continuously by every rising edge
of the ECn pin input.

The maximum frequency applied to the ECn pin is f

XIN

/2 [Hz].

In order to use event counter function, the bit 3, 4 of the Port
Mode Register PMR (address 0D9

) is required to be set to "1".

After reset, the value of timer data register TDRn is undefined, it
should be initialized to between 1

~FF

not to "0". The interval

period of Timer is calculated as below equation.

Figure 13-7 Event Counter Mode Timing Chart

Figure 13-8 Count Operation of Timer / Event counter

Period (sec)

XIN

----------

Divide Ratio

TDRn

n-1

ECn pin input

Up-counter

TDR1

T1IF interrupt

Start count

Timer 1 (T1IF)
Interrupt

TDR1

TIME

Occur interrupt

stop

clear & start

disable

enable

Start & Stop

T1ST

T1CN
Control count

-c

oun

T1ST = 0

T1ST = 1

T1CN = 0

T1CN = 1

GMS81C7008/7016

APR., 2001 Ver 2.01

13.2 16-bit Timer / Counter Mode

The Timer register is being run with all 16 bits. A 16-bit timer/
counter register T0, T1 are incremented from 0000

until it

matches TDR0, TDR1 and then resets to 0000

. The match out-

put generates Timer 0 interrupt.

The clock source of the Timer 0 is selected either internal or ex-
ternal clock by bit T0SL1, T0SL0.

Even if the Timer 0 (including the Timer 1) is used as a 16-bit
timer, the Timer 2 and Timer 3 can still be used as either two 8-
bit timer or one 16-bit timer by setting the TM2. Reversely, even
if the Timer 2 (including the Timer 3) is used as a 16-bit timer,
the Timer 0 and Timer 1 can still be used as 8-bit timer indepen-
dently.

Figure 13-9 16-bit Timer/Counter

T0IF

clear

0: Stop
1: Clear and start

T0ST

T0CK[2:0]

TIMER 0 INTERRUPT

T0CN

Comparator

TIMER 0 + TIMER 1

TIMER 0 (16-bit)

Higher byte

Lower byte

COMPARE DATA

(16-bit)

(Not Timer 1 interrupt)

INITIAL VALUE: 00

ADDRESS: 0E0

TM0

X means don't care

MUX

esca

l
e

000

001

010

128

512

2048

011

100

101

110

111

Edge Detector

EC0 PIN

TM1

BTCL

POL0

PWME0

T1CK1

INITIAL VALUE: 00

ADDRESS: 0E2

T1CK0 T1CN T1ST

16BIT0

CAP1

BTCL

CAP0

T0CK1 T0CK0 T0CN T0ST

T0CK2

INITIAL VALUE: 00

ADDRESS: 0E6

TM2

TM3

BTCL

POL1

PWME1

T3CK1

INITIAL VALUE: 00

ADDRESS: 0E8

T3CK0 T3CN T3ST

16BIT1

CAP3

BTCL

CAP2

T2CK1 T2CK0 T2CN T2ST

T2CK2

R31/T1O/PWM0

F/F

PIN

PMR.6

TDR0

TDR1

XIN

SXIN

SCMR[1:0]

T2IF

clear

0: Stop
1: Clear and start

T2ST

T2CK[2:0]

TIMER 2 INTERRUPT

T2CN

Comparator

TIMER 0 + TIMER 1

TIMER 0 (16-bit)

Higher byte

Lower byte

COMPARE DATA

(16-bit)

(Not Timer 3 interrupt)

MUX

Pre

scale

000

001

010

128

512

2048

011

100

101

110

111

Edge Detector

EC2 PIN

R32/T3O/PWM1

F/F

PIN

PMR.7

TDR2

TDR3

XIN

SXIN

SCMR[1:0]

[0D9

.6]

[0D9

.7]

X means don't care

GMS81C7008/7016

APR., 2001 Ver 2.01

13.3 8-bit Capture Mode

The capture mode can be used to measure the pulse width be-
tween two edges. The Timer 0 capture mode is set by bit CAP0
of Timer Mode Register TM0, and the Timer 1 capture mode is
set by CAP1 of Timer Mode Register TM1 as shown in Figure
13-10. Timer 2 and Timer 3 have same architecture with Timer 0
and Timer 1.

The Timer/Counter register is incremented in response internal or
external input. This counting function is same with normal timer
mode, and Timer interrupt is generate when timer register T0 (T1,
T2, T3) increase and match TDR0 (TDR1, TDR2, TDR3).

Timer/Counter still does the above, but with the added feature
that a edge transition at external input INTn pin causes the current

Figure 13-10 8-bit Capture Mode (Timer0/Timer1 case)

timer

xin

prescaler value

TDR

(

)

--------------------------------------------------------------------------------

T0CK[2:0]

MUX

000

001

010

128

512

2048

011

100

101

110

111

Edge Detector

EC0 PIN

T0CN

INT0IF

0: Stop
1: Clear and start

INT0
INTERRUPT

CDR0 (8-bit)

T0 (8-bit)

capture

IEDS[1:0]

CDR0 (8-bit)

CDR0

T0IF

TIMER 0
INTERRUPT

Comparator

COMPARE DATA

CDR0 (8-bit)

TDR0 (8-bit)

INT0 PIN

T0ST

clear

T1CK[1:0]

MUX

T1CN

0: Stop
1: Clear and start

CDR0 (8-bit)

T1 (8-bit)

CDR0 (8-bit)

CDR1

T1IF

TIMER 1
INTERRUPT

Comparator

COMPARE DATA

CDR0 (8-bit)

TDR1 (8-bit)

T1ST

clear

INT1IF

INT1
INTERRUPT

capture

IEDS[3:2]

INT1 PIN

clear

INITIAL VALUE: 00

ADDRESS: 0E0

TM0

TM1

BTCL

POL0

PWME0

T1CK1

INITIAL VALUE: 00

ADDRESS: 0E2

T1CK0 T1CN T1ST

16BIT0

CAP1

BTCL

CAP0

T0CK1 T0CK0 T0CN T0ST

T0CK2

Pre

scaler

XIN

SXIN

SCMR[1:0]

R31/T1O/PWM0

F/F

PIN

PMR.6
[0D9

.6]

GMS81C7008/7016

APR., 2001 Ver 2.01

value in the Timer counter register (T0,T1), to be captured and
stored into registers CDRn (CDR0, CDR1), respectively. After
capture, the Timer counter register is cleared and restarts by hard-
ware. At this time, reading the address E1

as a CDR0, not T0.

T0, TDR0, CDR0 are located at same address. The other
CDR1~CDR3 are same. Refer to Timer registers of page 27.

It has three transition modes: "falling edge", "rising edge", "both
edge" which are selected by interrupt edge selection register
IEDS. Refer to "17.4 External Interrupt" on page 68. In addition,
the transition at INTn pin generate an interrupt.

Note: The CDRn and Tn are in same address.In the cap-
ture mode, reading operation is read as CDRn, not Tn be-
cause addressing path is opened to the CDRn.

Figure 13-11 16-bit Capture Mode

13.4 16-bit Capture Mode

16-bit capture mode is the same as 8-bit capture, except that the
Timer register is being run will 16 bits. Configuration is shown in

Figure 13-11.

13.5 Timer output port mode

The GMS81C7008/16 has a function of Timer compare output.
To pulse out, the timer match can goes out to port pin (T1O, T3O)
as shown in Figure 13-3, Figure 13-4 and Figure 13-9.
Thus pulse out is generated by the timer match. These operation
is implemented to pin T1O, T3O. This pin output the signal hav-
ing 50% duty square wave and output frequency is same as below

equation.

To use this function, the bit 6 and bit 7 of Port Mode Register
(PMR) are set or clear properly. In addition, 16-bit Timer output
mode is available, also

T0CK[2:0]

MUX

000

001

010

128

512

2048

011

100

101

110

111

Edge Detector

EC0 PIN

T0CN

INT0IF

0: Stop
1: Clear and start

INT0
INTERRUPT

capture

IEDS[1:0]

T0IF

TIMER 0
INTERRUPT

Comparator

COMPARE DATA

INT0 PIN

T0ST

clear

esca

ler

XIN

SXIN

SCMR[1:0]

R31/T1O/PWM0

F/F

PIN

PMR.6

CDR1

CDR0

TDR1

TDR0

BTCL

CAP0

T0CK1

INITIAL VALUE: 00

ADDRESS: 0E0

TM0

T0CK0 T0CN T0ST

T0CK2

X means don't care

BTCL

POL0

PWME0

T1CK1

INITIAL VALUE: 00

ADDRESS: 0E2

TM1

T1CK0 T1CN T1ST

16BIT0

CAP1

[0D9

.6]

16 BITS

MSB

LSB

GMS81C7008/7016

APR., 2001 Ver 2.01

13.6 PWM Mode

The GMS81C70xx and GMS81C71xx have two high speed
PWM (Pulse Width Modulation) functions which shared with

Timer 1 and Timer 3.

Figure 13-12 PWM Mode

T1CK[1:0]

MUX

T1CN

T1PPR (8-bit)

Comparator

clear

T1ST

TM1

BTCL

POL0

PWME0

T1CK1

INITIAL VALUE: 00

ADDRESS: 0E2

T1CK0 T1CN T1ST

16BIT0

CAP1

esca

ler

XIN

SXIN

SCMR[1:0]

2 Bit

T1 (8-bit)

(note1)

T1PDR (8-bit)

2 Bit

T1PDR (8-bit)

2 Bit

T0 clock source

(from Timer 0)

POL0

R31/T1O/PWM0
PIN

PMR.6

PWM0HR

PWM02

INITIAL VALUE: 00

ADDRESS: 0E5

PWM03

PWM00

PWM01

Duty high

Period high

PWM[01:00]

[0E4

]

[0E5

]

PWM[03:02]

[0E3

]

[0E5

]

[0D9

.6]

2 Bit

Note1: In the PWM mode, 2 bits are added

by hardware automatically.

T3CK[1:0]

MUX

T3CN

T3PPR (8-bit)

Comparator

clear

T3ST

TM3

BTCL

POL1

PWME1

T3CK1

INITIAL VALUE: 00

ADDRESS: 0E8

T3CK0 T3CN T3ST

16BIT1

CAP3

r
esca

ler

XIN

SXIN

SCMR[1:0]

2 Bit

T3 (8-bit)

(note1)

T3PDR (8-bit)

2 Bit

T3PDR (8-bit)

2 Bit

T2 clock source

(from Timer 2)

POL1

R32/T3O/PWM1
PIN

PMR.7

PWM1HR

PWM12

INITIAL VALUE: 00

ADDRESS: 0EB

PWM13

PWM10

PWM11

Duty high

Period high

PWM[11:10]

[0EA

]

[0EB

]

PWM[13:12]

[0E9

]

[0EB

]

[0D9

.7]

2 Bit

GMS81C7008/7016

APR., 2001 Ver 2.01

Note: Whenever change the register content of Period or
Duty of PWM output, the timer counter Tn must be stopped
and restart again by software.

The PWM0 will be explained in this chapter. Other PWM1 has
same architecture. Pin R32/T1O/PWM0 outputs up to a 10-bit
resolution PWM output. This pin should be configure as a PWM
output to set bit PRM0.6 to "1".

The period of the PWM output is determined by the T1PPR
(PWM0 Period Register) and PWM0HR[3:2] and the duty is de-
t e r mi n ed b y t h e T 1 P D R ( P W M 0 D u t y R e g i s t e r ) a n d
PWM0HR[1:0].

The user writes the lower 8-bit period value to the T1PPR and the
higher 2-bit period value to the PWM0HR[3:2].
And writes duty value to the T1PDR and the PWM0HR[1:0]
same way.

The T1PDR is configure as a double buffering for glitchless
PWM output. In, the duty data is transferred from the master to
the slave when the period data matched to the counted value. (i.e.
at the beginning of next duty cycle)

The relation between frequency and resolution is in inverse pro-
portion. Table 13-1 shows the PWM frequency in each clock
source. If it needed higher frequency of PWM, it should be re-
duced resolution.

Figure 13-13 Example of Register setting

The bit POL0 of TM0 decides the polarity of duty cycle.

If the duty value is set same to the period value, the PWM output
is determined by the bit POL0 (1: High, 0: Low). And if the duty
value is set to "00

", the PWM output is determined by the bit

POL0 (1: Low, 0: High).

It can be changed duty value when the PWM output. However the
changed duty value is output after the current period is over. And
it can be maintained the duty value at present output when

changed only period value shown as Figure 13-14. As it were, the
absolute duty time is not changed in varying frequency. But the
changed period value must greater than the duty value.

At PWM output start command, one first pulse would be output
abnormally. Because if user writes register values while timer is
in operation, these register could be set with certain values at first.
To prevent this operation, user must stop PWM timer clock and
then set the duty and the period register values.

256

257

258

3E7

PWM output

Duty; (257

+1) x 500nS = 300uS

Clock source

Period; (3E7

+1) x 500nS = 500uS

T1PPR

PWM0HR

1 1

1 1 1 0 0 1 1 1

T1PDR

1 0

0 1 0 1 0 1 1 1

[0E4

]

[0E3

]

[0E5

]

- - - - 1 1 1 0

Period

Duty

GMS81C7008/7016

APR., 2001 Ver 2.01

Example:

Timer1 = 2kHz, 30% duty PWM mode

LDM

TM1,#00H

LDM

T1PPR,#0E8H

LDM

T1PDR,#58H

LDM

PWM0HR,0000_1110B

LDM

TM1,#1010_1011B

Refer to Figure 13-13.

Figure 13-14 Example of changing the period in absolute duty cycle at 4MHz

Resolutio

PWM clock source

XIN

÷
÷
÷
÷

XIN

÷
÷
÷
÷

XIN

÷
÷
÷
÷

1024

10-bit

3.9kHz

1.95kHz

3.8Hz

9-bit

7.8kHz

3.9kHz

7.6Hz

8-bit

15.6kHz

7.8kHz

15.3Hz

7-bit

31.2kHz

15.6kHz

30.5Hz

Table 13-1 PWM Frequency vs. Resolution at 4MHz

Source

PWM
POL=1

Duty Cycle

Period Cycle [ (D

+1) x 2uS = 28uS, 35.7kHz ]

PWMHR = 00

T1PPR = 0D

T1PDR = 04

T1CK[1:0] = 10 (2uS)

00 01 02

0A 0B 0C 0D 00

05 06

02 03

[ (4+1) x 2uS = 10uS ]

Duty Cycle

[ (4+1) x 2uS =10uS ]

Period Cycle [ (9+1) x 2uS = 20uS, 50kHz ]

Duty Cycle

[ (4+1) x 2uS = 10uS ]

Write "09

" to T1PPR

Period changed

clock

GMS81C7008/7016

APR., 2001 Ver 2.01

14. ANALOG DIGITAL CONVERTER

The analog-to-digital converter (A/D) allows conversion of an
analog input signal to a corresponding 8-bit digital value. The A/
D module has eight analog inputs, which are multiplexed into one
sample and hold. The output of the sample and hold is the input
into the converter, which generates the result via successive ap-
proximation. The analog supply voltage is connected to AV

ladder resistance of A/D module.

The A/D module has two registers which are the control register
ADCM and A/D result register ADR. The register ADCM, shown
in Figure 14-4, controls the operation of the A/D converter mod-
ule. The port pins can be configured as analog inputs or digital I/
O. To use analog inputs, I/O is selected input mode by R2DD di-
rection register.

How to Use A/D Converter

The processing of conversion is start when the start bit ADST is
set to "1". After one cycle, it is cleared by hardware. The register
ADR contains the results of the A/D conversion. When the con-
version is completed, the result is loaded into the ADR, the A/D
conversion status bit ADSF is set to "1", and the A/D interrupt
flag AIF is set. The block diagram of the A/D module is shown in
Figure 14-1. The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conversion is in
process. The conversion time takes maximum 20 uS (at f

XIN

MHz).

Figure 14-1 A/D Block Diagram

A/D Converter Cautions

(1) Input voltage range of AN0 to AN7

The input voltage of AN0 to AN7 should be within the specifica-
tion range. In particular, if a voltage above AV

or below AV

is input (even if within the absolute maximum rating range), the
conversion value for that channel can not be indeterminate. The
conversion values of the other channels may also be affected.

(2) Noise countermeasures

In order to maintain 8-bit resolution, attention must be paid to
noise on pins AV

and AN0 to AN7. Since the effect increases

in proportion to the output impedance of the analog input source,
it is recommended that a capacitor be connected externally as
shown in Figure 14-2 in order to reduce noise.

Figure 14-2 Analog Input Pin Connecting Capacitor

R20/AN0

R21/AN1

R22/AN2

R23/AN3

R24/AN4

R25/AN5

R26/AN6

R27/AN7

S/H

Sample & Hold

"0"

"1"

ADEN

t D

DDER RESIST

ADIF

A/D
INTERRUPT

SUCCESSIVE

APPROXIMATION

CIRCUIT

ADR

A/D result register

ADDRESS: ED

RESET VALUE: Undefined

000

001

010

011

100

101

110

111

ADS[2:0]

AN0~AN7

100~1000pF

Analog
Input

GMS81C7008/7016

APR., 2001 Ver 2.01

(3) AD pin sharing with normal I/O port

The analog input pins AN0 to AN7 also function as input/output
port (PORT R20~R27) pins. When A/D conversion is performed
with any of pins AN0 to AN7 selected, be sure not to execute a
PORT input instruction while conversion is in progress, as this
may reduce the conversion resolution.

Also, if digital pulses are applied to a pin adjacent to the pin in the
process of A/D conversion, the expected A/D conversion value
may not be obtainable due to coupling noise. Therefore, avoid ap-
plying pulses to pins adjacent to the pin undergoing A/D conver-
sion.

(4) AV

pin input impedance

A series resistor string of approximately 10k

is connected be-

tween the AV

pin and the AV

pin.

Therefore, if the output impedance of the reference voltage
source is high, this will result in parallel connection to the series
resistor string between the AV

pin and the AV

pin, and there

will be a large reference voltage error.

Figure 14-3 A/D converter Operation Flow

Figure 14-4 A/D Converter Control Register

ENABLE A/D CONVERTER

A/D START ( ADST = 1 )

NOP

ADSF = 1

A/D INPUT CHANNEL SELECT

ANALOG REFERENCE SELECT

READ ADR

YES

BTCL

ADEN

ADST

A/D status bit

Analog input channel select

INITIAL VALUE: -0-0 0001

ADDRESS: 0EC

ADCM

ADSF

A/D converter Enable bit

0: A/D converter module turn off and

current is not flow.

1: Enable A/D converter

R/W

000: Channel 0 (AN0)
001: Channel 1 (AN1)
010: Channel 2 (AN2)
011: Channel 3 (AN3)
100: Channel 4 (AN4)
101: Channel 5 (AN5)
110: Channel 6 (AN6)
111: Channel 7 (AN7)

0: A/D conversion is in progress
1: A/D conversion is completed

A/D start bit

Setting this bit starts an A/D conversion.

After one cycle, bit is cleared to "0" by hardware.

ADS1 ADS0

ADS2

INITIAL VALUE: Undefined

ADDRESS: 0ED

ADR

A/D Conversion Data

BTCL

0: -
1: A/D start

GMS81C7008/7016

APR., 2001 Ver 2.01

15. SERIAL COMMUNICATION

The serial interface is used to transmit/receive 8-bit data serially.
Serial communication block consists of serial I/O data register,
serial I/O mode register, clock selection circuit, octal counter and
control circuit as illustrated in Figure 15-1.Pin R07/SIN, R06/
SOUT and R05/SCLK pins are controlled by the Serial Mode
Register. The contents of the Serial I/O data register can be writ-
ten into or read out by software.

The serial communication is activated by the instruction "SET1

SIOST". The octal counter is reset to "0" by this instruction, starts
counting at the falling or rising edge (by POL selection) of the
transmit clock (SCLK), and it increments at the every clock. A se-
rial interrupt request flag is set when the eighth transmit clock
signal is input (the serial interface is reset) or when serial commu-
nication is discontinued (the octal counter is reset).

The data in the Serial Data Register can be shifted synchronously
with the transfer clock signal.

Figure 15-1 SCI Control Register

SCK1

SCK0

SCLK/R05 Port

Clock Source

Prescaler Divide Ratio

SCLK output

Internal clock

SCLK output

Internal clock

SCLK output

Internal clock

Use clock from Timer 0 overflow

SCLK input

External clock

BTCL

MSB

POL

SIOST

Serial transmission status bit

Serial transmission Clock selection

INITIAL VALUE: 0000_0001

ADDRESS: 0FE

SIOM

SIOSF

MSB first or LSB first

0: LSB First
1: MSB First

R/W

00: f

XIN

01: f

XIN

10: Timer 0 Overflow
11: External Clock

0: Serial transmission is in progress
1: Serial transmission is completed

Serial transmission start bit
Setting this bit starts an Serial transmission.
After one cycle, bit is cleared to "0" by hardware.

SCK1 SCK0

SIO1

SIO0

R/W

Serial transmission Operation Mode
00: Normal Port(R05,R06,R07)
01: Sending Mode(SCLK,SOUT,R07)
10: Receiving Mode(SCLK,R06,SIN)
11: Sending & Receiving Mode(SCLK,SOUT,SIN)

INITIAL VALUE: Undefined

ADDRESS: 0FF

SIOR

BTCL

R/W R/W R/W R/W

R/W R/W

R/W

Sending Data during Sending Mode
Receiving Data during Receiving Mode

Selection Polarity

0: Data in on rising edge, data out on falling edge
1: Data in on falling edge, data out on rising edge

R/W

GMS81C7008/7016

APR., 2001 Ver 2.01

Serial I/O Mode Register(SIOM) controls serial I/O function.

The POL bit control which edge

According to SCK1 and SCK0, the internal clock or external
clock can be selected.

Serial I/O Data Register(SIOR) is an 8-bit shift register.

Figure 15-2 Block Diagram of SCI

15.1 Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 of
SIOM) to "1". After one cycle of SCK, SIOST is cleared
automatically to "0". The serial output data from 8-bit shift
register is output at falling edge of SCLK. And input data

is latched at rising edge of SCLK pin. When transmission
clock is counted 8 times, serial I/O counter is cleared as
`0". Transmission clock is halted in "H" state and serial I/
O interrupt(SIOIF) occurred.

Figure 15-3 SPI Timing Diagram at POL=0

R05/SCLK PIN

CONTROL CIRCUIT

R06/SOUT PIN

Serial IO Data

Octal Counter

Serial communication
Interrupt

SIOIF

R07/SIN PIN

SCK, SIO

overflow

SCK[1:0]

MUX

esca

ler

XIN

SXIN

SCMR[1:0]

T0OV

(Timer 0 overflow)

POL

SIOST

start

SIOSF

complete

clock

clear

SIO1

SIO0

[0FF

]

Edge Detector

SIO[1:0]

shift clock

SCLK OUT

D 1

D 2

D 3

D 4

D 6

D 7

D 0

D 5

SIOST

SCLK [R05]

(POL=0)

SOUT [R06]

SIN [R07]

SIOIF

(Interrupt Req.)

SIOSF

GMS81C7008/7016

APR., 2001 Ver 2.01

15.2 The method of Serial I/O

1. Select transmission/receiving mode

When external clock is used, the frequency should be less than
1MHz and recommended duty is 50%.

2. In case of sending mode, write data to be send to SIOR.

3. Set SIOST to "1" to start serial transmission.

If both transmission mode is selected and transmission is per-

formed simultaneously it would be made error.

4. The SIO interrupt is generated at the completion of SIO and
SIOSF is set to "1". In SIO interrupt service routine, correct trans-
mission should be tested.

5. In case of receiving mode, the received data is acquired by
reading the SIOR.

Figure 15-4 SPI Timing Diagram at POL=1

15.3 The Method to Test Correct Transmission

Figure 15-5 Serial Method to Test Transmission

D 1

D 2

D 3

D 4

D 6

D 7

D 0

D 5

SIOST

SCLK [R05]

(POL=1)

SOUT [R06]

SIN [R07]

SCIIF

SIOSF

Serial I/O Interrupt
Service Routine

SE = 0

Write SIOM

Normal Operation

Overrun Error

Abnormal

SIOSF

- SE : Interrupt Enable Register Low IENL(Bit3)

- SR : Interrupt Request Flag Register Low IRQL(Bit3)

GMS81C7008/7016

APR., 2001 Ver 2.01

16. BUZZER FUNCTION

The buzzer driver block consists of 6-bit binary counter, buzzer
register, and clock source selector. It generates square-wave
which has very wide range frequency (500Hz ~ 250kHz at f

XIN

4MHz) by user software.

A 50% duty pulse can be output to R30/BUZ pin to use for piezo-
electric buzzer drive. Pin R30 is assigned for output port of Buzz-
er driver by setting the bit 5 of PMR (address D9

) to "1". At this

time, the pin R30 must be defined as output mode (the bit 0 of
R3DD=1).

Example: 2.4kHz output at 4MHz.

LDM

R3DD,#XXXX_XXX1B

LDM

BUR,#0111_0011B

SET1

PMR.5

;BUZ ON

CLR1

PMR.5

;BUZ OFF

X means don't care

The bit 0 to 5 of BUR determines output frequency for buzzer
driving.

Equation of frequency calculation is shown below.

BUZ

: Buzzer frequency

XIN

: Oscillator frequency

Divide Ratio: Prescaler divide ratio by BUCK[1:0]

BUR: Lower 6-bit value of BUR. Buzzer period value.

The frequency of output signal is controlled by the buzzer control
register BUR.The BUR[5:0] determine output frequency for
buzzer driving.

Figure 16-1 Block Diagram of Buzzer Driver

Figure 16-2 PMR and Buzzer Register

BUZ

XIN

DivideRatio

BUR 5:0

[

]

(

)

----------------------------------------------------------------------------------------

r
esca

ler

R30/BUZ PIN

PMR.5

R30 port data

F/F

Comparator

6-bit Compare Data

6-bit Binary Counter

MUX

BUR[5:0]

[0FD

]

BUR[7:6]

XIN

SXIN

SCMR[1:0]

BUR[5:0]

BUR

ADDRESS: 0FD

RESET VALUE: Undefined

Source clock select

00:

01:

10:

11:

Define Frequency of Buzzer signal

BUCK1 BUCK0

R30/BUZ Selection

PMR

ADDRESS: 0D9

RESET VALUE: 00

R/W R/W R/W R/W R/W R/W

0: R30 port (Turn off buzzer)

R/W R/W

PWM1

BUZ

PWM0

INT0

INT1

INT2

EC0

EC2

1: BUZ port (Turn on buzzer)

GMS81C7008/7016

APR., 2001 Ver 2.01

Note that BUR is a write-only register.

The 6-bit counter is cleared and starts the counting by writing sig-
nal at BUR register. It is incremental from 00

until it matches 6-

bit BUR value.

When main-frequency is 4MHz, buzzer frequency is shown as
below table. The unit is kHz.

BUR
[5:0]

BUCK[1:0]

BUR
[5:0]

BUCK[1:0]

00
01
02
03
04
05
06
07

250.000
125.000

83.333
62.500
50.000
41.667
35.714
31.250

125.000

62.500
41.667
31.250
25.000
20.833
17.857
15.625

62.500
31.250
20.833
15.625
12.500
10.417

8.929
7.813

31.250
15.625
10.417

7.813
6.250
5.208
4.464
3.906

20
21
22
23
24
25
26
27

7.576
7.353
7.143
6.944
6.757
6.579
6.410
6.250

3.788
3.676
3.571
3.472
3.378
3.289
3.205
3.125

1.894
1.838
1.786
1.736
1.689
1.645
1.603
1.563

0.947
0.919
0.893
0.868
0.845
0.822
0.801
0.781

08
09

0A
0B
0C
0D
0E
0F

27.778
25.000
22.727
20.833
19.231
17.857
16.667
15.625

13.889
12.500
11.364
10.417

9.615
8.929
8.333
7.813

6.944
6.250
5.682
5.208
4.808
4.464
4.167
3.906

3.472

3.125
2.841
2.604
2.404
2.232
2.083
1.953

28
29

2A
2B
2C
2D
2E
2F

6.098
5.952
5.814
5.682
5.556
5.435
5.319
5.208

3.049
2.976
2.907
2.841
2.778
2.717
2.660

2.604

1.524
1.488
1.453
1.420
1.389
1.359
1.330
1.302

0.762
0.744
0.727
0.710
0.694
0.679
0.665
0.651

10
11
12
13
14
15
16
17

14.706
13.889
13.158
12.500
11.905
11.364
10.870
10.417

7.353
6.944
6.579
6.250
5.952
5.682
5.435
5.208

3.676
3.472
3.289
3.125
2.976
2.841
2.717
2.604

1.838
1.736
1.645
1.563
1.488
1.420
1.359
1.302

30
31
32
33
34
35
36
37

5.102
5.000
4.902
4.808
4.717
4.630
4.545

4.464

2.551
2.500
2.451
2.404
2.358
2.315
2.273
2.232

1.276
1.250
1.225
1.202
1.179
1.157
1.136
1.116

0.638
0.625
0.613
0.601
0.590
0.579
0.568
0.558

18
19

1A
1B
1C
1D
1E
1F

10.000

9.615
9.259
8.929
8.621
8.333
8.065
7.813

5.000
4.808
4.630
4.464
4.310
4.167
4.032
3.906

2.500
2.404
2.315
2.232
2.155
2.083
2.016
1.953

1.250
1.202
1.157
1.116
1.078
1.042
1.008
0.977

38
39

3A
3B
3C
3D
3E
3F

4.386
4.310
4.237
4.167
4.098
4.032
3.968
3.906

2.193
2.155
2.119
2.083
2.049
2.016
1.984
1.953

1.096
1.078
1.059
1.042
1.025
1.008
0.992
0.977

0.548
0.539
0.530
0.521
0.512
0.504
0.496
0.488

Table 16-1 Buzzer Frequency at 4MHz

GMS81C7008/7016

APR., 2001 Ver 2.01

17. INTERRUPTS

The GMS81C7008/16 interrupt circuits consist of Interrupt en-
able register (IENH, IENL), Interrupt request flags of IRQH,
IRQL, Priority circuit, and Master enable flag ("I" flag of PSW).
Thirteen interrupt sources are provided. The configuration of in-
terrupt circuit is shown in Figure 17-2.

The keyscan interrupt is generated when 1-to-0 transition is de-
tected at KS0 or KS0 pin.

The Basic Interval Timer Interrupt is generated by BITIF which
is set by an overflow in the timer register.

The Watchdog timer Interrupt is generated by WDTIF which set
by a match in Watchdog timer register.

The External Interrupts INT0 ~ INT2 each can be transition-acti-
vated (1-to-0 or 0-to-1 transition) by selection IEDS.
The flags that actually generate these interrupts are bit INT0IF,
INT1IF and INT2IF in register IRQH and IRQL. When an exter-
nal interrupt is generated, the flag that generated it is cleared by
the hardware when the service routine is vectored to only if the
interrupt was transition-activated.

The Timer 0 ~ Timer 3 Interrupts are generated by T0IF~T3IF
which are set by a match in their respective timer/counter register.

The Serial Communication Interrupts are generated by SIOIF
which is set by 8-bit serial data transmitting or receiving through
SCK, SIN, SOUT pin.

The AD converter Interrupt is generated by ADIF which is set by
finishing the analog to digital conversion.

The Watch Timer Interrupt is generated by WTIF which is set by
an 14-bit binary counter overflow.

The interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW on page 19), the interrupt enable register
(IENH, IENL), and the interrupt request flags (in IRQH and
IRQL) except Power-on reset and software BRK interrupt. Below
table shows the Interrupt priority.

Vector addresses are shown in Figure 8-6 on page 21. Interrupt
enable registers are shown in Figure 17-3. These registers are
composed of interrupt enable flags of each interrupt source and
these flags determines whether an interrupt will be accepted or
not. When enable flag is "0", a corresponding interrupt source is
prohibited. Note that PSW contains also a master enable bit, I-
flag, which disables all interrupts at once.

Figure 17-1 Interrupt Request Flag

Reset/Interrupt

Symbol

Priority

Hardware Reset
Key scan Interrupt
Basic Interval Timer
Watchdog Timer
External Interrupt 0
External Interrupt 1
Timer/Counter 0
Timer/Counter 1
External Interrupt 2
Serial Communication
ADC Interrupt
Watch Timer Interrupt
Timer/Counter 2
Timer/Counter 3

RESET

BIT

WDT

INT0
INT1

Timer 0
Timer 1

INT2

SCI

ADC

Timer 2
Timer 3

1
2
3
4
5
6
7
8
9

10
11
12
13

WDTIF

R/W

Timer/Counter 3

INITIAL VALUE: -000 0000

ADDRESS: 0DD

IRQH

KSIF

MSB

LSB

T0IF

T1IF

INT0IF INT1IF

BITIF

R/W

Timer/Counter 2

Timer/Counter 1 interrupt request flag

External interrupt 1

Serial Communication

INITIAL VALUE: 0--0 0000

ADDRESS: 0DC

IRQL

MSB

LSB

Timer/Counter 0

R/W

Basic Interval Timer

Watchdog timer

A/D Converter

External interrupt 0

Key scan

SIOIF

INT2IF

T2IF

T3IF

ADIF

WTIF

R/W

Watch timer

External interrupt 2

GMS81C7008/7016

APR., 2001 Ver 2.01

Figure 17-2 Block Diagram of Interrupt

Figure 17-3 Interrupt Enable Flag

INT1

INT0

INT2

INT2IF

IENL

Interrupt Enable

IRQL [0DC

]

IRQH [0DD

]

Interrupt

Vector

Address

Generator

Internal bus line

Release STOP

To CPU

Interrupt Master
Enable Flag

I-flag

IENH

r
io

r
i
ty Co

t
r
o

I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.

[0DA

]

[0DB

]

INT0IF

INT1IF

T3IF

T2IF

Timer 3

Timer 2

A/D Converter

ADIF

SIOIF

BITIF

Watchdog Timer

Serial

BIT

WDTIF

Communication

Watch Timer

WTIF

Key Scan

KSIF

T1IF

T0IF

Timer 1

Timer 0

SIOE

INT2E

Timer/Counter 3 interrupt enable flag

INITIAL VALUE: 0--0 0000

ADDRESS: 0DA

IENL

MSB

LSB

T2E

T3E

ADE

WTE

R/W

Timer/Counter 2 interrupt enable flag

Watch Timer interrupt enable flag

Serial Communication interrupt enable flag

INITIAL VALUE: -000 0000

ADDRESS: 0DB

IENH

MSB

LSB

R/W

Basic Interval Timer interrupt enable flag

Watchdog timer interrupt enable flag

A/D Converter interrupt enable flag

External interrupt 2 enable flag

0: Disable
1: Enable

VALUE

WDTE

R/W

KSE

T0E

T1E

INT0E

INT1E

BITE

R/W

Timer/Counter 1 interrupt enable flag
Timer/Counter 0 interrupt enable flag

External interrupt 1 enable flag

External interrupt 0 enable flag

Key scan interrupt enable flag

GMS81C7008/7016

APR., 2001 Ver 2.01

17.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the
interrupt latch is cleared to "0" by a reset or an instruction. Inter-
r u p t a c c e p t a n c e s e q u e n c e r e q u i r e s 8

X I N

( 2

s a t

MAIN

=4.19MHz) after the completion of the current instruction

execution. The interrupt service task is terminated upon execu-
tion of an interrupt return instruction [RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

"0" to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following
interrupts is temporarily disabled.

2. Interrupt request flag for the interrupt source accepted is

cleared to "0".

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is

read from the vector table address and the entry address
is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

Figure 17-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

A interrupt request is not accepted until the I-flag is set to "1"
even if a requested interrupt has higher priority than that of the
current interrupt being serviced.

When nested interrupt service is required, the I-flag should be set
to "1" by "EI" instruction in the interrupt service program. In this
case, acceptable interrupt sources are selectively enabled by the
individual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program counter and
the program status word are automatically saved on the stack, but
accumulator and other registers are not saved itself. These regis-
ters are saved by the software if necessary. Also, when multiple
interrupt services are nested, it is necessary to avoid using the
same data memory area for saving registers.

The following method is used to save/restore the general-purpose
registers.

V.L.

System clock

Address Bus

SP-1

SP-2

V.H.

New PC

V.L.

Data Bus

Not used

PCH

PCL

PSW

ADL

OP code

ADH

Instruction Fetch

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.

Watch Timer

012

0E3

0FFE4

0FFE5

0E312

0E313

Entry Address

Correspondence between vector table address for Watch Timer Interrupt
and the entry address of the interrupt service program.

Vector Table Address

GMS81C7008/7016

APR., 2001 Ver 2.01

Example: Register save using push and pop instructions

General-purpose register save/restore using push and pop instruc-
tions;

17.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.

Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK inter-
rupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.

Each processing step is determined by B-flag as shown in Figure
17-5.

Figure 17-5 Execution of BRK/TCALL0

17.3 Multi Interrupt

If two requests of different priority levels are received simulta-
neously, the request of higher priority level is serviced. If re-
qu est s of th e int errup t are received at t he same t ime
simultaneously, an internal polling sequence determines by hard-
ware which request is serviced.

However, multiple processing through software for special fea-
tures is possible. Generally when an interrupt is accepted, the I-
flag is cleared to disable any further interrupt. But as user sets I-
flag in interrupt routine, some further interrupt can be serviced
even if certain interrupt is in progress.

Example: During Timer1 interrupt is in progress, INT0 interrupt
serviced without any suspend.

TIMER1:

PUSH

LDM

IENH,#08H

;

Enable INT0 only

LDM

IENL,#00H

;

Disable other

;

Enable Interrupt

:
:

:
:
LDM

IENH,#0FFH

;

Enable all interrupts

LDM

IENL,#0FFH

POP

RETI

Figure 17-6 Execution of Multi Interrupt

INTxx:

PUSH

;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.

interrupt processing

POP

RETI

;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN

main task

interrupt
service task

saving
registers

restoring
registers

acceptance of

interrupt

interrupt return

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

TCALL0

ROUTINE

RET

BRK or

TCALL0

enable INT0

TIMER 1
service

INT0
service

Main Program
service

Occur
TIMER1 interrupt

Occur
INT0

disable other

enable INT0
enable other

In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.

GMS81C7008/7016

APR., 2001 Ver 2.01

17.4 External Interrupt

The external interrupt on INT0, INT1 and INT3 pins are edge
triggered depending on the edge selection register IEDS (address
0D8

) as shown in Figure 17-7.

The edge detection of external interrupt has three transition acti-
vated mode: rising edge, falling edge, and both edge.

Figure 17-7 External Interrupt Block Diagram

INT0 ~ INT2 are multiplexed with general I/O ports (R00~R02).
To use as an external interrupt pin, the bit of Port Mode Register
PMR should be set to "1" correspondingly as shown in Figure 17-
9.

Example: To use as an INT0 and INT2

:
:

;

**** Set port as an input port R00,R02

LDM

R0DD,#1111_1010B

;

**** Set port as an external interrupt port

LDM

PMR,#05H

;

**** Set Falling-edge Detection

LDM

IEDS,#0001_0001B

:
:

Response Time

The INT0 ~ INT2 edge are latched into INT1IF ~ INT2IF at every
machine cycle. The values are not actually polled by the circuitry
until the next machine cycle. If a request is active and conditions
are right for it to be acknowledged, a hardware subroutine call to
the requested service routine will be the next instruction to be ex-
ecuted. The DIV itself takes twelve cycles. Thus, a minimum of
twelve complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution of the
first instruction of the service routine.

Figure 17-8 shows interrupt response timings.

Figure 17-8 Interrupt Response Timing Diagram

17.5 Key Scan Interrupt

GMS81C7008/16 has the key-scan block which consists of
Port selection Multiplexer, Interrupt controller, Key scan
mode register and Falling edge detector shown as Figure
17-10.

When the key scan interrupt is used, key scan register
KSMR (address 0F0

) should be set to "1" as KS0 and

KS1. After reset, initial setting is general R10 and R00
ports.

If key scan is detected at any one or more of these pins, the
KSIF request flag is set to "1". This generates an interrupt
request. It also can be used in the way of release from
STOP mode.

INT0IF

INT0 pin

INT0 INTERRUPT

INT1IF

INT1 pin

INT1 INTERRUPT

INT2IF

INT2 pin

INT2 INTERRUPT

IEDS

[0D8

]

Edge selection
Register

Interrupt
goes
active

Interrupt
latched

Interrupt
processing

Interrupt
routine

8 f

XIN

period

max. 12 f

XIN

period

GMS81C7008/7016

APR., 2001 Ver 2.01

Figure 17-9 PMR and IEDS Registers

Figure 17-10 Key Scan Port Block Diagram

BTCL

BUZ

PWM0

PWM1

INT1S

0: R00
1: INT0

INITIAL VALUE: 00

ADDRESS: 0D9

PMR

EC2S

INT0S

INT2S

EC0S

0: R01
1: INT1

0: R02
1: INT2

0: R03
1: EC0

0: R32
1: PWM1/T3O

0: R31
1: PWM0/T1O

0: R30

1: BUZ

0: R04
1: EC2

LSB

MSB

BTCL

R/W

IED2H

IED0H

INITIAL VALUE: 00

ADDRESS: 0D8

IEDS

IED2L

IED0L

IED1L

IED1H

LSB

MSB

Edge selection register
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)

INT0

INT1

INT2

R/W

Key Scan Interrupt

R10/KS0

R11/KS1

KSIF

KSMR

[0F0

]

R1PU[1:0]

Key Scan Mode Register

KSMR

ADDRESS: 0F0

RESET VALUE: 00

KS1 KS0

Port selection
0: R10
1: KS0

Port selection
0: R11
1: KS1

Reserved

Edge detector

Pull up Resistor
Typ. 160k

GMS81C7008/7016

APR., 2001 Ver 2.01

18. LCD DRIVER

The GMS81C7008/16 has the circuit that directly drives the liq-
uid crystal display (LCD) and its control circuit. In addition,
VCLn pin is provided as the drive power pin.

Basically, the GMS81C7008/16 has 24 seg.

4 com. ports of

LCD driver. Extend display modes are shown in left table.

Figure 18-1shows the configuration of the LCD driver.

********Caution********

When you developing the software using by
Emulator, you must select the External bias re-
sistor mode because of no internal bias resistor
inside the Emulator (EVA. chip).

Figure 18-1 LCD Driver Block Diagram

18.1 LCD Control Registers

The LCD driver is controlled by the LCD control register LCR

which is shown in Figure 18-2. LCD block input the clock from

GMS81C7008/16

1/4 duty:

24 seg

×
×
×
×

4com

1/3 duty:

25 seg

×
×
×
×

3com

1/2 duty:

26 seg

×
×
×
×

2com

Static:

27 seg

×
×
×
×

1com

SEG0/R40

Disp

l
a

ct C

t
r
o

i
s

reg

i
ster

r
S

Display Memory

t Dr

ive

(27

4 bits)

128

256

i
ng

t
ro

SEG7/R47

LPMR[1:0]

LPMR[3:2]

SEG8/R50

SEG15/R57

LPMR[5:4]

SEG16/R60

SEG23/R67

Select
SEG or Normal port

[0F1

]

LCR

INT

RNA

BUS L

I
NE

Enable LCD

Control bias voltage and resistor

by LPMR [0F2

]

MUX

"Same with above"

WTCK[1:0]

M U X

SUB

MAIN

Pre

scale

COM0

COM1/SEG26

COM2/SEG25

COM3/SEG24

LCR[3:2] of address 0F1

.
o

r
SEG

r
& Bia

t
r
o

BIAS

VCL2

VCL1

VCL0

Control frame frequency

GMS81C7008/7016

APR., 2001 Ver 2.01

the Watch Timer. When LCD is operate, the Watch Timer much

be enabled by WTEN (bit 6 of address 0EF

Figure 18-2 LCD Control Register

Selection frame frequency
00: 1024Hz
01: 512Hz
10: 256Hz
11: 128Hz

INITIAL VALUE: 00

ADDRESS: 0F1

LCR

R/W

Duty control
00: 1/4 duty
01: 1/3 duty (SEG24 active)

Bias resistor control
0: External
1: Internal

LCD display control
0: LCD display all segment 0 data output
1: LCD display enable

R/W

Bias transistor control
0: off
1: on

BTC

SUBM

LCDEN BRC

LCK1 LCK0

R/W

10: 1/2 duty (SEG24, SEG25 active)
11: Static (SEG24, SEG25, SEG26 active)

Sub clock port mode
0: SXIN, SXOUT
1: R35, R36

DTY0

DTY1

R4 port selection
00:SEG0~SEG7
01:SEG4~SEG7,R40~R43
10:SEG0~SEG3,R44~R47
11:R40~R47

INITIAL VALUE:0000 0000

ADDRESS: 0F2

LPMR

R/W

R5LPMR

R4LPMR

R5 port selection
00:SEG8~SEG15
01:SEG12~SEG15,R50~R53
10:SEG8~SEG11,R54~R57
11:R50~R57

R6LPMR

R6 port selection
00:SEG16~SEG23
01:SEG20~SEG23,R60~R63
10:SEG16~SEG19,R64~R67
11:R60~R67

R/W

INITIAL VALUE: 00

ADDRESS: 0F3

RPR

R/W

RPR1 RPR0

The RPR register is used for RAM page selection.

RAM page

Instruction

PRP1

PRR0

Page 0

CLRG

Page 0

SETG

Page 1

SETG

Reserved

SETG

Reserved

SETG

When

SXIN

= 32.768kHz

XIN

= 4.19MHz

No internal bias registers in the Emulator,
so user must select the "0", External mode at least
during use the Emulator.
OTP and Mask MCU can use both.

GMS81C7008/7016

APR., 2001 Ver 2.01

18.2 Duty and Bias Selection of LCD driver

5 kinds of driving methods can be selected by DTY (bits 3 and 2
of LCD Control Register and connection of VCL pin externally.

Figure 18-3 shows typical driving waveforms for LCD.).

Figure 18-3 LCD drive waveform (Voltage COM-SEG Pins)

18.3 Selecting Frame Frequency

Frame frequency is set to the base frequency as shown in the fol-
lowing Table 18-1.

The LCK[1:0] of LCR determines the frequency of COM signal
scanning of each segment output. The watch timer must be en-
abled when the LCD display is turned on. RESET clears the LCD
control register LCR values to logic zero. The LCD display can
continue to operate even during the SLEEP and STOP modes if a
sub-frequency clock is oscillate and used as clock source of LCD
driver.

VCL2
VCL1
VCL0

GND

-VCL0
-VCL1
-VCL2

1/f

Data "1"

(a) 1/4 duty, 1/3 bias

Data "0"

VCL2
VCL1
VCL0

GND

-VCL0
-VCL1
-VCL2

1/f

Data "1"

(b) 1/3 duty, 1/3 bias

Data "0"

1/f

Data "1" Data "0"

(c) 1/2 duty,1/3 bias

1/f

Data "1"

Data "0"

VCL2
VCL1
VCL0

GND

-VCL0
-VCL1
-VCL2

(e) Static

Note: f

: LCD Frame Frequency

1/f

Data "1" Data "0"

VCL2

GND

-VCL0 = -VCL1

-VCL2

(d) 1/2 duty, 1/2 bias

VCL1 = VCL0

VCL2
VCL1
VCL0

GND

-VCL0
-VCL1
-VCL2

LCK[1:0]

LCD clock

Frame Frequency (Hz)

(When f

SUB

= 32.768 kHz)

00
01
10
11

SUB

128

SUB

256

1024

512
256
128

Table 18-1 Setting of LCD Frame Frequency

GMS81C7008/7016

APR., 2001 Ver 2.01

LCD Port Selection

Segment pins are also used for normal I/O pins. The LCD port se-
lection register LPMR is used to set Rn pin for ordinary digital in-
put. Refer to LPMR register as shown in Figure 18-2.

Bias Resistor

To operate LCD, built-in Bias resistor dividing V

to V

section into several stages generates necessary voltage.

The BTC (Bit 6 of LCR) switches Transistor supplying voltage to
serially connected Bias resistor. If it is `1', it turns on, and if it is
`0', it turns off. The LCD drive voltage (V

CL2

) is given by the dif-

ference in potential (V

-V

CL2

) between pins V

and V

CL2

Therefore, when the MCU operating voltage is 5V and LCD drive
voltage are the same, the Bias pin is connected to the V

CL2

pin as

shown in (a) of Figure 18-5.

Figure 18-4 Application Example of 5V LCD Panel

When require supply 3V output to the LCD, the voltage of V

CL2

becomes 3V as shown in Figure 18-5. Because V

is down to

3V through internal 2R resistor.

The LCD light only when the difference in potential between the
segment and common output is ±VCL, and turn off at all other
times. During reset, the power switch of the LCD driver is turned
off automatically, shutting off the VCL voltage.

one frame

(at 1/4 duty, 1/3 bias)

COM0 pin

VCL1

VCL2

BIAS

BTC

(a) Internal, Static or 1/3 Bias

BTC = "1"

BRC = "1"

ter

nal

i
a

sisto

r
s

MCU Internal

VCL0

BRC

BTC

(b) Internal, Static or 1/2 Bias

BTC = "1"

BRC = "1"

Two pins are connected
each other

ter

nal

i
a

sisto

r
s

MCU Internal

BRC

Typ. R=65k

VCL1

VCL2

BIAS

VCL0

Short two pins
each other externally

VCL2=5V
VCL1=3.33V
VCL0=1.67V

VCL2=5V
VCL1=2.5V
VCL0=2.5V

GMS81C7008/7016

APR., 2001 Ver 2.01

Figure 18-5 Application Example of 3V LCD Panel

Some user want to use external bias resisor instead of internal,
you can connect external resistor as shown in Figure 18-6. And

the external capacitors are may required for stable display accord-
ing to your system environment.

Figure 18-6 External Resistor

VCL1

VCL2

BIAS

BTC

= 5V

(a) Internal, Static or 1/3 Bias

BTC = "1"

BRC = "1"

Short two pins
externally

ter

nal B

i
a

sistor

MCU Internal

VCL0

BRC

Typ. R=65k

BTC

= 5V

(b) Internal, Static or 1/2 Bias

BTC = "1"

BRC = "1"

ter

nal B

i
a

sistor

MCU Internal

BRC

Typ. R=65k

VCL1

VCL2

BIAS

VCL0

VCL2=3V
VCL1=2V
VCL0=1V

VCL2=3V
VCL1=1.5V
VCL0=1.5V

VCL1

VCL2

BIAS

BTC

BTC = "0"

BRC = "0"

External circuit

ter

nal

i
a

sisto

r
s

MCU Internal

VCL0

BRC

Adjust Contrast

GMS81C7008/7016

APR., 2001 Ver 2.01

18.4 LCD Display Memory

Display data are stored to the display data area (address
100

-11A

) in the data memory.

The display data stored to the display data area are read au-
tomatically and sent to the LCD driver by the hardware.

The LCD driver generates the segment signals and com-
mon signals in accordance with the display data and drive
method.

Figure 18-7

LCD Display Memory

Therefore, display patterns can be changed by only over-
writing the contents of the display data area with a pro-
gram. The table look up instruction is mainly used for this
overwriting.
Figure 18-7 shows the correspondence between the display
data area and the SEG/COM pins. The LCD lights when
the display data is "1" and turn off when "0".
The number of segment which can be driven differs de-
pending on the LCD drive method, therefore, the number
of display data area bits used to store the data also differs

(Refer to Figure 18-2). Consequently, data memory not

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

COM

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

Bit

100

101

102

103

104

105

106

107

108

109

10A

10B

10C

10D

10E

10F

110

111

112

113

114

115

116

117

118

119

11A

Note:
The bit 4 to 7 of every byte are
reserved. Any read or write is not
effect.

Drive methods

Bit 3

Bit 2

Bit 1

Bit 0

1/4 duty

COM3

COM2

COM1

COM0

1/3 duty

COM2

COM1

COM0

1/2 duty

COM1

COM0

Static

COM0

Table 18-2 The duty vs. COM port Configuration

GMS81C7008/7016

APR., 2001 Ver 2.01

used to store display data and data memory for which the
address are not connected to LCD can be used to store or-
dinary user's processing data.

Blanking

Blanking is applied by setting LCDEN (bit 7 of LCR) to "0" and

turns off the LCD by outputting the non light operation level to
the COM pin. When setting Frame frequency or changing operat-
ing mode, LCD display should be off before operation, to prevent
display flickering.

18.5 Control Method of LCD Driver

Initial Setting

Flow chart of initial setting is shown in Figure 18-8.

Example: When operating with 1/4 duty LCD using a

frame frequency of 512Hz.

Figure 18-8 Initial Setting of LCD Driver

Figure 18-9 Example of Connection COM & SEG

Display Data Setting

Normally, display data are kept permanently in the pro-
gram memory and then stored at the display data area by
the table look-up instruction. This can be explained using

numerical display with 1/4 duty LCD as an example. The
COM and SEG connections to the LCD and display data
are the same as those shown is Figure 18-9. Programming

LDM

LCR,#0101_0001B ;1/4duty, f

=512Hz

SUB

= 32.768kHz)

:
SETG
LDM

RPR,#1

;Select LCD Memory
;area (Page 1 = address 1XX

)

LDX

C_LCD1:

LDA

;RAM Clear
;RAM(100H~11AH)

STA

{X}+

CMPX

#01BH

BNE

C_LCD1

CLRG
:
:
SET1

LCR.5

;Enable LCD display

:
:

Clear

LCD Display

Memory

Select Frame Frequency

Turn on LCD

Setting of LCD drive method

Initialize of display memory

Enable display

(Release of blanking)

SEG0

SEG1

COM3

COM0

COM1

COM2

Example: display "2"

100

101

bit 7

Note: * are don't care.

GMS81C7008/7016

APR., 2001 Ver 2.01

19. WATCH / WATCHDOG TIMER

19.1 Watch Timer

The watch timer goes the clock continuously even during the
power saving mode. When MCU is in the Stop or Sleep mode,
MCU can wake up itself every 2Hz or 4Hz or 16Hz.

The watch timer consists of input clock selector, 14-bit binary
counter, interval selector and Watch Timer Mode Register
WTMR (address 0EF

). The WTMR is 5-bit read/write register

and shown in Figure 19-2. WTMR can select the clock input by
2 bits WTCK[1:0] and interval time selector by 2 bits WTIN[1:0]
and enable/disable bit. The WTEN bit is set to "1" timer start
counting. Input clocks can be selected among three different
source which are sub clock or divided main clock (f

XIN

128) or

main clock. For the switching between main and sub clock, rec-

ommend the oscillator 4.194304MHz as a main and 32.768kHz
as a sub. Because above main frequency is equal to 128 times of
sub frequency. Generally main clock (f

XIN

) at WTCK=10

is not

be used, it is just for test purpose in factory.

In the Stop Mode, the main clock is stopped but sub clock is os-
cillation continuously for watch clock operation. Output timer in-
terval can be selected and Watch Timer Interrupt is generated.

LDM

IENL,#XXXX_X1XXB

EI
LDM

WTMR,#0100_1000B

Figure 19-1 Block Diagram of Watchdog Timer

19.2 Watchdog Timer

The watchdog timer rapidly detects the CPU malfunction such as
endless looping caused by noise or the like, and resumes the CPU
to the normal state.
The watchdog timer signal for detecting malfunction can be se-
lected either a reset CPU or a interrupt request as you want.

When the watchdog timer is not being used for malfunction de-
tection, it can be used as a timer to generate an interrupt at fixed
intervals.

Watchdog Timer Control

Figure 19-2 shows the watchdog timer control register WDTR
(address 0DF

). The watchdog timer is automatically enabled

initially and watchdog output to reset CPU but clock input source
is disabled. To enable this function, you should write bit WTEN
of WTMR (address 0EF

) set to "1".

The CPU malfunction is detected during setting of the detection
time, selecting of output, and clearing of the binary counter.
Clearing the 2-bit binary counter by bit WDCLR of WDTR is re-
peated within the detection time.

If the malfunction occurs for any cause, the watchdog timer out-
put will become active from the binary counters unless the binary
counter is cleared. At this time, when WDOM=1, a reset is gen-
erated, which drives the RESET pin to low to reset the internal
hardware. When WDOM=0, a watchdog timer interrupt (WD-
TIF) is generated instead of Reset function. This interrupt can be
used general timer as user want.

When main clock is selected as clock input source on the STOP
mode, clock input is stopped so the watchdog timer temporarily
stops counting. The other side, when sub clock is selected as
clock input source on the STOP mode, sub clock operates always

enable

Watch Timer interrupt

WTIF

14-bit Binary Counter

MUX

SXIN

XIN

128

XIN

SXIN

= 32.768 kHz

XIN

= 4.194304 MHz

Interval Selector

2-bit Binary Counter

WDCK[1:0]

WTIN[1:0]

WTCK[1:0]

WDOE[0DF

]

R34/WDTO

clea

0: Stop
1: Clear and start

WDCLR

WDTIF

to RESET CPU

Watchdog Timer Interrupt

overflow

WDEN

WDOM

10 11

enable

WTEN

MUX

When

GMS81C7008/7016

APR., 2001 Ver 2.01

so the watchdog timer works continuously.

Figure 19-2 WTMR, WDTR: Watch Timer and Watchdog Timer Data Register

Example: Sets the watchdog timer detection time to 1 sec at 4.19MHz, 32.768kHz

Enable and Disable Watchdog

Watchdog timer is enabled by setting WDEN (bit 4 in CKCTLR)
to "1". WDEN is initialized to "1" during reset and it should be
clear to "0" disable.

Example: Enables watchdog timer for Reset

:
LDM

WTMR,#0100_XXXXB;

WTEN

LDM

WDTR,#00X1_XX11B;

WDEN

The watchdog timer is disabled by clearing either bit 4 (WDEN)
of WDTR or bit 6 (WTEN) of WTMR. The watchdog timer is
halted in STOP mode and restarts automatically after STOP mode
is released.

Clearing 2-bit binary counter of the Watchdog
timer

The watchdog timer count the clock source as 14-bit binary

INITIAL VALUE: -0--_0000

ADDRESS: 0EF

WTMR

WTEN

WTIN1 WTIN0

R/W

WTCK1 WTCK0

Clock source selection
00: Sub clock
01: Main clock (f

XIN

128)

10: Main clock (test purpose in factory)
11: -

Watch timer interrupt interval selection
00: 16Hz
01: 4Hz
10: 2Hz
11: -

Watch Timer count enable
0: Disable
1: Enable

INITIAL VALUE: --01_0010

ADDRESS: 0DF

WDTR

W D O E

W D C K 1 W D C K 0

R/W

W D E N

W D O M W D C LR

Watchdog timer interrupt interval selection
00: 2 sec.
01: 1 sec.
10: 0.5 sec.
11: 0.25 sec.

R34/WDTO selection
0: R34 port
1: WDTO port

R/W

Clear bit
0: Normal operation
1: Clear and starts counting

When

SXIN

= 32.768kHz

XIN

= 4.19MHz

Output Mode
0: Interrupt request
1: Reset CPU

Watchdog Timer count enable

0: Disable
1: Enable

When

SXIN

= 32.768kHz

XIN

= 4.19MHz

LDM

WTMR,#0100_1000B

;

Select sub clock as an input source

LDM

WDTR,#0001_0111B

SET1

WDCLR

;

Clear counter

:
:
:
:
SET1

WDCLR

;

Clear counter

:
:
:
:
SET1

WDCLR

;

Clear counter

Within 0.75 sec.

GMS81C7008/7016

APR., 2001 Ver 2.01

counter which is free run can not be cleared. The watchdog timer
has 2-bit binary counter. It is incremented by 14-bit binary
counter match as shown in Figure 19-1. Interrupt request flag or
Reset signal are generated by overflow 2-bit binary counter.

During normal operation in the software, 2-bit binary counter

should be cleared by bit WDCLR of WDTR within watchdog
timer overflow.
The time of clearing must be within 3 times of 14-bit binary
counter interval as shown in Figure 19-3.

The worst case, watchdog time is just 3 times of 14-bit counter.

Figure 19-3 Watchdog timer Timing

If the watchdog timer output becomes active, a reset is generated,
which drives the RESET pin low to reset the internal hardware.

The main clock oscillator also turns on when a watchdog timer re-
set is generated in sub clock mode.

14-bit binary

2-bit binary

WDTIF interrupt

Write WDCLR = 1 at this point

Counter
Clear

counter

R34/WDTO pin

reset

1FFE

1FFF

counter

1FFE

1FFF

1FFE

1FFF

1FFE

1FFF

8 osc.

(2us at f

XIN

=4.19MHz)

Even if user set to 1 sec.,

When WDTR = 0011_0111B

worst case 0.75 second

GMS81C7008/7016

APR., 2001 Ver 2.01

20. POWER DOWN OPERATION

The GMS81C7008/16 has two power-down modes. In power-
down mode, power consumption is reduced considerably that in
Battery operation Battery life can be extended a lot.

Sleep mode is entered by setting bit 0 of Sleep Mode Reg-
ister, and STOP Mode is entered by STOP instruction.

20.1 SLEEP Mode

In this mode, the internal oscillation circuits remain active.

Oscillation continues and peripherals are operate normally but
CPU stops. Movement of all Peripherals is shown in Table 20-1.
Sleep mode is entered by setting bit 0 of SMR (address 0DE

It is released by RESET or interrupt. To be release by interrupt,
interrupt should be enabled before Sleep mode.

Figure 20-1 SLEEP Mode Register

Figure 20-2 Sleep Mode Release Timing by External Interrupt

Figure 20-3 SLEEP Mode Release Timing by RESET pin

Sleep Mode Register

SMR

ADDRESS : 0DE

RESET VALUE : -------0

0: Release Sleep Mode
1: Enter Sleep Mode

Oscillator

Normal Operation

Stand-by Mode

Normal Operation

Interrupt

Internal CPU Clock

Release

Set bit 0 of SMR

or SX

pin)

Oscillator

or SX

pin)

BIT Counter

= 62.5ms

RESET

Internal CPU Clock

Clear & Start

Normal Operation

Sleep Mode

Normal Operation

Release

Set bit 0 of SMR

~~
~~

at 4.19MHz by hardware

x 256

MAIN

1024

GMS81C7008/7016

APR., 2001 Ver 2.01

20.2 STOP Mode

For applications where power consumption is a critical
factor, device provides reduced power of STOP.

Start The Stop Operation

An instruction that STOP causes to be the last instruction
is executed before going into the STOP mode. In the Stop

mode, the on-chip main-frequency oscillator is stopped.
With the clock frozen, all functions are stopped, but the on-
chip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.

Note: Since the X

pin is connected internally to GND to

avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.

In the Stop mode of operation, V

can be reduced to minimize

power consumption. Be careful, however, that V

is not re-

duced before the Stop mode is invoked, and that V

is restored

to its normal operating level before the Stop mode is terminated.

The reset should not be activated before V

is restored to its

normal operating level, and must be held active long enough to
allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP instruction
should be written as shown in example below.

Example)

LDM

CKCTLR,#0EB ;32.8ms

;

LDM

CKCTLR,#0FB ;65.5ms

STOP
NOP
NOP

The Interval Timer Register CKCTLR should be initialized (0F

or 0E

) by software in order that oscillation stabilization time

should be longer than 20ms before STOP mode.

Release the STOP mode

The exit from STOP mode is using hardware reset or external in-
terrupt, watch timer, key scan or timer/counter.

To release STOP mode, corresponding interrupt should be
enabled before STOP mode.
Specially as a clock source of Timer/Event counter, EC0 or EC2
pin can release it by Timer/Event counter

Interrupt request

Reset redefines all the control registers but does not change the
on-chip RAM. External interrupts allow both on-chip RAM and
Control registers to retain their values.

Start-up is performed to acquire the time for stabilizing oscilla-
tion. During the start-up, the internal operations are all stopped.

Peripheral

STOP Mode

SLEEP Mode

CPU

All CPU operations are disabled

RAM

Retain

LCD driver

LCD driver operates continuously

Basic Interval Timer

Halted

BIT operates continuously

Timer/Event counter

Halted (Only when the Event counter mode
is enabled, Timer operates normally)

Timer/Event counter operates continuously

Watch Timer

Watch Timer operates continuously

Main-oscillation

Stop (X

pin = "L", X

OUT

pin = "L")

Oscillation

Sub-oscillation

Oscillation

I/O ports

Retain

Control Registers

Retain

Release method

RESET, Key Scan interrupt, SIO interrupt,
Watch Timer interrupt, Timer interrupt
(EC0,2), External interrupt

RESET, All interrupts

Table 20-1 Peripheral Operation during Power Down Mode

GMS81C7008/7016

APR., 2001 Ver 2.01

Figure 20-4 STOP Mode Release Timing by External Interrupt

Figure 20-5 STOP Mode Release Timing by RESET

Minimizing Current Consumption

The Stop mode is designed to reduce power consumption.
To minimize current drawn during Stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.

Note: In the STOP operation, the power dissipation asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the

pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
of the STOP feature. This point should be little current flows
when the input level is stable at the power voltage level
(V

); however, when the input level becomes higher

than the power voltage level (by approximately 0.3V), a cur-
rent begins to flow. Therefore, if cutting off the output tran-
sistor at an I/O port puts the pin signal into the high-
impedance state, a current flow across the ports input tran-
sistor, requiring it to fix the level by pull-up or other means.

Before executing Stop instruction, Basic Interval Timer must be set

Oscillator

pin)

BIT Counter

n+1

n+2

n+3

Normal Operation

Stop Operation

Normal Operation

20ms

External Interrupt

Internal Clock

Clear

STOP Instruction
Executed

properly by software to get stabilization time which is longer than 20ms.

by software

Oscillator

pin)

BIT Counter

n+1

n+2

n+3

Normal Operation

Stop Operation

Normal Operation

> 62.5ms

Internal Clock

Clear

STOP Instruction

Executed

at 4.19MHz by hardware

RESET

n+2

x 256

MAIN

1024

GMS81C7008/7016

APR., 2001 Ver 2.01

It should be set properly that current flow through port doesn't ex-
ist.

First consider the setting to input mode. Be sure that there is no
current flow after considering its relationship with external cir-
cuit. In input mode, the pin impedance viewing from external
MCU is very high that the current doesn't flow.

But input voltage level should be V

or V

. Be careful that if

unspecified voltage, i.e. if un-firmed voltage level (not V

) is applied to input pin, there can be little current (max. 1mA

at around 2V) flow.

If it is not appropriate to set as an input mode, then set to output
mode considering there is no current flow. Setting to High or Low
is decided considering its relationship with external circuit. For
example, if there is external pull-up resistor then it is set to output
mode, i.e. to High, and if there is external pull-down register, it is
set to low.

Figure 20-6 Application Example of Unused Input Port

Figure 20-7 Application Example of Unused Output Port

INPUT PIN

GND

Weak pull-up current flows

internal
pull-up

INPUT PIN

Very weak current flows

OPEN

i=0

GND

When port is configure as an input, input level should
be closed to 0V or 5V to avoid power consumption.

OUTPUT PIN

GND

In the left case, much current flows from port to GND.

OFF

OUTPUT PIN

GND

In the left case, Tr. base current flows from port to GND.

i=0

OFF

OPEN

GND

OFF

To avoid power consumption, there should be low output

OFF

to the port .

GMS81C7008/7016

APR., 2001 Ver 2.01

21. OSCILLATOR CIRCUIT

The GMS81C7008/16 has two oscillation circuits internally. X

and X

OUT

are input and output for main frequency and SX

and

OUT

are input and output for sub frequency, respectively, in-

verting amplifier which can be configured for being used as an
on-chip oscillator, as shown in Figure 21-1. To use RC oscillation
instead of crystal, user should check mark on the "A. MASK OR-
DER SHEET" on page i of the appendix of this manual. However
in the OTP device, when the programming RC oscillation can be
selected or not into the configuration bit. For more detail, refer to

"24.1 OTP Programming" on page 89.

Note: When using the sub clock oscillation, connect a re-
sistor in series with R which is shown as below figure.
In order to reduce the power consumption, the sub clock
oscillator employs a low amplification factor circuit. Be-
cause of this, the sub clock oscillator is more sensitive to
noise than the main system clock oscillator.

Figure 21-1 Oscillation Circuit

Oscillation circuit is designed to be used either with a ceramic
resonator or crystal oscillator. Since each crystal and ceramic res-
onator have their own characteristics, the user should consult the
crystal manufacturer for appropriate values of external compo-
nents.

Note: Minimize the wiring length. Do not allow the wiring to
intersect with other signal conductors. Do not allow the wir-
ing to come near changing high current. Set the potential of
the grounding position of the oscillator capacitor to that of
V

. Do not ground it to any ground pattern where high cur-

rent is present. Do not fetch signals from the oscillator.

Figure 21-2 Recommend Layout of Oscillator PCB

circuit

OUT

Recommend

C1,C2 = 20pF

OUT

External Clock

Open

OUT

External Oscillator

RC Oscillator (mask option)

Crystal or Ceramic Oscillator

OUT

Recommend
C1,C2 = 30pF±5pF

32.768kHz

4.19MHz

Crystal Oscillator

Ceramic Resonator

C1,C2 = 30pF

Refer to AC Characteristics

For selection R value,

EXT

R= 47k

±5k

OUT

GMS81C7008/7016

APR., 2001 Ver 2.01

22. RESET

The GMS81C7008/16 has two types of reset generation proce-
dures; one is an external reset input, the other is a watch-dog tim-
er reset. Table 22-1 shows on-chip hardware initialization by
reset action.

Figure 22-1 Simple Power-on-Reset Circuit.

22.1 External Reset Input

The reset input is the RESET pin, which is the input to a Schmitt
Trigger. A reset in accomplished by holding the RESET pin low
for at least 8 oscillator periods, within the operating voltage range
and oscillation stable, it is applied, and the internal state is initial-
ized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods
are required to start execution as shown in Figure 22-2.

Internal RAM is not affected by reset. When V

is turned on,

the RAM content is indeterminate. Therefore, this RAM should

be initialized before read or tested it.

When the RESET pin input goes to high, the reset operation is re-
leased and the program execution starts at the vector address
stored at addresses FFFE

- FFFF

A connection for simple power-on-reset is shown in Figure .

Figure 22-2 Timing Diagram after RESET

22.2 Watchdog Timer Reset

Refer to "18. LCD DRIVER" on page 70.

7036P

10uF

10k

to the RESET pin

On-chip Hardware

Initial Value

Program counter (PC)

(FFFF

) - (FFFE

)

G-flag (G)

Operation mode

Main operating mode

Peripheral clock

Watchdog timer

Disable (Because the Watch

timer is disabled)

Control registers

Refer to Table 8-1 on

page 25

Low voltage detector

Enable

Table 22-1 Initializing Internal Status by Reset Action

MAIN PROGRAM

Oscillator

pin)

FFFE FFFF

Stabilization Time

= 62.5mS at 4.19MHz

RESET

ADDRESS

DATA

Start

ADL

ADH

BUS

RESET Process Step

~~
~~

x 256

MAIN

1024

GMS81C7008/7016

APR., 2001 Ver 2.01

23. POWER FAIL PROCESSOR

The GMS81C7008/16 has an on-chip low voltage detection cir-
cuitry to detect the V

voltage. A configuration register, LVDR

(address 0FB

), can enable or disable the low voltage detect cir-

cuitry. Whenever V

falls close to or below 2.2V, the LVD0 is

just set to "1", and if it recovering 3.4V, LVD0 is held to "1". If
V

falls below around 3.4V range, the low voltage situation

may reset the MCU or freeze the clock according to setting of bit
5 (LVDM) of LVDR . The bit 4 LVD1 function is same with
LVD0 except different voltage level 2.1V. The detection voltage
is varied very little. See "7.3 DC Electrical Characteristics" on
page 11 for more detail voltage level.

In the in-circuit emulator, power fail function is not implemented
and user may not use it. Therefore, after completed development
of user program, this function may be experimented or evaluated
using by OTP.

When power fail certainly occur the MCU was reset, program no-
tify this Reset circumstance cause by LVD function. So, does not
erase the all RAM contents and operates subsequently as shown
in Figure .

Figure 23-1 Low Voltage Detector Register

LVDE

INITIAL VALUE: 00

ADDRESS: 0FB

LVDR

R/W

LVD1

Operation Mode
0: Clock freeze
1: Reset

Enable / Disable Flag
0: Disable
1: Enable

LVDS

LVD0

Power Fail Voltage Selection
0: 3.4V
1: 2.1V

R/W

LVDM

Detection Flag 1

0: Above 3.4V
1: Below 3.4V

Detection Flag 2

0: Above 2.1V
1: Below 2.1V

Figure 23-2 Example S/W of RESET by Power fail

FUNTION

EXECUTION

INITIALIZE RAM DATA

LVD0 =1

RESET VECTOR

INITIALIZE ALL PORTS

INITIALIZE REGISTERS

RAM CLEAR

YES

Skip the initial routine when
the Reset cause from power fail.

GMS81C7008/7016

APR., 2001 Ver 2.01

24. DEVELOPMENT TOOLS

24.1 OTP Programming

The GMS87C7016 is OTP (One Time Programmable) type mi-
crocontrollers. Its internal user memory is constructed with
EPROM (Electrically Programmable Read Only Memory).

The OTP microcontroller is generally used for chip evaluation,
first production, small amount production, fast mass production,
etc.

Blank OTP's internal EPROM is filled by 00

, not FF

Note: In any case, you have to use the *.OTP file for pro-
gramming, not the *.HEX file. After assemble the source
program, both OTP and HEX file are generated by automat-
ically. The HEX file is used during program emulation on
the emulator.

How to Program

To program the OTP devices, user should use HEI own program-
mer. Ask to HEI sales part for purchasing or more detail.

Programmer: CHOICE-SIGMA (Single type)

CHOICE-GNAG4 (4-gang type)

Socket adapter:87C70XX-64SD (for 64SDIP)

87C70XX-64QF (for 64MQFP)

The CHOICE-SIGMA is a HEI Universal Single Programmer for
all of HEI OTP devices, also the CHOICE-GANG4 can program
four OTPs at once.

Programming Procedure

1. Select device GMS87C7016 as you want.

2. Load the *.OTP file from the PC to Programmer. The

file is composed of Motorola-S1 format.

3. Set the programming address range as below table.

4. Mount the socket adapter on the programmer.

5. Set the configuration bytes as your needs.

6. Start program/verify.

Select the option for Program Lock and RC oscil-
lation

Except the user program memory C000

~FFFF

, there is config-

uration byte (address 707F

) for the selection of program lock

and RC oscillation. The configuration byte of OTP is shown as
Figure 24-1. It could be served when user use the OTP program-
mer (Choice-Sigma or Choice-Gang4).

Figure 24-1 The OTP Configuration Byte

87C70XX-64SD

87C70XX-64QF

87C71XX-52SD

ADDRESS: 707F

OTP Configuration Byte

LOCK

0: Crystal or Resonator
1: External RC Oscillator

0: Allow code read out
1: Not allow code read out

Lock bit

Oscillation Option

GMS

C7008/7

016

APR.

, 2001

Ver 2.

24.

2 Emul

ator

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-B86(5$

OFF

6XSSO

\
#.

8
9
#+
PD

[
1#
533

VR1

r
n

l
o

scilla

socke

GMS81C7008/7016

APR., 2001 Ver 2.01

DIP Switch and VR Setting

Before execute the user program, keep in your mind the below configuration

DIP S/W, VR

Description

ON/OFF Setting

SW1

Emulator Reset Switch. Reset the Emulator.

Reset the Emulator.

SW2

Pod RESET pin configuration

Normally OFF.
EVA. chip can be reset by external
user target board.
ON : Reset is available by either
user target system board or Emula-
tor RESET switch.
OFF : Reset the MCU by Emulator
RESET switch. Does not work from
user target board.

Pod XOUT pin configuration

Normally OFF.
MCU XOUT pin is disconnected
internally in the Emulator. Some cir-
cumstance user may connect this
circuit.
ON : Output XOUT signal
OFF : Disconnect circuit

SW4

1
2
3

External Bias Resistors Connection

Must be ON position.
It serves the external bias resistors.
If this switches are turned off, LCD
bias voltage does not supplied,
floated because there are no inter-
nal bias resistors and bias Tr. inside
the Emulator.

4
5
6

LCD Voltage doubling circuit.

Must be OFF position.
It is reserved for the GMS81C5108.

Select the Stack Page.

Must be ON position.
This switch select the Stack page 0
(off) or page 1 (on).
ON : For the 81C7XXX
OFF : For the GMS81C5108

81Cx detect the VDD voltage but Emulator can not do because
Emulator can not operate if V

is below normal opr. voltage

(5V), This switch serves LVD environment through the applying
0V to LVD pin of EVA. chip during 5V normal operation.

Position ON during normal opera-
tion.
ON : Normal operation
OFF : Force to detect the LVD, refer
to "23. POWER FAIL PROCES-
SOR" on page 87.

SW2-1

RESET pin

EVA.
Chip

SW2-2

XOUT pin

EVA.
Chip

Oscillator

VCL1

VCL2

BIAS

External Resistor

EVA. Chip Internal

VCL0

Adjust Contrast

SW4-1

SW4-2

SW4-3

0.47uF

10k

and Capacitor

VR1 50k

SW4

SW4-8

EVA.
Chip

LVD pin

A. MASK ORDER SHEET

1. Customer Information

Company Name

2. Device Information

3. Marking Specification

4. Delivery Schedule

Customer Sample

Date

YYYY

MM DD

Risk Order

YYYY

MM DD

Quantity Hynix Confirmation

Application

Order Date

YYYY

MM DD

Tel: Fax:

Name &
Signature:

Package

64SDIP 64MQFP

5. ROM Code Verification

Verification D ate:

YYYY

MM DD

Approval Date:

YYYY

MM DD

Please confirm our verification data.

I agree w ith your verification data and confirm

you to m ake m ask set.

Check Sum:

Tel: Fax:

Name &
Signature:

Tel: Fax:

Name &
Signature:

C000

E000

FFFF

.OTP file data

DFFF

Mask Data

Internet

File Name: ( .OTP)

(Please check mark into )

pcs

Check Sum: ( )

Customer should write inside thick line box.

This box is written after "5.Verification".

R C O SC O pt.

Crystal RC

GMS

81C

701

6 (1

7008 (8K

ROM Size

8K 16K

YYWW KOREA

Customer's logo

Customer logo is not required.

YYWW KOREA

GMS81C70

Customer's part number

If the customer logo must be used in the special mark, please submit a clean original of the logo.

08 or 16

E-mail:

01-APR-2001

MASK ORDER & VERIFICATION SHEET

GMS81C7008

-LA

GMS81C7016

-LA

GMS81C70

-LA

Lot Number

Hynix ROM Code
Number

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

B. INSTRUCTION

B.1 Terminology List

Terminology

Description

Accumulator

X - register

Y - register

PSW

Program Status Word

#imm

8-bit Immediate data

Direct Page Offset Address

!abs

Absolute Address

[ ]

Indirect expression

{ }

{ }+

.bit

Bit Position

A.bit

Bit Position of Accumulator

dp.bit

Bit Position of Direct Page Memory

M.bit

Bit Position of Memory Data (000

~0FFF

)

rel

Relative Addressing Data

upage

U-page (0FF00

~0FFFF

) Offset Address

Table CALL Number (0~15)

Addition

Upper Nibble Expression in Opcode

Subtraction

Multiplication

Division

( )

Contents Expression

AND

Exclusive OR

NOT

Assignment / Transfer / Shift Left

Shift Right

Exchange

Equal

Not Equal

Bit Position

GMS81C71XX LCD MCU APPENDIX

iii

APR. 2001 Ver 2.01

B.2 Instruction Map

LOW

HIGH

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

000

SET1
dp.bit

BBS

A.bit,rel

BBS

dp.bit,rel

ADC

#imm

ADC

dp+X

ADC

!abs

ASL

TCALL

SETA1

.bit

BIT

POP

PUSH

BRK

001

CLRC

SBC

#imm

SBC

dp+X

SBC

!abs

ROL

TCALL

CLRA1

.bit

COM

POP

PUSH

BRA

rel

010

CLRG

CMP

#imm

CMP

dp+X

CMP

!abs

LSR

TCALL

NOT1

M.bit

TST

POP

PUSH

PCALL

Upage

011

#imm

dp+X

!abs

ROR

TCALL

OR1

OR1B

CMPX

POP

PSW

PUSH

PSW

RET

100

CLRV

AND

#imm

AND

dp+X

AND

!abs

INC

TCALL

AND1

AND1B

CMPY

CBNE

dp+X

TXSP

INC

101

SETC

EOR

#imm

EOR

dp+X

EOR

!abs

DEC

TCALL

EOR1

EOR1B

DBNE

XMA

dp+X

TSPX

DEC

110

SETG

LDA

#imm

LDA

dp+X

LDA
!abs

TXA

LDY

TCALL

LDC

LDCB

LDX

dp+Y

XCN

DAS

111

LDM

dp,#imm

STA

dp+X

STA
!abs

TAX

STY

TCALL

STC

M.bit

STX

dp+Y

XAX

STOP

LOW

HIGH

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

000

BPL

rel

CLR1

dp.bit

BBC

A.bit,rel

BBC

dp.bit,rel

ADC

{X}

ADC

!abs+Y

ADC

[dp+X]

ADC

[dp]+Y

ASL
!abs

ASL

dp+X

TCALL

JMP

!abs

BIT

!abs

ADDW

LDX

#imm

JMP

[!abs]

001

BVC

rel

SBC

{X}

SBC

!abs+Y

SBC

[dp+X]

SBC

[dp]+Y

ROL

!abs

ROL

dp+X

TCALL

CALL

!abs

TEST

!abs

SUBW

LDY

#imm

JMP

[dp]

010

BCC

rel

CMP

{X}

CMP

!abs+Y

CMP

[dp+X]

CMP

[dp]+Y

LSR
!abs

LSR

dp+X

TCALL

MUL

TCLR1

!abs

CMPW

CMPX

#imm

CALL

[dp]

011

BNE

rel

{X}

!abs+Y

[dp+X]

[dp]+Y

ROR

!abs

ROR

dp+X

TCALL

DBNE

CMPX

!abs

LDYA

CMPY

#imm

RETI

100

BMI

rel

AND

{X}

AND

!abs+Y

AND

[dp+X]

AND

[dp]+Y

INC

!abs

INC

dp+X

TCALL

DIV

CMPY

!abs

INCW

INC

TAY

101

BVS

rel

EOR

{X}

EOR

!abs+Y

EOR

[dp+X]

EOR

[dp]+Y

DEC

!abs

DEC

dp+X

TCALL

XMA

{X}

XMA

DECW

DEC

TYA

110

BCS

rel

LDA

{X}

LDA

!abs+Y

LDA

[dp+X]

LDA

[dp]+Y

LDY
!abs

LDY

dp+X

TCALL

LDA
{X}+

LDX
!abs

STYA

XAY

DAA

111

BEQ

rel

STA

{X}

STA

!abs+Y

STA

[dp+X]

STA

[dp]+Y

STY
!abs

STY

dp+X

TCALL

STA
{X}+

STX
!abs

CBNE

XYX

NOP

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

B.3 Instruction Set

Arithmetic / Logic Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

ADC #imm

Add with carry.

ADC dp

( A ) + ( M ) + C

ADC dp + X

ADC !abs

NV--H-ZC

ADC !abs + Y

ADC [ dp + X ]

ADC [ dp ] + Y

ADC { X }

AND #imm

Logical AND

AND dp

( A )

( M )

AND dp + X

AND !abs

N-----Z-

AND !abs + Y

AND [ dp + X ]

AND [ dp ] + Y

AND { X }

ASL A

Arithmetic shift left

ASL dp

N-----ZC

ASL dp + X

ASL !abs

CMP #imm

Compare accumulator contents with memory contents
( A ) - ( M )

CMP dp

CMP dp + X

CMP !abs

N-----ZC

CMP !abs + Y

CMP [ dp + X ]

CMP [ dp ] + Y

CMP { X }

CMPX #imm

Compare X contents with memory contents

CMPX dp

( X ) - ( M )

N-----ZC

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

CMPY dp

( Y ) - ( M )

N-----ZC

CMPY !abs

COM dp

1'S Complement : ( dp )

~( dp )

N-----Z-

DAA

Decimal adjust for addition

N-----ZC

DAS

Decimal adjust for subtraction

N-----ZC

DEC A

Decrement

N-----Z-

DEC dp

( M ) - 1

N-----Z-

DEC dp + X

N-----Z-

DEC !abs

N-----Z-

DEC X

N-----Z-

DEC Y

N-----Z-

7 6 5 4 3 2 1 0

"0"

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

DIV

Divide : YA / X Q: A, R: Y

NV--H-Z-

EOR #imm

Exclusive OR

EOR dp

( A )

( M )

EOR dp + X

EOR !abs

N-----Z-

EOR !abs + Y

EOR [ dp + X ]

EOR [ dp ] + Y

EOR { X }

INC A

Increment

N-----ZC

INC dp

( M ) + 1

N-----Z-

INC dp + X

N-----Z-

INC !abs

N-----Z-

INC X

N-----Z-

INC Y

N-----Z-

LSR A

Logical shift right

LSR dp

N-----ZC

LSR dp + X

LSR !abs

MUL

Multiply : YA

N-----Z-

OR #imm

Logical OR

OR dp

( A )

( M )

OR dp + X

OR !abs

N-----Z-

OR !abs + Y

OR [ dp + X ]

OR [ dp ] + Y

OR { X }

ROL A

Rotate left through Carry

ROL dp

N-----ZC

ROL dp + X

ROL !abs

ROR A

Rotate right through Carry

ROR dp

N-----ZC

ROR dp + X

ROR !abs

SBC #imm

Subtract with Carry

SBC dp

( A ) - ( M ) - ~( C )

SBC dp + X

SBC !abs

NV--HZC

SBC !abs + Y

SBC [ dp + X ]

SBC [ dp ] + Y

SBC { X }

TST dp

Test memory contents for negative or zero, ( dp ) - 00

N-----Z-

XCN

Exchange nibbles within the accumulator
A

N-----Z-

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

7 6 5 4 3 2 1 0

"0"

7 6 5 4 3 2 1 0

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

Register / Memory Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

LDA #imm

Load accumulator

LDA dp

( M )

LDA dp + X

LDA !abs

LDA !abs + Y

N-----Z-

LDA [ dp + X ]

LDA [ dp ] + Y

LDA { X }

LDA { X }+

X- register auto-increment : A

( M ) , X

X + 1

LDM dp,#imm

Load memory with immediate data : ( M )

imm

--------

LDX #imm

Load X-register

LDX dp

( M )

N-----Z-

LDX dp + Y

LDX !abs

LDY #imm

Load Y-register

LDY dp

( M )

N-----Z-

LDY dp + X

LDY !abs

STA dp

Store accumulator contents in memory

STA dp + X

( M )

STA !abs

STA !abs + Y

--------

STA [ dp + X ]

STA [ dp ] + Y

STA { X }

STA { X }+

X- register auto-increment : ( M )

A, X

X + 1

STX dp

Store X-register contents in memory

STX dp + Y

( M )

--------

STX !abs

STY dp

Store Y-register contents in memory

STY dp + X

( M )

--------

STY !abs

TAX

Transfer accumulator contents to X-register : X

N-----Z-

TAY

Transfer accumulator contents to Y-register : Y

N-----Z-

TSPX

Transfer stack-pointer contents to X-register : X

N-----Z-

TXA

Transfer X-register contents to accumulator: A

N-----Z-

TXSP

Transfer X-register contents to stack-pointer: sp

N-----Z-

TYA

Transfer Y-register contents to accumulator: A

N-----Z-

XAX

Exchange X-register contents with accumulator :X

--------

XAY

Exchange Y-register contents with accumulator :Y

--------

XMA dp

Exchange memory contents with accumulator

XMA dp+X

( M )

N-----Z-

XMA {X}

XYX

Exchange X-register contents with Y-register : X

--------

GMS81C71XX LCD MCU APPENDIX

vii

APR. 2001 Ver 2.01

16-BIT operation

Bit Manipulation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

ADDW dp

16-Bits add without Carry
YA

( YA ) ( dp +1 ) ( dp )

NV--H-ZC

CMPW dp

Compare YA contents with memory pair contents :
(YA)

(dp+1)(dp)

N-----ZC

DECW dp

Decrement memory pair
( dp+1)( dp)

( dp+1) ( dp) - 1

N-----Z-

INCW dp

Increment memory pair
( dp+1) ( dp)

( dp+1) ( dp ) + 1

N-----Z-

LDYA dp

Load YA
YA

( dp +1 ) ( dp )

N-----Z-

STYA dp

Store YA
( dp +1 ) ( dp )

--------

SUBW dp

16-Bits subtract without carry
YA

( YA ) - ( dp +1) ( dp)

NV--H-ZC

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

AND1 M.bit

Bit AND C-flag : C

( C )

( M .bit )

-------C

AND1B M.bit

Bit AND C-flag and NOT : C

( C )

~( M .bit )

-------C

BIT dp

Bit test A with memory :

MM----Z-

BIT !abs

( A )

( M ) , N

( M

) , V

( M

)

CLR1 dp.bit

Clear bit : ( M.bit )

"0"

--------

CLRA1 A.bit

Clear A bit : ( A.bit )

"0"

--------

CLRC

Clear C-flag : C

"0"

-------0

CLRG

Clear G-flag : G

"0"

--0-----

CLRV

Clear V-flag : V

"0"

-0--0---

EOR1 M.bit

Bit exclusive-OR C-flag : C

( C )

( M .bit )

-------C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

( C )

~(M .bit)

-------C

LDC M.bit

Load C-flag : C

( M .bit )

-------C

LDCB M.bit

Load C-flag with NOT : C

~( M .bit )

-------C

NOT1 M.bit

Bit complement : ( M .bit )

~( M .bit )

--------

OR1 M.bit

Bit OR C-flag : C

( C )

( M .bit )

-------C

OR1B M.bit

Bit OR C-flag and NOT : C

( C )

~( M .bit )

-------C

SET1 dp.bit

Set bit : ( M.bit )

"1"

--------

SETA1 A.bit

Set A bit : ( A.bit )

"1"

--------

SETC

Set C-flag : C

"1"

-------1

SETG

Set G-flag : G

"1"

--1-----

STC M.bit

Store C-flag : ( M .bit )

--------

TCLR1 !abs

Test and clear bits with A :
A - ( M ) , ( M )

( M )

~( A )

N-----Z-

TSET1 !abs

Test and set bits with A :
A - ( M ) , ( M )

( M )

( A )

N-----Z-

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

viii

Branch / Jump Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

BBC A.bit,rel

4/6

Branch if bit clear :

--------

BBC dp.bit,rel

5/7

if ( bit ) = 0 , then pc

( pc ) + rel

BBS A.bit,rel

4/6

Branch if bit set :

--------

BBS dp.bit,rel

5/7

if ( bit ) = 1 , then pc

( pc ) + rel

BCC rel

2/4

Branch if carry bit clear
if ( C ) = 0 , then pc

( pc ) + rel

--------

BCS rel

2/4

Branch if carry bit set
if ( C ) = 1 , then pc

( pc ) + rel

--------

BEQ rel

2/4

Branch if equal
if ( Z ) = 1 , then pc

( pc ) + rel

--------

BMI rel

2/4

Branch if minus
if ( N ) = 1 , then pc

( pc ) + rel

--------

BNE rel

2/4

Branch if not equal
if ( Z ) = 0 , then pc

( pc ) + rel

--------

BPL rel

2/4

Branch if plus
if ( N ) = 0 , then pc

( pc ) + rel

--------

BRA rel

Branch always
pc

( pc ) + rel

--------

BVC rel

2/4

Branch if overflow bit clear
if (V) = 0 , then pc

( pc) + rel

--------

BVS rel

2/4

Branch if overflow bit set
if (V) = 1 , then pc

( pc ) + rel

--------

CALL !abs

Subroutine call

CALL [dp]

M( sp)

( pc

), sp

sp - 1, M(sp)

(pc

), sp

sp - 1,

if !abs, pc

abs ; if [dp], pc

( dp ), pc

( dp+1 ) .

--------

CBNE dp,rel

5/7

Compare and branch if not equal :

--------

CBNE dp+X,rel

6/8

if ( A )

( M ) , then pc

( pc ) + rel.

DBNE dp,rel

5/7

Decrement and branch if not equal :

--------

DBNE Y,rel

4/6

if ( M )

0 , then pc

( pc ) + rel.

JMP !abs

Unconditional jump

JMP [!abs]

jump address

--------

JMP [dp]

PCALL upage

U-page call
M(sp)

( pc

), sp

sp - 1, M(sp)

( pc

sp - 1, pc

( upage ), pc

"0FF

" .

--------

TCALL n

Table call : (sp)

( pc

), sp

sp - 1,

M(sp)

( pc

),sp

sp - 1,

(Table vector L), pc

(Table vector H)

--------

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

Control Operation & Etc.

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

BRK

Software interrupt : B

"1", M(sp)

(pc

), sp

sp-1,

M(s)

(pc

), sp

sp - 1, M(sp)

(PSW), sp

sp -1,

( 0FFDE

) , pc

( 0FFDF

) .

---1-0--

Disable all interrupts : I

"0"

-----0--

Enable all interrupt : I

"1"

-----1--

NOP

No operation

--------

POP A

sp + 1, A

M( sp )

POP X

sp + 1, X

M( sp )

--------

POP Y

sp + 1, Y

M( sp )

POP PSW

sp + 1, PSW

M( sp )

restored

PUSH A

M( sp )

A , sp

sp - 1

PUSH X

M( sp )

X , sp

sp - 1

--------

PUSH Y

M( sp )

Y , sp

sp - 1

PUSH PSW

M( sp )

PSW , sp

sp - 1

RET

Return from subroutine
sp

sp +1, pc

M( sp ), sp

sp +1, pc

M( sp )

--------

RETI

Return from interrupt
sp

sp +1, PSW

M( sp ), sp

sp + 1,

M( sp ), sp

sp + 1, pc

M( sp )

restored

STOP

Stop mode ( halt CPU, stop oscillator )

--------

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

C. SOFTWARE EXAMPLE

;*****************************************************************************
; Title: GMS81C7016 (GMS800 Series) Demonstration Program *
; Company: Hynix semiconductor Inc. *
; Contents: LCD DISPLAY & DUAL THERMOMETER *
;*****************************************************************************
;
;******** DEFINE I/O PORT & FUNCTION REGISTER ADDRESS *********
;
R0 EQU 0C0H ;port R0 register
R1 EQU 0C1H ;port R1 register
R2 EQU 0C2H ;port R2 register
R3 EQU 0C3H ;port R3 register
R4 EQU 0C4H ;port R4 register
R5 EQU 0C5H ;port R5 register
;
R0DD EQU 0C8H ;port R0 data I/O direction register
R1DD EQU 0C9H ;port R1 data I/O direction register
R2DD EQU 0CAH ;port R2 data I/O direction register
R3DD EQU 0CBH ;port R3 data I/O direction register
R4DD EQU 0CCH ;port R4 data I/O direction register
R5DD EQU 0CDH ;port R5 data I/O direction register
;
R0PU EQU 0D0H ;port R0 Pull-up selection register
R1PU EQU 0D1H ;port R1 Pull-up selection register
R2PU EQU 0D2H ;port R2 Pull-up selection register
R3PU EQU 0D3H ;port R3 Pull-up selection register
;
R0CR EQU 0D4H ;port R0 Type selection register
R1CR EQU 0D5H ;port R1 Type selection register
R2CR EQU 0D6H ;port R2 Type selection register
R3CR EQU 0D7H ;port R3 Type selection register
;
IEDS EQU 0D8H ;External interrupt edge selection register
PMR EQU 0D9H ;Alternative port mode register
IENL EQU 0DAH ;int. enable register low
IENH EQU 0DBH ;int. enable register high
IRQL EQU 0DCH ;int. request flag register low
IRQH EQU 0DDH ;int. request flag register high

SLPR EQU 0DEH ;sleep mode register
WDTR EQU 0DFH ;Watchdog timer register

TM0 EQU 0E0H ;Timer 0 mode register
TDR0 EQU 0E1H ;Timer 0 data register
TM1 EQU 0E2H ;Timer 1 mode register
TDR1 EQU 0E3H ;Timer 1 data register
T1PPR EQU 0E3H ;PWM0 period register
T1PDR EQU 0E4H ;Timer 1 pulse duty register
PWM0HR EQU 0E5H ;PWM0 high register
TM2 EQU 0E6H ;Timer 2 mode register
TDR2 EQU 0E7H ;Timer 2 data register
TM3 EQU 0E8H ;Timer 3 mode register
TDR3 EQU 0E9H ;Timer 3 data register
T3PPR EQU 0E9H ;PWM1 period register
T3PDR EQU 0EAH ;Timer 3 pulse duty register
PWM1HR EQU 0EBH ;PWM1 high register

ADCM EQU 0ECH ;ADC mode register
ADR EQU 0EDH ;ADC result data register
WTMR EQU 0EFH ;Watch timer mode register

KSMR EQU 0F0H ;Key scan mode register
LCDM EQU 0F1H ;LCD mode register
LCDPM EQU 0F2H ;LCD port mode register
RPR EQU 0F3H ;RAM paging register
BITR EQU 0F4H ;Basic interval timer data register
CKCTLR EQU 0F4H ;Clock control register
SCMR EQU 0F5H ;System clock mode register
PFDR EQU 0FBH ;Power fail detector

BUR EQU 0FDH ;buzzer data register
SMR EQU 0FEH ;Serial mode register
SIOD EQU 0FFH ;Serial data buffer register
;
;*********** MACRO DEFINITION ************
;
R_SAVEMACRO ;Save Registers to Stacks

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

PUSH A
PUSH X
PUSH Y
ENDM
;
R_RSTRMACRO ;Restore Register from Stacks
POP Y
POP X
POP A
ENDM
;
;*********** CONSTANT DEFINITION ***********
;
;
;
;**************************************************************************
; RAM ALLOCATION *
;**************************************************************************
TEMP0 DS 1
TEMP1 DS 1
TEMP2 DS 1
FLAG1 DS 1

RPTEN EQU 1,FLAG1 ;SET RPTEN(REPEAT KEY ENABLE) AFTER 1 SEC.
KEYONF EQU 2,FLAG1 ;KEYSCAN
ACTKEY EQU 3,FLAG1 ;AT ONCE, KEY VALID
TOGMO3 EQU 4,FLAG1 ;MODE 3 (PORT TOGGLE)
DUAL_T EQU 5,FLAG1 ;INSIDE & OUTSIDE TEMP. DUAL DISPLAY
OUTSIDE EQU 6,FLAG1 ;INSIDE TEMP or OUTSIDE TEMP.

FLAG2 DS 1
F200MS EQU 0,FLAG2
F20MS EQU 1,FLAG2
F_1MIN EQU 2,FLAG2 ;WTIMER
LPM EQU 3,FLAG2 ;LEFT TIME PM FLAG
RPM EQU 4,FLAG2 ;RIGHT TIME PM FLAG

STATUS DS 1
RPTKEY EQU 7,STATUS
F_CLOCK EQU 6,STATUS
F_ON EQU 0,STATUS

DISPSIGN DS 1
DISPRAM DS 1 ;TEMP.
DISPRAM1 DS 4 ;LEFT TIME, RIGHT TIME

ONDO DS 2
LHOUR DS 1 ;LEFT WATCH COUNT
LMINUTE DS 1
RHOUR DS 1
RMINUTE DS 1 ;RIGHT WATCH COUNT BUF.
TIMESET DS 4 ;WATCH SET BUFFER
TSFLAG DS 1
TSLPM EQU 0,TSFLAG ;TIME SET LEFT PM
TSRPM EQU 1,TSFLAG ;TIME SET RIGHT PM
BLINKCNT DS 1 ;BLINK COUNTER 0~250 LOOP
;
NEWKY DS 1
OLDKY DS 1
PORTDT DS 1
KEYNM DS 1
KEYDT DS 1
TOTLKY DS 1
CHATFL DS 1
R0BUF DS 1

DGTCNT DS 1
MODE DS 1
SUBMODE DS 1
BSCTIME DS 1

TEMPCNT DS 1
HZCNT DS 1

PWMF DS 1
PERIOD EQU 0,PWMF
;
;**************************************************************************
; INTERRUPT VECTOR TABLE *
;**************************************************************************

GMS81C71XX LCD MCU APPENDIX

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xii

;
ORG 0FFE0H
DW NOT_USED ; Timer-3
DW NOT_USED ; Timer-2
DW WTIMER ; Watch Timer
DW INT_AD ; A/D CON.
DW NOT_USED ; Serial I/O
DW NOT_USED ; Not used
DW NOT_USED ; Not used
DW NOT_USED ; Int.2
DW TIMER1 ; Timer-1
DW TIMER0 ; Timer-0
DW INT1 ; Int.1
DW INT0 ; Int.0
DW NOT_USED; Watch Dog Timer
DW NOT_USED; BIT
DW INT_KEY ; Key Scan
DW RESET ; Reset
;
;**************************************************************************
; MAIN PROGRAM *
;**************************************************************************
;
ORG 0C000H ;Program Start Address
;ORG 0E000H ; 8K ROM VERSION
;
RESET: LDM WDTR,#0
LDM RPR,#1
;
CLRG
LDX #0
RAMCLR: LDA #0 ;RAM Clear(!0000H->!00BFH)
STA {X}+ ;M(X) <- A, then X <- X+1
CMPX #0C0H ;X = #0C0H ?
BNE RAMCLR
SETG
LDX #0
RAMCLR1: LDA #0 ;RAM Clear(!0100H->!011AH)
STA {X}+ ;M(X) <- A, then X <- X+1
CMPX #1BH ;X = #01BH ?
BNE RAMCLR1
CLRG
;
LDX #0FFH ;Stack Pointer Initial
TXSP ;SP. <- #0FFH
;
;******** USER RAM INITIALIZE **********
;
; LDM MODE,#4
; LDM SUBMODE,#1
SET1 LPM ;KST PM 12:00 JUST NOON
LDM LHOUR,#12H
LDM LMINUTE,#00H
LDM RHOUR,#03H ;UTC AM 03:00
LDM RMINUTE,#00H
SET1 OUTSIDE
SET1 F_ON ;POWER ON
;
;********** PORT INITIALIZE ************
;
LDM LCDPM,#0 ;SEG0~SEG23 are used
LDM R0,#0 ;I/O Port Data Clea
LDM R1,#0 ;I/O Port Data Clear
LDM R2,#0
LDM R3,#0
LDM R0DD,#1111_0001B ;R05,R06,R07: output for Keyscan
LDM R1DD,#0000_0000B
LDM R2DD,#0000_0000B ;R20~R23: input for keyscan
LDM R3DD,#0000_0100B
LDM R2PU,#0000_1111B ;R20~R23 pull-up active
;
;***** CONTROL REGISTER INITIALIZE *****
;
LDM CKCTLR,#0 ;WAKE UP TIME = 0.0625 sec
;(1/32768)*8*256 = 0.0625sec
LDM TDR0,#249 ;8us x (249+1) = 2ms
LDM TM0,#0000_1111B ;8BIT Timer,8us,Start Count-up
LDM TDR1,#249 ;2us x (249+1) = 500us
LDM TM1,#0000_1111B ;Timer1(8bit),32us,Start Count-up
LDM TM3,#1010_1011B

GMS81C71XX LCD MCU APPENDIX

xiii

APR. 2001 Ver 2.01

LDM T3PPR,#99
LDM T3PDR,#50
LDM PWM1HR,#00H
LDM PMR,#80H

LDM IRQH,#0 ;Clear All Interrupts Requeat Flags
LDM IRQL,#0
LDM IENL,#1111_1111B ;INT2,ADC,WT,T2,T3
LDM IENH,#1111_1111B ;BIT,WDT,INT0,INT1,T0,T1
LDM IEDS,#0001_0101B ;External Int. Falling edge select
LDM KSMR,#0000_0001B ;R10 KEY INTERRUPT
LDM WTMR,#48H ;ENABLE WT COUNTER, 2Hz, SELECT SUBCLOCK
LDM LCDM,#70H ;CLK=fsub/64, 1/4duty, internal Bias
LDM SCMR,#0 ;1/2, MAIN OSC.

EI ;Enable Interrupts
;
LOOP: BBC KEYONF,EXE1 ;TEST IF KEY IS PRESSED
CALL KEYDECODE
CLR1 KEYONF ;CLEAR KEY FLAG
EXE1:
BBC F20MS,NEXT1
CLR1 F20MS
;
;*****EVERY 20MS*****
;
CALL MODEEXE ;SETTING DISPLAY MEMORY
CALL MODE1EXE ;DURING CLOCK,
CALL MODE3EXE
CALL LCDDGT ;7-Segments Display
CALL LCDDOT ;Dot Display
CALL ADCEXE ;ADC execution
CALL LKEYSCAN

NEXT1:
BBC F200MS,ELOOP
CLR1 F200MS
;
;*****EVERY 200MS*****
;
CALL WIND

ELOOP:
BBS F_ON,EXE2
CLR1 R0.7 ;FOR WAKE-UP BY NEXT KEY
CLR1 R0.6 ;FOR WAKE-UP BY NEXT KEY
CLR1 R0.5 ;FOR WAKE-UP BY NEXT KEY
CLR1 R0.4 ;FOR WAKE-UP BY NEXT KEY
STOP
NOP
NOP
IF [F_1MIN]
CLR1 F_1MIN
CALL MODEEXE
CALL LCDDGT ;7-Segments Display
CALL LCDDOT ;Dot Display
ENDIF
CALL LKEYSCAN
EXE2:
JMP LOOP
;
;**************************************************************************
; TIMER0,INTERRUPT ROUTINE(2ms) *
;**************************************************************************
;
TIMER0: R_SAVE ;Save Registers to Stacks
CLRG
CALL MAKE10MS ;SET every 10ms
R_RSTR ;Restore Registers from Stacks
RETI
;
;**************************************************************************
; TIMER1 *
;**************************************************************************
;
TIMER1: R_SAVE
CLRG

R_RSTR

GMS81C71XX LCD MCU APPENDIX

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xiv

RETI
;
;**************************************************************************
; WATCH TIMER 4Hz *
;**************************************************************************
;
WTIMER: R_SAVE
CLRG
NOT1 R0.0

INC HZCNT
LDA HZCNT
CMP #120
BNE WT5
LDM HZCNT,#0
SET1 F_1MIN
CALL INC1MIN

WT5: R_RSTR
RETI
;
;**************************************************************************
; PORT INTERRUPT *
;**************************************************************************
;
INT_KEY: R_SAVE
CLRG
BBS CHATFL.7,IK8
BBS F_ON,IK8
LDX #3
LDM KSMR,#0 ;MAKE R10 TO BE NORMAL INPUT

WW: LDY #2 ;24ms wait
WW2: LDA #8
WW3: DEC A
BNE WW3
DEC Y
BNE WW2

LDA R1 ;READ R10
ROR A
BCS IK8
DEC X
BNE WW

LDM SCMR,#0 ;MAIN OSC.
SET1 F_ON
SET1 CHATFL.7
LDM OLDKY,#0CH
IK8: LDM KSMR,#1
R_RSTR
RETI
;
;**************************************************************************
; EXTERNAL INTERRUPT 0 *
;**************************************************************************
;
INT0: R_SAVE
CLRG
R_RSTR
RETI
;
;**************************************************************************
; EXTERNAL INTERRUPT 1 *
;**************************************************************************
;
INT1:
CLRG
RETI
;
;**************************************************************************
; ADC INTERRUPT *
;**************************************************************************
;
INT_AD:
RETI

;
;***********************************************************************

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

; Subject: LCDDGT
; LCD 7-SEG. DIGIT DISPLAY (TMEP,LTIME,RTIME *
;***********************************************************************
; Entry: DGTCNT (DIGIT COUNTER) *
; X (START ADDRESS) *
; Output: Output SEG_PORT (SEG0~SEG23) *
; Output COM_PORT (COM0~COM3) *
;***********************************************************************
; EXAMPLE) _ _ _ _ _ _ _ _ *
; DGTCNT=9 | | | | | | | | *
; X=LMINUTE |---| |---| |---| |---| *
; |___| |___| |___| |___| *
; LMINUTE+1 LMINUTE *
;***********************************************************************
;
LCDDGT: LDM DGTCNT,#9
LDX #DISPRAM
GOLCD: LDA {X}
PUSH X
if [DGTCNT.0] ;WHEN DIGIT IS EVEN NUMBER,
AND #0F0H ;WHEN DIGIT IS ODD NUMBER,
XCN
CALL LCDDSP ;HIGHER 4 NIBBLE IS DISPLAYED
POP X
else
AND #0FH ;LOWER 4 NIBBLE IS DISPLAYED
CALL LCDDSP
POP X
INC X
endif
DEC DGTCNT
BPL GOLCD
RET
;
;********* ONE DIGIT DISPLAY **********
;
LCDDSP:
TAY
;
;****** ZERO SURPRESS TO BLANK ******
;
BNE GOCONT ;IF A=0 THEN SURPRESS
LDA DGTCNT
CMP #9
BEQ BLNK
CMP #7
BEQ BLNK
CMP #3
BEQ BLNK
BRA GOCONT
BLNK: LDY #0AH
;
GOCONT: LDA !FONT+Y ;LOAD FONT DATA
STA TEMP0 ;STORE 7-SEG FONT
LDM TEMP2,#7 ;SHIFT COUNTER INITIALIZE
LDY DGTCNT ;GET OFFSET LCD ADDRESS FOR DGTCNT
LDA #14
MUL
TAY
DPL1: LDA !FONTD0+Y ;GET LCD RAM ADDRESS
TAX ;STORE LCD RAM ADDRESS
INC Y ;INCREMENT POINTER
LDA !FONTD0+Y ;GET BIT POSITION
STA TEMP1 ;STORE BIT POSITION
ROR TEMP0
BCS DPL3
LDA #0FFH ;CLEAR BIT DISPLAY RAM
ROL A
DEC TEMP1
BPL $-3
SETG
AND {X}
BRA DPL5
DPL3: LDA #00H ;SET BIT DISPLAY RAM
ROL A
DEC TEMP1
BPL $-3
SETG
OR {X}
DPL5: STA {X}

GMS81C71XX LCD MCU APPENDIX

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xvi

CLRG
INC Y
DBNE TEMP2,DPL1
RET

FONTD0 DB 13H,1H,13H,2H,13H,0H,13H,3H,0CH,3H,0CH,2H,0CH,0H ;RMINUTE0
FONTD1 DB 12H,1H,12H,2H,12H,0H,12H,3H,05H,3H,05H,2H,05H,0H ;RMINUTE1
FONTD2 DB 06H,1H,06H,2H,06H,0H,06H,3H,01H,3H,01H,2H,01H,0H ;RHOUR0
FONTD3 DB 80H,0H,01H,1H,01H,1H,80H,0H,80H,0H,80H,0H,80H,0H ;RHOUR1
FONTD4 DB 02H,1H,02H,2H,02H,0H,02H,3H,15H,3H,15H,2H,15H,0H ;LMINUTE0
FONTD5 DB 09H,1H,15H,1H,09H,0H,09H,3H,16H,0H,16H,1H,09H,2H ;LMINUTE1
FONTD6 DB 14H,1H,14H,2H,14H,0H,14H,3H,00H,3H,00H,2H,00H,0H ;LHOUR0
FONTD7 DB 80H,0H,08H,2H,08H,2H,80H,0H,80H,0H,80H,0H,80H,0H ;LHOUR1
FONTD8 DB 0BH,2H,0BH,0H,0BH,3H,0BH,1H,17H,1H,17H,0H,17H,3H ;ONDO0
FONTD9 DB 0FH,2H,0FH,0H,0FH,3H,0FH,1H,10H,1H,10H,0H,10H,3H ;ONDO1
;
;**************************************************************************
; 7-SEGMENT PATTERN DATA *
; _a_ *
; f | g |b *
; |---| *
; e |___|c *
; d .h *
;**************************************************************************

; Segment: hgfe dcba To be displayed Digit Number

FONT DB 0011_1111B ; 0 "0"
DB 0000_0110B ; 1
DB 0101_1011B ; 2
DB 0100_1111B ; 3
DB 0110_0110B ; 4
DB 0110_1101B ; 5
DB 0111_1101B ; 6
DB 0000_0111B ; 7
DB 0111_1111B ; 8 "8"
DB 0110_1111B ; 9 "9"
DB 0000_0000B ; A "BLANK"
DB 0100_0000B ; B "BAR"

_LCOLON EQU 2,116H
_RCOLON EQU 2,10EH
_ONDO EQU 2,107H
_C EQU 0,111H
_RAM EQU 1,10EH
_RPM EQU 0,10EH
_LAM EQU 1,108H
_LPM EQU 3,108H
_OUTSIDE EQU 1,104H
_INSIDE EQU 0,107H
_S1 EQU 2,10AH
_SNOW EQU 3,10AH
_SAVE EQU 3,104H
;
LCDDOT: SETC
STC _LCOLON
STC _S1
STC _ONDO
STC _C

LDCB F_ON
STC _SAVE
LDCB DUAL_T
STC _RCOLON

LDC LPM
STC _LPM
LDCB LPM
STC _LAM

IF [DUAL_T]==0
ldc RPM ;AM,PM SETTING
stc _RPM
ldcb RPM
stc _RAM
ELSE
LDCB DUAL_T ;TURN OFF THE AM, PM
STC _RPM

GMS81C71XX LCD MCU APPENDIX

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APR. 2001 Ver 2.01

STC _RAM
ENDIF

LDC OUTSIDE
STC _OUTSIDE
LDCB OUTSIDE
STC _INSIDE

RET
;
;***********************************************
; Subject: ANY EXECUTION *
;***********************************************
; DESCRIPTION: EVERY 20MS *
; *
;***********************************************
;
MODEEXE: IF [OUTSIDE]
LDX #0
ELSE
LDX #1
ENDIF

LDA ONDO+X ;COPY ONDO DATA TO DISPRAM
STA DISPRAM
LDA SIGN+X
STA DISPSIGN

IF [DISPSIGN.0] ;IF MINUS ONDO, THEN "-" DISPLAY
IF [DISPRAM] < #10
LDA #0B0H
OR DISPRAM
STA DISPRAM
CLRC
STC _SNOW
ELSE
SETC
STC _SNOW
ENDIF
ELSE
CLRC
STC _SNOW
ENDIF

LDX #3 ;MOVE TIME_BUF. TO DISP_BUF.
MX1: LDA LHOUR+X
STA DISPRAM1+X
DEC X
BPL MX1

BBC DUAL_T,MX2 ;IF SINGLE TEMP. MODE, SKIP
LDA #0AAH ;MAKE ERASE DISP BUF. WITCH
STA DISPRAM1+2 ;WILL BE DISPLAYED TEMP.

IF [OUTSIDE] ;IF DUAL TEMP. MODE
LDX #1 ;IF MAIN=OUSIDE, THEN SELECT INSIDE
ELSE
LDX #0 ;IF MAIN=INSIDE, THEN SELECT OUTSIDE
ENDIF

LDA ONDO+X
STA DISPRAM1+3

LDA SIGN+X ;GET BIT0 OF SIGN
ROR A ;COPY SIGN TO CARRY

IF C ;IF MINUS ONDO, THEN "-" DISPLAY
IF [DISPRAM1+3] < #10
LDA #0B0H ;EXE) BB-4
OR DISPRAM1+3
STA DISPRAM1+3
ELSE
LDM DISPRAM1+2,#0ABH ;EXE) B-14
ENDIF
ELSE
IF [DISPRAM1+3] < #10
LDA #0A0H ;EXE) BB-4
OR DISPRAM1+3
STA DISPRAM1+3
ENDIF

GMS81C71XX LCD MCU APPENDIX

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xviii

ENDIF

MX2: RET

;
;***********************************************
; Subject: MODE 1 EXECUTION *
;***********************************************
; DESCRIPTION: CLOCK SET *
; *
;***********************************************
;
MODE1EXE: LDA MODE
AND #0F0H
CMP #10H ;IF MODE=1x
BNE MB3
LDX #3
MB1: LDA TIMESET+X ;TIMESET BUF. COPIED TO DISP BUF.
STA DISPRAM1+X ;4BYTE & 2 BIT
DEC X
BPL MB1
LDC TSLPM
STC LPM
LDC TSRPM
STC RPM
;
LDA MODE
CMP #10H ;TEST IF LEFT TIME SET MODE ?
BEQ MO10
CMP #11H
BEQ MO11 ;TEST IF RIGHT TIME SET MODE ?
BRA MB3

MO10: LDA BLINKCNT
CMP #125 ;IF LESS THAN 124, OFF
BCS MB3
LDA #0AAH
STA DISPRAM1
STA DISPRAM1+1
MB3: RET

MO11: LDA BLINKCNT
CMP #125 ;IF LESS THAN 124, OFF
BCS MB3
LDA #0AAH
STA DISPRAM1+2
STA DISPRAM1+3
BRA MB3
;
;***********************************************
; Subject: MODE 3 EXECUTION *
;***********************************************
; DESCRIPTION: All pin goes low and high *
; repeatly every 20ms, rectangle wave output *
; *
;***********************************************
;
MODE3EXE: LDA MODE
CMP #3
BNE MO2
LDA SUBMODE
DEC A ;BECAUSE INITIAL NO.=1
ROL A ;EIGHT TIMES
ROL A
ROL A
NOT1 TOGMO3
BBC TOGMO3,MO1
CLRC
ADC #4 ;ADD OFFSET
MO1: TAY
LDA !PPORT+Y
AND #0001_1111B
OR R0BUF
STA R0BUF
STA R0
LDA !PPORT+1+Y
STA R1
LDA !PPORT+2+Y
STA R2

GMS81C71XX LCD MCU APPENDIX

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LDA !PPORT+3+Y
STA R3
MO2: RET

PPORT DB 00H,00H,00H,00H
DB 00H,00H,00H,00H

DB 0FFH,0FFH,0FFH,0FFH
DB 0FFH,0FFH,0FFH,0FFH

DB 00H,00H,00H,00H
DB 0FFH,0FFH,0FFH,0FFH

DB 00H,00H,00H,00H
DB 0FFH,00H,0FFH,00H

DB 00H,0FFH,00H,0FFH
DB 00H,00H,00H,00H

DB 00H,0FFH,00H,0FFH
DB 0FFH,00H,0FFH,00H

DB 55H,55H,55H,55H
DB 0AAH,0AAH,0AAH,0AAH
;
;***********************************************
; Subject: Set falg at every 20ms *
;***********************************************
;
MAKE10MS: SETC
LDA #0
ADC BSCTIME
DAA
STA BSCTIME
BNE $+4
SET1 F200MS ;SET F200MS EVERY 200ms
AND #0FH
BNE $+4
SET1 F20MS ;SET F20MS EVERY 20ms
;
INC BLINKCNT ;USED IN MODE0(CLOCK SET)
LDA BLINKCNT
CMP #250
BNE MZ1
LDM BLINKCNT,#0
MZ1: RET
;
;***********************************************
; Subject: Analog to Digital Conversion *
;***********************************************
; It is called in main routine every 20ms
ADCNT DS 2
ADR_AVR DS 2
ADTTL DS 4
ADFLAG DS 1
AD_CH EQU 0,ADFLAG
SIGN DS 2
DIVISOR EQU 250
;
; :-------: :-------:
; :ADR_AVR: :ADR_AVR:
; : : : :
; :OUTSIDE: :INSIDE :
; :CH4 : :CH5 :
; :-------: :-------:
;
ADCEXE: IF [AD_CH]== 0
LDM ADCM,#52H ;AD START CH4
LDX #0 ;SET TO 0 INDEX POINTER
ELSE
LDM ADCM,#56H ;AD START CH5
LDX #1 ;SET TO 1 INDEX POINTER
ENDIF

LDY #20 ;WAIT ADC END
ADWAIT: DEC Y
BBS ADCM.0,GOGET
CMPY #0
BNE ADWAIT

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

GOGET: CLRC ;UP8 LO8
LDA ADR ;ADTTL2|ADTTL0 = CH4 DATA
ADC ADTTL+X ;ADTTL3|ADTTL1 = CH5 DATA
STA ADTTL+X
LDA #0
ADC ADTTL+2+X
STA ADTTL+2+X
;
INC ADCNT+X
LDA ADCNT+X
IF A == #DIVISOR ;GET AVERAGE VALUE
LDA #0
STA ADCNT+X
LDY ADTTL+2+X
LDA ADTTL+X
PUSH X
LDX #DIVISOR ;DIVIDE BY DIVISOR
DIV
POP X
STA ADR_AVR+X
LDA #0 ;CLEAR SUM BUF.
STA ADTTL+X
STA ADTTL+2+X

LDA ADR_AVR+X
IF A < #65 ;IGNORE BELOW 65
LDA #65
ENDIF
IF A > #240 ;MAX. 240
LDA #240
ENDIF
CMP #181 ;MAKE SIGN
ROL SIGN+X ;COPY TO MINUS OR PLUS

SETC
SBC #65
TAY
LDA !ADTABLE1+Y
STA ONDO+X
ENDIF

NOT1 AD_CH
ADCQUIT: RET
;
;
ADTABLE DB 50H,49H,49H,48H,48H,47H ; 65~ 70 65->+50'C
DB 47H,46H,46H,45H,45H,44H,44H,43H,43H,42H ; 71~ 80
DB 41H,41H,40H,40H,40H,39H,39H,38H,38H,37H ; 81~ 90 83->+40'C
DB 37H,36H,36H,35H,35H,34H,34H,33H,33H,32H ; 91~100
DB 32H,31H,31H,30H,30H,30H,29H,29H,28H,28H ;101~110 105->+30'C
DB 27H,27H,26H,26H,25H,25H,24H,24H,24H,23H ;111~120
DB 23H,22H,22H,22H,21H,21H,20H,20H,20H,20H ;121~130 129->+20'C
DB 19H,19H,18H,18H,17H,17H,16H,16H,15H,15H ;131~140
DB 15H,14H,14H,14H,13H,13H,13H,12H,12H,12H ;141~150
DB 11H,11H,11H,10H,10H,10H,09H,09H,09H,08H ;151~160 154->+10'C
DB 08H,07H,07H,07H,06H,05H,05H,04H,04H,04H ;161~170
DB 03H,03H,02H,02H,01H,01H,00H,00H,00H,01H ;171~180 178-> 0'C
DB 01H,02H,02H,03H,03H,04H,04H,05H,05H,06H ;181~190
DB 06H,07H,07H,08H,08H,09H,09H,10H,10H,11H ;191~200 199->-10'C
DB 11H,12H,12H,13H,13H,14H,15H,15H,16H,17H ;201~210
DB 17H,18H,18H,19H,19H,20H,20H,21H,21H,22H ;211~220 217->-20'C
DB 23H,23H,24H,24H,25H,25H,26H,27H,28H,29H ;221~230
DB 30H,31H,32H,33H,34H,35H,36H,37H,38H,39H ;231~240 231->-30'C
DB 40H,41H,42H
ADTABLE1 DB 50H,50H,50H,49H,49H,48H ; 65~ 70 65->+50'C
DB 48H,47H,47H,46H,46H,45H,45H,44H,44H,43H ; 71~ 80
DB 43H,42H,41H,40H,39H,38H,37H,36H,35H,34H ; 81~ 90 83->+40'C
DB 35H,35H,34H,34H,33H,33H,32H,32H,31H,31H ; 91~100
DB 30H,30H,29H,29H,28H,28H,27H,27H,26H,26H ;101~110 105->+30'C
DB 26H,25H,25H,25H,24H,24H,24H,23H,23H,23H ;111~120
DB 22H,22H,22H,21H,21H,21H,20H,20H,20H,20H ;121~130 129->+20'C
DB 19H,18H,18H,18H,17H,17H,17H,16H,16H,16H ;131~140
DB 15H,15H,15H,14H,14H,14H,13H,13H,13H,12H ;141~150
DB 12H,11H,11H,10H,10H,09H,09H,09H,08H,08H ;151~160 154->+10'C
DB 07H,07H,06H,06H,05H,05H,04H,04H,04H,03H ;161~170
DB 03H,03H,02H,02H,02H,01H,01H,01H,00H,00H ;171~180 178-> 0'C
DB 01H,01h,02H,02H,03H,03H,04H,04H,05H,05H ;181~190
DB 06H,06H,07H,07H,08H,08H,09H,09H,10H,10H ;191~200 199->-10'C
DB 11H,11H,12H,12H,13H,13H,14H,15H,15H,16H ;201~210
DB 16H,16H,17H,18H,18H,19H,19H,20H,20H,21H ;211~220 217->-20'C

GMS81C71XX LCD MCU APPENDIX

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DB 21H,22H,23H,23H,24H,24H,25H,25H,26H,27H ;221~230
DB 28H,29H,30H,31H,32H,33H,34H,35H,36H,37H ;231~240 231->-30'C
DB 38H,39H,40H
;
;***********************************************
; Subject: KEYDECODE *
;***********************************************
; *
;***********************************************
;
REPEAT EQU #1000_0000B
CLOCK EQU #0100_0000B
PWRON EQU #0000_0001B

KEYDECODE: LDA KEYDT
LDY #3
MUL
TAY
LDA !KEY+Y
STA TEMP0
LDA !KEY+1+Y
STA TEMP1
LDA !KEY+2+Y
STA TEMP2
CALL CONDICHK
BCC QUIT
JMP [TEMP0]
;
KEY: DW NOKEY ;0
DB 0
DW NOKEY ;1
DB 0
DW NOKEY ;2
DB 0
DW NOKEY ;3
DB 0
DW NOKEY ;4
DB 0
DW NOKEY ;5
DB 0
DW NOKEY ;6
DB 0
DW DOWNKEY ;7
DB PWRON+REPEAT
DW NOKEY ;8
DB 0
DW DUALKEY ;9
DB PWRON
DW SWAPKEY ;A
DB PWRON
DW NOKEY ;B
DB 0
DW POWERKEY ;C
DB PWRON
DW CLOCKKEY ;D
DB PWRON+CLOCK
DW HOURKEY ;E
DB PWRON+REPEAT+CLOCK
DW MINUTEKEY ;F
DB PWRON+REPEAT+CLOCK
DW NOKEY ;10
DB 0
DW UPKEY ;11
DB PWRON+REPEAT
DW NOKEY ;12
DB 0
QUIT:
NOKEY: RET

CONDICHK: LDA TEMP2
OR STATUS
SBC TEMP2
BEQ CDC9
BCS CDC10
CDC9: SETC ;PASS
RET
CDC10: CLRC ;SKIP
RET
;

GMS81C71XX LCD MCU APPENDIX

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xxii

;***********************************************************
; DISPLAY SWAP KEY (TEMP. DISPLAY SWAP) *
;***********************************************************
;
SWAPKEY: NOT1 OUTSIDE
RET
;
;***********************************************************
; DUAL KEY *
;***********************************************************
;
DUALKEY: NOT1 DUAL_T
RET
;
;***********************************************************
; POWER KEY *
;***********************************************************
;
POWERKEY: CLR1 F_ON
IF [F_ON]
ELSE
LDM SCMR,#2
CLR1 DUAL_T
LDM MODE,#0
SET1 F20MS
ENDIF
RET
;
;***********************************************************
; CLOCK KEY *
;***********************************************************
;
CLOCKKEY: SET1 F_CLOCK
LDM BLINKCNT,#0
LDA MODE ; 10->11
CMP #10H ; 11->00
BNE CL1 ; ETC. -> 10
LDM MODE,#11H
BRA QUIT
CL1: CMP #11H
BNE CL2
LDM MODE,#0
CLR1 F_CLOCK
CALL SETTO_CNT
LDC TSLPM
STC LPM
LDC TSRPM
STC RPM
LDM HZCNT,#0
CLR1 F_1MIN
BRA CLQ

CL2: LDM MODE,#10H
CLR1 DUAL_T
CALL CNTTO_SET
LDC LPM
STC TSLPM
LDC RPM
STC TSRPM
CLQ: RET
;
SETTO_CNT: LDX #3
CL11: LDA TIMESET+X
STA LHOUR+X
DEC X
BPL CL11
RET
;
CNTTO_SET: LDX #3
CL3: LDA LHOUR+X
STA TIMESET+X
DEC X
BPL CL3
RET
;
;***********************************************************
; HOUR/MINUTE KEY *
;***********************************************************
;
HOURKEY: LDA MODE

GMS81C71XX LCD MCU APPENDIX

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APR. 2001 Ver 2.01

AND #0F0H
CMP #10H
BNE HO1
LDM BLINKCNT,#125
LDA MODE
CMP #10H
BNE HO2
SETC ;IF MODE=10H, THEN LEFT TIME SET
LDA #0 ;INC. LEFT HOUR 1UP
ADC TIMESET
DAA
IF A==#12H
NOT1 TSLPM ;ADJUST AM,PM FLAG
ENDIF
IF A==#13H
LDA #1
ENDIF
STA TIMESET
HO1: RET
HO2: CMP #11H
BNE HO1
SETC ;INC. RIGHT HOUR 1UP
LDA #0
ADC TIMESET+2
DAA
IF A==#12H
NOT1 TSRPM ;ADJUST AM,PM FLAG
ENDIF
IF A==#13H
LDA #1
ENDIF
STA TIMESET+2
BRA HO1

MINUTEKEY: LDA MODE
AND #0F0H
CMP #10H
BNE MT3

LDM BLINKCNT,#125
LDX #3
LDA MODE
CMP #10H
BNE MT1
LDX #1
MT1: SETC
LDA #0
ADC TIMESET+X
DAA
CMP #60H
BNE MT2
LDA #0
MT2: STA TIMESET+X
MT3: RET
;
;***********************************************
; UP /DOWN KEY *
;***********************************************
;
UPKEY: BBS PERIOD,PRU
LDA PWM1HR
AND #0000_0011B
CMP #3
BNE UPK1
LDA T3PDR
CMP #0FFH
BNE UPK1
UPK0: RET

UPK1: INC T3PDR
BNE UPK0
INC PWM1HR
BRA UPK0
PRU:

DOWNKEY: BBS PERIOD,PRD
LDA PWM1HR
AND #0000_0011B
CMP #0

GMS81C71XX LCD MCU APPENDIX

APR. 2001 Ver 2.01

xxiv

BNE DNK1
LDA T3PDR
CMP #0
BEQ UPK0
DNK1: DEC T3PDR
LDA T3PDR
CMP #0FFH
BNE DNK2
DEC PWM1HR
DNK2: RET

PRD:

PWMMODE:
;
;***********************************************************
; PLUS KEY *
; *
; When MODE=3, PRESS PULS KEY, SUBMODE IS INCRESED *
; When MODE=3, PRESS MINUS KEY, SUBMODE IS DECRESED *
; *
;***********************************************************
;
;
;***********************************************
; Subject: KEYSCAN *
;***********************************************
; STROBE OUT: R05,R06,R07 *
; READ PORT : R20,R21,R22,R23 *
; *
;***********************************************
;
LKEYSCAN: BBS KEYONF,KS7
LDM KEYNM,#1
LDM TOTLKY,#0
LDM NEWKY,#0
LDY #3 ;INITIALIZE STROBE LINE
KS1:
CMPY #3
BNE $+4
CLR1 R0.4 ;OUTPUT STROBE SIGNAL
CMPY #2
BNE $+4
CLR1 R0.5 ;OUTPUT STROBE SIGNAL
CMPY #1
BNE $+4
CLR1 R0.6 ;OUTPUT STROBE SIGNAL
CMPY #0
BNE $+4
CLR1 R0.7 ;OUTPUT STROBE SIGNAL
;
NOP
NOP
LDA R2
STA PORTDT ;READ KEY IN PORT
AND #0FH
CMP #0FH ;IF KEY IS PRESSED ?
BNE KS2
CLRC ;KEYNM + 4 -> KEYNM
LDA #4
ADC KEYNM
STA KEYNM
BRA KS5
;
KS2: LDX #3 ;INITIALIZE SHIFT COUNTER
KS3: ROR PORTDT
BCS KS4
INC TOTLKY ;IF TOTLKY IS ABOVE 2, THEN QUIT
LDA TOTLKY
CMP #20
BEQ KS7
LDA KEYNM ;KEYNM -> NEWKY
STA NEWKY
KS4: INC KEYNM
DEC X
BPL KS3
KS5:
SET1 R0.4
SET1 R0.5

GMS81C71XX LCD MCU APPENDIX

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APR. 2001 Ver 2.01

SET1 R0.6
SET1 R0.7
DEC Y ;TEST NEXT LINE
BPL KS1
LDA NEWKY
CMP #0 ;WHEN NO KEY IS PRESSED,
BNE KS8 ;INITIALIZE NEWKY,OLDKY,CHATFL
KS6: LDA NEWKY
STA OLDKY
LDM CHATFL,#0
CLR1 RPTKEY
CLR1 ACTKEY
CLR1 RPTEN
KS7: RET
KS8: LDA NEWKY
CMP OLDKY
BNE KS6
BBS CHATFL.7,KS10
LDA CHATFL
AND #0111_1111B
CMP #5
BCC KS9
LDA NEWKY
STA KEYDT
SET1 ACTKEY
KS81: LDM CHATFL,#80H ;SET1 CHATFL.7 & SET TO 0
SET1 KEYONF
BRA KS7
KS9: INC CHATFL
BRA KS7

KS10: LDA CHATFL ;REPEAT KEY
AND #0111_1111B
BBS RPTEN,KS11
CMP #25
BCC KS9
SET1 RPTEN
BRA KS81
KS11: CMP #3
BCC KS9
BBC ACTKEY,KS7
SET1 RPTKEY
BRA KS81
;
;***********************************************
; Subject: Increase 1 minute *
;***********************************************
;
INC1MIN: LDX #LMINUTE
CALL MIN1UP
LDX #RMINUTE
CALL MIN1UP
RET
;
MIN1UP: SETC
LDA #0 ; LMINUTE <- LMINUTE + 1
ADC {X}
DAA
IF A ==#60H
SETC
LDA #0
ENDIF
STA {X}
BCC INC1
DEC X
LDA #0
ADC {X}
DAA
IF A==#12H
IF X==#LHOUR
NOT1 LPM
ELSE
NOT1 RPM
ENDIF
ENDIF
IF A==#13H
LDA #1
ENDIF
STA {X}
INC1: RET

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81C7008K

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS81C7008K