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Электронный компонент: GMS90C320Q50

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HYNIX SEMICONDUCTOR INC.
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS90C320
User's Manual (Ver. 1.2)
Version 1.2
Published by
MCU Application Team
Copy right



2001 Hynix semiconductor, All right reserved.
Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Repre-
sentatives listed at address directory.
Hynix semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconductor is in no
way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
REVISION HISTORY
VERSION 1.2 (Oct. 2000) This book
Correct the pin number of 44-MQFP package type on page 6.
VERSION 1.1 (Oct. 1999) Before version
GMS90C320
OCT. 2000 Ver 1.2
Device Naming Structure
H(G)MS90X320
Frequency
Package Type
Blank: 24MHz
Blank:
PL:
Q:
40PDIP
44PLCC
44MQFP
Enhanced ROM-less version
Operating Voltage
C:
L:
Normal voltage
Low voltage
H
y
ni
x
s
e
m
i
c
on
du
ctor
M
C
U
XXXX
MCU
S
er
ies
40:
40MHz
50:
50MHz
GMS90C320
OCT. 2000 Ver 1.2
GMS90C320 ordering information
Operating
Voltage (V)
Device Name
ROM size
(bytes)
RAM size
(bytes)
Operating max.
Frequency (MHz)
Package Type
4.25~5.5
GMS90C320 40
GMS90C320 PL40
GMS90C320 Q40
ROM-less
256
40
40PDIP
44PLCC
44MQFP
GMS90C320 50
GMS90C320 PL50
GMS90C320 Q50
ROM-less
256
50
40PDIP
44PLCC
44MQFP
2.7~5.5
GMS90L320
GMS90L320 PL
GMS90L320 Q
ROM-less
256
24
40PDIP
44PLCC
44MQFP
GMS90C320
OCT. 2000 Ver 1.2
1
GMS90C320/L320
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
ROM-less Version for 90C52
Features
Fully compatible to standard MCS-51 microcontroller
Versions for 40/50 MHz operating frequency
Low voltage version for 24MHz operating frequency
256 bytes of on-chip data RAM
64K external program memory space
64K external data memory space
Four 8-bit ports
Three 16-bit Timers/Counters (Timer 2 with up/down counter feature)
USART
Six interrupt sources, two priority levels
Power saving Idle and power down mode
2.7Volt low voltage version available
P-DIP-40, P-LCC-44, P-MQFP-44 package
The GMS90C320 described in this document is compatible with the standard 80C32 can be used for all present standard
80C32 applications.
Operating Voltage (V)
Device Name
ROM
RAM
Operating
Frequency (MHz)
4.25~5.5
GMS90C320
ROM-less
256



8bit
40/50
2.7~5.5
GMS90L320
ROM-less
256



8bit
24
RAM
256 x 8
T0
T1
ROM-less
CPU
8-BIT
USART
PORT0
PORT3
PORT1
PORT2
T2
I/O
I/O
I/O
I/O
GMS90C320
2
OCT. 2000 Ver 1.2
44-PLCC Pin Configuration
(top view)
(P-LCC-44)
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
N.C.
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1
.4
P1
.3
P1
.2
P1
.1
/
T
2
E
X
P1
.0
/
T
2
N.C.
V
CC
P0
.0
/
A
D0
P0
.1
/
A
D1
P0
.2
/
A
D2
P0
.3
/
A
D3
WR
/P3
.
6
RD
/P3
.
7
XTA
L
2
XTA
L
1
V
SS
N.C.
P2
.0
/A8
P2
.1
/A9
P2
.2
/A
1
0
P2
.3
/A
1
1
P2
.4
/A
1
2
P1.5
P1.6
P1.7
RESET
RxD/P3.0
N.C.
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
GMS90C320
OCT. 2000 Ver 1.2
3
40-PDIP Pin Configuration
(top view)
(P-DIP-40)
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE
PSEN
P1.6
P1.7
RESET
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
1
2
3
4
5
6
XTAL2
XTAL1
V
S S
18
19
20
V
C C
40
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
28
27
26
25
24
23
22
21
GMS90C320
4
OCT. 2000 Ver 1.2
44-PLCC Pin Configuration
(top view)
(P-MQFP-44)
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
N.C.
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1
.
4
P1
.3
P1
.
2
P
1
.1
/T
2
E
X
P
1
.0
/T
2
N.
C
.
V
CC
P
0
.0
/A
D
0
P
0
.1
/A
D
1
P
0
.2
/A
D
2
P
0
.3
/A
D
3
WR
/P
3
.
6
RD
/P
3
.
7
XT
AL
2
XT
AL
1
V
SS
N.
C
.
P
2
.0
/A
8
P
2
.1
/A
9
P2
.2
/
A
1
0
P2
.3
/
A
1
1
P2
.4
/
A
1
2
P1.5
P1.6
P1.7
RESET
RxD/P3.0
N.C.
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
GMS90C320
OCT. 2000 Ver 1.2
5
Logic Symbol
Port 0
XTAL1
XTAL2
RESET
EA
ALE
PSEN
8-bit Digital I/O
Port 1
8-bit Digital I/O
Port 2
8-bit Digital I/O
Port 3
8-bit Digital I/O
V
C C
V
S S
GMS90C320
6
OCT. 2000 Ver 1.2
Pin Definitions and functions
Symbol
Pin Number
Input/
Output
Function
P-LCC-44
P-DIP-40
P-MQFP-
44
P1.0-P1.7
2-9
1-8
40-44,
1-3
I/O
Port1
is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-up
resistors and can be used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of the pulls-ups
(I
IL
, in the DC characteristics). Pins P1.0 and P1.1 also. Port 1
also receives the low-order address byte during program memory
verification. Port1 also serves alternate functions of Timer 2.
2
3
1
2
40
41
P1.0/T2: Timer/counter 2 external count input
P1.1/T2EX: Timer/counter 2 trigger input
P3.0-P3.7
11,13-
19
10-17
5, 7-
13
I/O
Port 3
is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state they can be used as inputs. As inputs,
port 3 pins being externally pulled low will source current (I
IL
, in
the DC characteristics) because of internal pulls-up resistors. Port
3 also serves the special features of the 80C51 family, as listed
below.
11
10
5
P3.0/RxD
receiver data input (asynchronous) or data input
output (synchronous) of the serial interface 0
13
11
7
P3.1 / TxD
transmitter data output (asynchronous) or clock
output (synchronous) of the serial interface 0
14
12
8
P3.2 / INT0
interrupt 0 input / timer 0 gate control
15
13
9
P3.3 / INT1
interrupt 1 input / timer 1 gate control
16
14
10
P3.4 / T0
counter 0 input
17
15
11
P3.5 / T1
counter 1 input
18
16
12
P3.6 / WR
the write control signal latches the data byte from
port 0 into the external data memory
19
17
13
P3.7 / RD
the read control signal enables the external data
memory to port 0
XTAL2
20
18
14
O
XTAL2
Output of the inverting oscillator amplifier
XTAL1
21
19
15
I
XTAL1
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
To drive the device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are no require-
ments on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is divided down by a divide-
by-two flip-flop. Minimum and maximum high and low times as
well as rise fall times specified in the AC characteristics must be
observed.
GMS90C320
OCT. 2000 Ver 1.2
7
P2.0-P2.7
24-31
21-28
18-25
I/O
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal
pull-up resistors and can be used as inputs. As inputs, port 2 pins
that are externally pulled low will source current because of the
pulls-ups (I
IL
, in the DC characteristics). Port 2 emits the high-
order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it uses strong
internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @Ri), port 2 emits
the contents of the P2 special function register.
PSEN
32
29
26
O
The Program Store Enable
The read strobe to external program memory when the device is
executing code from the external program memory. PSEN is acti-
vated twice each machine cycle, except that two PSEN activation
are skipped during each access to external data memory. PSEN
is not activated during fetches from internal program memory.
RESET
10
9
4
I
RESET
A high level on this pin for two machine cycles while the oscillator
is running resets the device. An internal diffused resistor to V
S S
permits power-on reset using only an external capacitor to V
C C
.
ALE
33
30
27
O
The Address Latch Enable
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted
at a constant rate of 1/6 the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory.
EA
35
31
29
I
External Access Enable
EA must be external held low to enable the device to fetch code
from external program memory locations 0000
H
to FFFF
H
. If EA is
held high, the device executes from internal program memory
unless the program counter contains an address greater than its
internal memory size.
P0.0-P0.7
43-36
39-32
37-30
I/O
Port 0
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high-impedance
inputs. Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s.
Port 0 also outputs the code bytes during program verification in
the GMS97C5x. External pull-up resistors are required during
program verification.
V
S S
22
20
16
-
Circuit ground potential
V
C C
44
40
38
-
Supply terminal for all operating modes
N.C.
1,12,
23,34
-
6,17,
28,39
-
No connection
Symbol
Pin Number
Input/
Output
Function
P-LCC-44
P-DIP-40
P-MQFP-
44
GMS90C320
8
OCT. 2000 Ver 1.2
Function Description
The GMS90 series is fully compatible to the standard 8051 microcontroller family.
It is compatible with the standard 80C32. While maintaining all architectural and operational characteristics of the standard
80C32, the GMS90C320 incorporates some enhancements in the Timer 2 unit.
Figure 1 shows a block diagram of the GMS90C320
Figure 1 Block Diagram of the GMS90C320
RAM
256 x 8
Port 0
Port 0
8-bit Digital I/O
Port 1
Port 1
8-bit Digital I/O
Port 2
Port 2
8-bit Digital I/O
Port 3
Port 3
8-bit Digital I/O
CPU
Timer 0
Timer 1
Timer 2
Interrupt Unit
Serial Channel
OSC & Timing
XTAL1
XTAL2
RESET
EA
ALE
PSEN
GMS90C320
OCT. 2000 Ver 1.2
9
CPU
The GMS90C320 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD
arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set con-
sisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are
executed in 1.0
s.
Special Function Register PSW
Reset value of PSW is 00
H .
Bit
Function
CY
Carry Flag
AC
Auxiliary Carry Flag (for BCD operation)
F0
General Purpose Flag
RS1
0
0
1
1
RS0
0
1
0
1
Register Bank select control bits
Bank 0 selected, data address 00
H
-07
H
Bank 1 selected, data address 08
H
-0F
H
Bank 2 selected, data address 10
H
-17
H
Bank 3 selected, data address 18
H
-1F
H
OV
Overflow Flag
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/
even number of "one" bits in the accumulator, i.e. even parity.
MSB
LSB
Bit No.
7
6
5
4
3
2
1
0
Addr. D0
H
CY
AC
F0
RS1
RS2
OV
F1
P
PSW
GMS90C320
10
OCT. 2000 Ver 1.2
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the special function register
area.
The 27 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other
on-chip peripherals. There are also 128 directly addressable bits within the SFR area.
All SFRs are listed in Table 1, Table 2, and Table 3.
In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the
functional blocks of the GMS90C320. Table 3 illustrates the contents of the SFRs.
Table 1
Special Function Registers in Numeric Order of their Addresses
Address
Register
Contents after
Reset
Address
Register
Contents after
Reset
80
H
81
H
82
H
83
H
84
H
85
H
86
H
87
H
P0
1)
SP
DPL
DPH
reserved
reserved
reserved
PCON
1)
: Bit-addressable Special Function Register
FF
H
07
H
00
H
00
H
XX
H 2)
XX
H 2)
XX
H 2)
0XXX0000
B2)
2)
: X means that the value is indeterminate and the location is reserved
A0
H
A1
H
A2
H
A3
H
A4
H
A5
H
A6
H
A7
H
P2
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FF
H
XX
H 2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
88
H
89
H
8A
H
8B
H
8C
H
8D
H
8E
H
8F
H
TCON
1)
TMOD
TL0
TL1
TH0
TH1
reserved
reserved
00
H
00
H
00
H
00
H
00
H
00
H
XX
H
2)
XX
H
2)
A8
H
A9
H
AA
H
AB
H
AC
H
AD
H
AE
H
AF
H
IE
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0X000000
B2)
XX
H 2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
90
H
91
H
92
H
93
H
94
H
95
H
96
H
97
H
P1
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FF
H
00
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
B0
H
B1
H
B2
H
B3
H
B4
H
B5
H
B6
H
B7
H
P3
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FF
H
XX
H 2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
98
H
99
H
9A
H
9B
H
9C
H
9D
H
9E
H
9F
H
SCON
1)
SBUF
reserved
reserved
reserved
reserved
reserved
reserved
00
H
XX
H 2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
B8
H
B9
H
BA
H
BB
H
BC
H
BD
H
BE
H
BF
H
IP
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX000000
B2)
XX
H 2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
GMS90C320
OCT. 2000 Ver 1.2
11
Table 1
Special Function Registers in numeric order of their addresses (cont'd)
Address
Register
Contents after
Reset
Address
Register
Contents after
Reset
C0
H
C1
H
C2
H
C3
H
C4
H
C5
H
C6
H
C7
H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
E0
H
E1
H
E2
H
E3
H
E4
H
E5
H
E6
H
E7
H
ACC
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
C8
H
C9
H
CA
H
CB
H
CC
H
CD
H
CE
H
CF
H
T2CON
1)
T2MOD
RC2L
RC2H
TL2
TH2
reserved
reserved
00
H
XXXXXXX0
B
2)
00
H
00
H
00
H
00
H
XX
H
2)
XX
H
2)
E8
H
E9
H
EA
H
EB
H
EC
H
ED
H
EE
H
EF
H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
D0
H
D1
H
D2
H
D3
H
D4
H
D5
H
D6
H
D7
H
PSW
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1)
: Bit-addressable Special Function Register
00
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
2)
: X means that the value is indeterminate and the location is reserved
F0
H
F1
H
F2
H
F3
H
F4
H
F5
H
F6
H
F7
H
B
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
D8
H
D9
H
DA
H
DB
H
DC
H
DD
H
DE
H
DF
H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
F8
H
F9
H
FA
H
FB
H
FC
H
FD
H
FE
H
FF
H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
GMS90C320
12
OCT. 2000 Ver 1.2
Table 2
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address
Content
after Reset
CPU
ACC
B
DPH
DPL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
E0
H
1)
F0
H
1)
83
H
82
H
D0
H
1)
81
H
1)
Bit-addressable Special Function Registers
00
H
00
H
00
H
00
H
00
H
07
H
Interrupt System
IE
IP
Interrupt Enable Register
Interrupt Priority Register
A8
H
1)
B8
H
1)
0X000000
B
2)
XX000000
B
2)
2)
This special function register is listed repeatedly since some bits of it also belong to other functional blocks
Ports
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
80
H
1)
90
H
1)
A0
H
1)
B0
H
1)
FF
H
FF
H
FF
H
FF
H
Serial Channels
PCON
SBUF
SCON
Power Control Register
Serial Channel Buffer Register
Serial Channel 0 Control Register
87
H
99
H
98
H
1)
0XXX0000
B
2)
XX
H
3)
00
H
3)
X means that the value is indeterminate and the location is reserved
Timer 0 / Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88
H
1)
8C
H
8D
H
8A
H
8B
H
89
H
00
H
00
H
00
H
00
H
00
H
00
H
Timer 2
T2CON
T2MOD
RC2H
RC2L
TH2
TL2
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload Capture Register, High Byte
Timer 2 Reload Capture Register, Low Byte
Timer 2, High Byte
Timer 2, Low Byte
C8
H
1)
C9
H
CB
H
CA
H
CD
H
CC
H
00
H
XXXXXXX0
B
2)
00
H
00
H
00
H
00
H
Power Saving
Modes
PCON
Power Control Register
87
H
0XXX0000
B
2)
GMS90C320
OCT. 2000 Ver 1.2
13
Table 3
Contents of SFRs, SFRs in Numeric Order
Address
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
H
P0
81
H
SP
82
H
DPL
83
H
DPH
87
H
PCON
SMOD
-
-
-
GF1
GF0
PDE
IDLE
88
H
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
89
H
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8A
H
TL0
8B
H
TL1
8C
H
TH0
8D
H
TH1
90
H
P1
98
H
SCON
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
99
H
SBUF
A0
H
P2
A8
H
IE
EA
-
ET2
ES
ET1
EX1
ET0
EX0
B0
H
P3
B8
H
IP
-
-
PT2
PS
PT1
PX1
PT0
PX0
C8
H
T2CON
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
C9
H
T2MOD
-
-
-
-
-
-
-
DCEN
SFR bit and byte addressable
SFR not bit addressable
-
This bit location is reserved.
GMS90C320
14
OCT. 2000 Ver 1.2
Table 3
Contents of SFRs, SFRs in Numeric Order (cont'd)
Address
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CA
H
RC2L
CB
H
RC2H
CC
H
TL2
CD
H
TH2
D0
H
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
E0
H
ACC
F0
H
B
SFR bit and byte addressable
SFR not bit addressable
-
This bit location is reserved.
GMS90C320
OCT. 2000 Ver 1.2
15
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is
.
In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin
(P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is
. External inputs
INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements.
Figure 2 illustrates the input clock logic.
Figure 2 Timer/Counter 0 and 1 Input Clock Logic
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode
Description
TMOD
Input Clock
GATE
C/T
M1
M0
Internal
External
(Max.)
0
8-bit timer/counter with a
divide-by-32 prescaler
X
X
0
0
1
16-bit timer/counter
X
X
0
1
2
8-bit timer/counter with 8-bit
autoreload
X
X
1
0
3
Timer/counter 0 used as one
8-bit timer/counter and one 8-
bit timer
Timer 1 stops
X
X
1
1
OSC
12
32
-------------------
OSC
24
32
-------------------
OSC
12
----------------
OSC
24
----------------
OSC
12
----------------
OSC
24
----------------
OSC
12
----------------
OSC
24
----------------
OSC
12
/
OSC
24
/
f
O SC
12
C/T
TMOD
0
1
GATE
TMOD
TR 0/1
TCON
P3.4/T0
P3.5/T1
max. f
O SC
/24
P3.2/INT0
P3.3/INT1
Timer 0/1
Input Clock
Control
OSC
12
/
GMS90C320
16
OCT. 2000 Ver 1.2
Timer 2
Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which
is selected by bit C/T2 (T2CON.1).
It has three operating modes as shown in Table 5.
1Note:
=
falling edge
Table 5
Timer/Counter 2 Operating Modes
Mode
T2CON
T2MO
D
DECN
T2CON
EXEN
P1.1
T2EX
Remarks
Input Clock
RxCLK
or
TxCLK
CP/
RL2
TR2
Internal
External
(P1.0/T2)
16-bit Auto-
reload
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
X
X
X
0
1
reload upon overflow
reload trigger (falling edge)
Down counting
Up counting
max.
16-bit
Capture
0
0
1
1
1
1
X
X
0
1
X
16-bit Timer/Counter (only
up-counting)
capture
TH1, TL2
RC2H, RC2L
max.
Baud Rate
Generator
1
1
X
X
1
1
X
X
0
1
X
no overflow interrupt request
(TF2)
extra external interrupt
("Timer 2")
max.
off
X
X
0
X
X
X
Timer 2 stops
-
-
OSC
12
----------------
OSC
24
----------------
OSC
12
----------------
OSC
24
----------------
OSC
12
----------------
OSC
24
----------------
GMS90C320
OCT. 2000 Ver 1.2
17
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated
in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.
Table 6
USART Operating Modes
Mode
SCON
Baudrate
Description
SM0
SM1
0
0
0
Serial data enters and exits through RxD.
TxD outputs the shift clock.
8-bit are transmitted/received (LSB first)
1
0
1
Timer 1/2 overflow rate
8-bit UART
10 bits are transmitted (through TxD) or
received (RxD)
2
1
0
or
9-bit UART
11 bits are transmitted (through TxD) or
received (RxD)
3
1
1
Timer 1/2 overflow rate
9-bit UART
Like mode 2 except the variable baud rate
Table 7
Formulas for Calculating Baud rates
Baud Rate
derived from
Interface Mode
Baud rate
Oscillator
0
2
Timer 1 (16-bit timer)
(8-bit timer with 8-bit autore-
load)
1, 3
1, 3
Timer 2
1, 3
OSC
12
----------------
OSC
32
----------------
OSC
64
----------------
OSC
12
----------------
2
SMOD
OSC
64
------------------------------------------
2
SMOD
timer 1 overflow rate
32
---------------------------------------------------------------------------------
2
SMOD
OSC
32
12
256
TH1
(
)
-----------------------------------------------------------
OSC
32
65536
RC2H,RC2L
(
)
[
]
------------------------------------------------------------------------------
GMS90C320
18
OCT. 2000 Ver 1.2
Interrupt System
The GMS90C320 provides 6 interrupt sources with two priority levels. Figure 3 gives a general overview of the interrupt
sources and illustrates the request and control flags.
Figure 3
Interrupt Request Sources
PT0
IP.1
High Priority
Low Priority
EA
IE.7
TF0
TCON.5
Timer 0 Overflow
TF1
TCON.7
IE0
TCON.1
IE1
TCON.3
TF2
T2CON.7
EXF2
T2CON.6
RI
SCON.0
TI
SCON.1
Timer 2 Overflow
Timer 1 Overflow
P3.2/
INT0
P3.3/
INT1
P1.1/
T2EX
USART
PT1
IP.3
PT2
IP.5
PS
IP.4
PX0
IP.0
PX1
IP.2
ET0
IE.1
ET1
IE.3
ET2
IE.5
ES
IE.4
EX0
IE.0
EX1
IE.2
IT0
TCON.0
IT1
TCON.2
EXEN2
T2CON.3
GMS90C320
OCT. 2000 Ver 1.2
19
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-
priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of
the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within
each priority level there is a second priority structure determined by the polling sequence as shown in Table 9.
Table 8
Interrupt Sources and their Corresponding Interrupt Vectors
Source (Request Flags)
Vector
Vector Address
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
0003
H
000B
H
0013
H
001B
H
0023
H
002B
H
Table 9
Interrupt Priority-Within-Level
Interrupt Source
Priority
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
High
Low
GMS90C320
20
OCT. 2000 Ver 1.2
Power Saving Modes
Two power down modes are available, the Idle Mode and Power Down Mode.
The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down
mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview
of the power saving modes.
In the Power Down mode of operation, V
C C
can be reduced to minimize power consumption. It must be ensured, however,
that V
C C
is not reduced before the Power Down mode is invoked, and that V
C C
is restored to its normal operating level, before
the Power Down mode is terminated. The reset signal that terminates the Power Down Mode also restarts the oscillator. The
reset should not be activated before V
C C
is restored to its normal operating level and must be held active long enough to allow
the oscillator to restart and stabilize (similar to power-on reset).
Table 10
Power Saving Modes Overview
Mode
Entering Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON,#01H
- enabled interrupt
- Hardware Reset
CPU is gated off
CPU status registers maintain
their data.
Peripherals are active
Power-Down
Mode
ORL PCON,#02H
Hardware Reset
Oscillator is stopped, contents of
on-chip RAM and SFR's are main-
tained (leaving Power Down Mode
means redefinition of SFR con-
tents).
GMS90C320
OCT. 2000 Ver 1.2
21
Absolute Maximum Ratings
Ambient temperature under bias (T
A
) .......................................................................................................-40 to + 85
C
Storage temperature (T
S T
)..........................................................................................................................-65 to + 150
C
Voltage on V
C C
pins with respect to ground (V
S S
).....................................................................................-0.5 V to 6.5 V
Voltage on any pin with respect to ground (V
S S
).......................................................................................-0.5 to V
C C
+ 0.5 V
Input current on any pin during overload condition ..................................................................................-10 mA to + 10 mA
Absolute sum of all input currents during overload condition ..................................................................| 100 mA |
Power dissipation.......................................................................................................................................TBD
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the oper-
ational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may
affect device reliability. During overload conditions (V
IN
>
V
C C
or V
IN
<
V
S S
) the Voltage on V
C C
pins with respect to ground (V
S S
)
must not exceed the values defined by the absolute maximum ratings.
GMS90C320
22
OCT. 2000 Ver 1.2
DC Characteristics
DC Characteristics for GMS90C320
V
C C
= 5V + 10%, -15%; V
S S
=0V; T
A
= 0
C to 70
C
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
Max.
Input low voltage
(except EA, RESET)
V
IL
-0.5
0.2V
C C
- 0.1
V
-
Input low voltage (EA)
V
IL1
-0.5
0.2V
C C
- 0.3
V
-
Input low voltage (RESET)
V
IL2
-0.5
0.2V
C C
+ 0.1
V
-
Input high voltage (except
XTAL1, EA, RESET)
V
IH
0.2V
C C
+ 0.9
V
C C
+ 0.5
V
-
Input high voltage to XTAL1
V
IH 1
0.7V
C C
V
C C
+ 0.5
V
-
Input high voltage to EA,
RESET
V
IH 2
0.6V
C C
V
C C
+ 0.5
V
-
Output low voltage
(ports 1, 2, 3)
V
O L
-
0.3
0.45
1.0
V
I
O L
= 100
A
I
O L
= 1.6mA
1)
I
O L
= 3.5mA
Output low voltage
(port 0, ALE, PSEN)
V
O L1
-
0.3
0.45
1.0
V
I
O L
= 200
A
I
O L
= 3.2mA
1)
I
O L
= 7.0mA
Output high voltage
(ports 1, 2, 3)
V
O H
2.4
0.9V
C C
-
V
I
O H
= -80
A
I
O H
= -10
A
Output high voltage
(port 0 in external bus mode,
ALE, PSEN)
V
O H 1
2.4
0.9V
C C
-
V
I
O H
= -800
A
2)
I
O H
= -80
A
2)
Logic 0 input current
(ports 1, 2, 3)
I
IL
-10
-50
A
V
IN
= 0.45V
Logical 1-to-0 transition cur-
rent (ports 1, 2, 3)
I
T L
-65
-650
A
V
IN
= 2.0V
Input leakage current
(port 0, EA)
I
LI
-
1
A
0.45
<
V
IN
<
V
C C
Pin capacitance
C
IO
-
10
pF
f
C
=1MHz, T
A
= 25
C
Power supply current:
Active mode, 12MHz
3)
Idle mode, 12MHz
3)
Active mode, 24 MHz
3)
Idle mode, 24MHz
3)
Active mode, 40 MHz
3)
Idle mode, 40 MHz
3)
Active mode, 50 MHz
3)
Idle mode, 50 MHz
3)
Power Down Mode
3)
I
C C
I
C C
I
C C
I
C C
I
C C
I
C C
I
C C
I
C C
I
P D
-
-
-
-
-
-
-
-
-
16
7.5
26
13.5
44
18
55
22.5
50
mA
mA
mA
mA
mA
mA
mA
mA
A
V
C C
= 5V
4)
V
C C
= 5V
5)
V
C C
= 5V
4)
V
C C
= 5V
5)
V
C C
= 5V
4)
V
C C
= 5V
5)
V
C C
= 5V
4)
V
C C
= 5V
5)
V
C C
= 5.5V
6)
GMS90C320
OCT. 2000 Ver 1.2
23
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
O L
of ALE and port 3. The
noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions
during bus operation. In the worst case (capacitive loading:
>
50pF at 3.3V,
>
100pF at 5V), the noise pulse on ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-
trigger strobe input.
2)
Capacitive loading on ports 0 and 2 may cause the V
O H
on ALE and PSEN to momentarily fall below the 0.9V
C C
specification
when the address lines are stabilizing.
3)
I
C C m ax
at other frequencies is given by:
active mode: I
C C
= 1.0
O SC
+ 3.16
idle mode: I
C C
= 0.37
O SC
+ 3.63
where
O SC
is the oscillator frequency in MHz. I
C C
values are given in mA and measured at V
C C
= 5V.
4)
I
C C
(active mode) is measured with:
XTAL1 driven with t
C LC H
, t
C H C L
= 5ns, V
IL
= V
SS
+ 0.5V, V
IH
= V
C C
- 0.5V; XTAL2 = N.C.;
EA = Port 0 = RESET = V
C C
; all other pins are disconnected. I
C C
would be slightly higher if a crystal oscillator is used (appr.
1mA).
5)
I
C C
(Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with t
C LC H
, t
C H C L
= 5ns, V
IL
= V
SS
+ 0.5V, V
IH
= V
C C
- 0.5V; XTAL2 = N.C.;
RESET = EA = V
SS
; Port0 = V
C C
; all other pins are disconnected;
6)
I
PD
(Power Down Mode) is measured under following conditions:
EA = Port 0 = V
C C
; RESET = V
SS
; XTAL2 = N.C.; XTAL1 = V
S S
; all other pins are disconnected.
GMS90C320
24
OCT. 2000 Ver 1.2
DC Characteristics for GMS90L320
V
C C
= 3.3V + 0.3V, -0.6V; V
S S
=0V; T
A
= 0
C to 70
C
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
Max.
Input low voltage
V
IL
-0.5
0.8
V
-
Input high voltage
V
IH
2.0
V
C C
+ 0.5
V
-
Output low voltage
(ports 1, 2, 3)
V
O L
-
0.45
0.30
V
I
O L
= 1.6mA
1)
I
O L
= 100
A
1)
Output low voltage
(port 0, ALE, PSEN)
V
O L1
-
0.45
0.30
V
I
O L
= 3.2mA
1)
I
O L
= 200
A
1)
Output high voltage
(ports 1, 2, 3)
V
O H
2.0
0.9V
C C
-
V
I
O H
= -20
A
I
O H
= -10
A
Output high voltage
(port 0 in external bus mode, ALE,
PSEN)
V
O H 1
2.0
0.9V
C C
-
V
I
O H
= -800
A
2)
I
O H
= -80
A
2)
Logic 0 input current
(ports 1, 2, 3)
I
IL
-1
-50
A
V
IN
= 0.45V
Logical 1-to-0 transition current
(ports 1, 2, 3)
I
T L
-25
-250
A
V
IN
= 2.0V
Input leakage current
(port 0, EA)
I
LI
-
1
A
0.45
<
V
IN
<
V
C C
Pin capacitance
C
IO
-
10
pF
f
C
= 1MHz
T
A
= 25
C
Power supply current:
Active mode, 16 MHz
3)
Idle mode, 16MHz
3)
Active mode, 24MHz
3)
Idle mode, 24MHz
3)
Power Down Mode
3)
I
C C
I
C C
I
C C
I
C C
I
P D
-
-
-
-
-
10
5.25
16
8.25
10
mA
mA
A
V
C C
= 3.3V
4)
V
C C
= 3.3V
5)
V
C C
= 3.3V
4)
V
C C
= 3.3V
5)
V
C C
= 3.6V
6)
GMS90C320
OCT. 2000 Ver 1.2
25
AC Characteristics
Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a `t' (stand for time). The other characters, depending on
their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters
and what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P: PSEN
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
For example,
t
A VLL
= Time from Address Valid to ALE Low
t
LLPL
= Time from ALE Low to PSEN Low
GMS90C320
26
OCT. 2000 Ver 1.2
AC Characteristics for 12MHz version
External Program Memory Characteristics
V
CC
= 5V:
V
C C
= 5V
+
10%,
-
15%; V
S S
= 0V; T
A
= 0
C to 70
C
(C
L
for port 0. ALE and PSEN outputs = 100pF; C
L
for all other outputs = 80pF)
V
CC
= 3.3V:
V
C C
= 3.3V
+
0.3V,
-
0.6V; V
S S
= 0V; T
A
= 0
C to 70
C
(C
L
for port 0. ALE and PSEN outputs = 50pF; C
L
for all other outputs = 50pF)
Variable clock:
Vcc = 5V: 1/t
C LC L
= 3.5 MHz to 12 MHz
Vcc = 3.3V: 1/t
C LC L
= 1 MHz to 12 MHz
Parameter
Symbol
12 MHz Oscillator
Variable Oscillator
1/t
CLC L
= 3.5 to 12MHz
Unit
Min.
Max.
Min.
Max.
ALE pulse width
t
LH LL
127
-
2t
C LC L
-40
-
ns
Address setup to ALE
t
A VLL
43
-
t
C LC L
-40
-
ns
Address hold after ALE
t
LLA X
43
-
t
C LC L
-40
-
ns
ALE low to valid instruction in
t
LLIV
-
233
-
4t
C LC L
-100
ns
ALE to PSEN
t
LLP L
58
-
t
C LC L
-25
-
ns
PSEN pulse width
t
P LP H
215
-
3t
C LC L
-35
-
ns
PSEN to valid instruction in
t
P LIV
-
150
-
3t
C LC L
-100
ns
Input instruction hold after PSEN
t
P XIX
0
-
0
-
ns
Input instruction float after PSEN
t
P XIZ
1)
1)
Interfacing the GMS90C320 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage
to port 0 Drivers.
-
63
-
t
C LC L
-20
ns
Address valid after PSEN
t
P XA V
1)
75
-
t
C LC L
-8
-
ns
Address to valid instruction in
t
A VIV
-
302
-
5t
C LC L
-115
ns
Address float to PSEN
t
A ZP L
-10
-
-10
-
ns
GMS90C320
OCT. 2000 Ver 1.2
27
AC Characteristics for 12MHz version
External Data Memory Characteristics
Advance Information (12MHz)
External Clock Drive
Parameter
Symbol
12 MHz Oscillator
Variable Oscillator
1/t
C LCL
= 3.5 to 12MHz
Unit
Min.
Max.
Min.
Max.
RD pulse width
t
R LR H
400
-
6t
C LC L
-100
-
ns
WR pulse width
t
W LW H
400
-
6t
C LC L
-100
-
ns
Address hold after ALE
t
LLA X 2
127
-
2t
C LC L
-40
-
ns
RD to valid data in
t
R LD V
-
252
-
5t
C LC L
-165
ns
Data hold after RD
t
R H D X
0
-
0
-
ns
Data float after RD
t
R H D Z
-
97
-
2t
C LC L
-70
ns
ALE to valid data in
t
LLD V
-
517
-
8t
C LC L
-150
ns
Address to valid data in
t
A VD V
-
585
-
9t
C LC L
-165
ns
ALE to WR or RD
t
LLW L
200
300
3t
C LC L
-50
3t
C LC L
+50
ns
Address valid to WR or RD
t
A VW L
203
-
4t
C LC L
-130
-
ns
WR or RD high to ALE high
t
W H LH
43
123
t
C LC L
-40
t
C LC L
+40
ns
Data valid to WR transition
t
Q VW X
33
-
t
C LC L
-50
-
ns
Data setup before WR
t
Q VW H
433
-
7t
C LC L
-150
-
ns
Data hold after WR
t
W H Q X
33
-
t
C LC L
-50
-
ns
Address float after RD
t
R LA Z
-
0
-
0
ns
Parameter
Symbol
Variable Oscillator
(Freq. = 3.5 to 12MHz)
Unit
Min.
Max.
Oscillator period (V
C C
=5V)
Oscillator period (V
C C
=3.3V)
t
C LC L
t
C LC L
83.3
83.3
285.7
1
ns
High time
t
C H C X
20
t
C LC L
- t
C LC X
ns
Low time
t
C LC X
20
t
C LC L
- t
C H C X
ns
Rise time
t
C LC H
-
20
ns
Fall time
t
C H C L
-
20
ns
GMS90C320
28
OCT. 2000 Ver 1.2
AC Characteristics for 16MHz version
External Program Memory Characteristics
V
CC
= 5V:
V
C C
= 5V
+
10%,
-
15%; V
S S
= 0V; T
A
= 0
C to 70
C
(C
L
for port 0. ALE and PSEN outputs = 100pF; C
L
for all other outputs = 80pF)
V
CC
= 3.3V:
V
C C
= 3.3V
+
0.3V,
-
0.6V; V
S S
= 0V; T
A
= 0
C to 70
C
(C
L
for port 0. ALE and PSEN outputs = 50pF; C
L
for all other outputs = 50pF)
Variable clock:
Vcc = 5V: 1/t
C LC L
= 3.5 MHz to 16 MHz
Vcc = 3.3V: 1/t
C LC L
= 1 MHz to 16 MHz
Parameter
Symbol
16 MHz Oscillator
Variable Oscillator
1/t
C LCL
= 3.5 to 16MHz
Unit
Min.
Max.
Min.
Max.
ALE pulse width
t
LH LL
85
-
2t
C LC L
-40
-
ns
Address setup to ALE
t
A VLL
23
-
t
C LC L
-40
-
ns
Address hold after ALE
t
LLA X
43
-
t
C LC L
-40
-
ns
ALE low to valid instruction in
t
LLIV
-
150
-
4t
C LC L
-100
ns
ALE to PSEN
t
LLP L
38
-
t
C LC L
-25
-
ns
PSEN pulse width
t
P LP H
153
-
3t
C LC L
-35
-
ns
PSEN to valid instruction in
t
P LIV
-
88
-
3t
C LC L
-100
ns
Input instruction hold after PSEN
t
P XIX
0
-
0
-
ns
Input instruction float after PSEN
t
P XIZ
1)
1)
Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
-
43
-
t
C LC L
-20
ns
Address valid after PSEN
t
P XA V
1)
55
-
t
C LC L
-8
-
ns
Address to valid instruction in
t
A VIV
-
198
-
5t
C LC L
-115
ns
Address float to PSEN
t
A ZP L
-10
-
-10
-
ns
GMS90C320
OCT. 2000 Ver 1.2
29
AC Characteristics for 16MHz
External Data Memory Characteristics
Advance Information (16MHz)
External Clock Drive
Parameter
Symbol
16 MHz Oscillator
Variable Oscillator
1/t
C LCL
= 3.5 to 16MHz
Unit
Min.
Max.
Min.
Max.
RD pulse width
t
R LR H
275
-
6t
C LC L
-100
-
ns
WR pulse width
t
W LW H
275
-
6t
C LC L
-100
-
ns
Address hold after ALE
t
LLA X 2
127
-
2t
C LC L
-40
-
ns
RD to valid data in
t
R LD V
-
183
-
5t
C LC L
-130
ns
Data hold after RD
t
R H D X
0
-
0
-
ns
Data float after RD
t
R H D Z
-
75
-
2t
C LC L
-50
ns
ALE to valid data in
t
LLD V
-
350
-
8t
C LC L
-150
ns
Address to valid data in
t
A VD V
-
398
-
9t
C LC L
-165
ns
ALE to WR or RD
t
LLW L
138
238
3t
C LC L
-
50
3t
C LC L
+50
ns
Address valid to WR or RD
t
A VW L
120
-
4t
C LC L
-130
-
ns
WR or RD high to ALE high
t
W H LH
28
97
t
C LC L
-
35
t
C LC L
+35
ns
Data valid to WR transition
t
Q VW X
13
-
t
C LC L
-
50
-
ns
Data setup before WR
t
Q VW H
288
-
7t
C LC L
-150
-
ns
Data hold after WR
t
W H Q X
23
-
t
C LC L
-
40
-
ns
Address float after RD
t
R LA Z
-
0
-
0
ns
Parameter
Symbol
Variable Oscillator
(Freq. = 3.5 to 16MHz)
Unit
Min.
Max.
Oscillator period
t
C LC L
62.5
285.7
ns
High time
t
C H C X
17
t
C LC L
- t
C LC X
ns
Low time
t
C LC X
17
t
C LC L
- t
C H C X
ns
Rise time
t
C LC H
-
17
ns
Fall time
t
C H C L
-
17
ns
GMS90C320
30
OCT. 2000 Ver 1.2
AC Characteristics for 24MHz version
External Program Memory Characteristics
V
CC
= 5V:
V
C C
= 5V
+
10%,
-
15%; V
S S
= 0V; T
A
= 0
C to 70
C
(C
L
for port 0. ALE and PSEN outputs = 100pF; C
L
for all other outputs = 80pF)
V
CC
= 3.3V:
V
C C
= 3.3V
+
0.3V,
-
0.6V; V
S S
= 0V; T
A
= 0
C to 70
C
(C
L
for port 0. ALE and PSEN outputs = 50pF; C
L
for all other outputs = 50pF)
Variable clock:
Vcc = 5V: 1/t
C LC L
= 3.5 MHz to 24 MHz
Vcc = 3.3V: 1/t
C LC L
= 1 MHz to 24 MHz
Parameter
Symbol
24 MHz Oscillator
Variable Oscillator
1/t
C LCL
= 3.5 to 24MHz
Unit
Min.
Max.
Min.
Max.
ALE pulse width
t
LH LL
43
-
2t
C LC L
-40
-
ns
Address setup to ALE
t
A VLL
17
-
t
C LC L
-25
-
ns
Address hold after ALE
t
LLA X
17
-
t
C LC L
-25
-
ns
ALE low to valid instruction in
t
LLIV
-
80
-
4t
C LC L
-87
ns
ALE to PSEN
t
LLP L
22
-
t
C LC L
-20
-
ns
PSEN pulse width
t
P LP H
95
-
3t
C LC L
-30
-
ns
PSEN to valid instruction in
t
P LIV
-
60
-
3t
C LC L
-65
ns
Input instruction hold after PSEN
t
P XIX
0
-
0
-
ns
Input instruction float after PSEN
t
P XIZ
1)
1)
Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
-
32
-
t
C LC L
-10
ns
Address valid after PSEN
t
P XA V
1)
37
-
t
C LC L
-5
-
ns
Address to valid instruction in
t
A VIV
-
148
-
5t
C LC L
-60
ns
Address float to PSEN
t
A ZP L
-10
-
-10
-
ns
GMS90C320
OCT. 2000 Ver 1.2
31
AC Characteristics for 24MHz
External Data Memory Characteristics
Advance Information (24MHz)
External Clock Drive
Parameter
Symbol
24 MHz Oscillator
Variable Oscillator
1/t
C LCL
= 3.5 to 24MHz
Unit
Min.
Max.
Min.
Max.
RD pulse width
t
R LR H
180
-
6t
C LC L
-70
-
ns
WR pulse width
t
W LW H
180
-
6t
C LC L
-70
-
ns
Address hold after ALE
t
LLA X 2
56
-
2t
C LC L
-27
-
ns
RD to valid data in
t
R LD V
-
118
-
5t
C LC L
-90
ns
Data hold after RD
t
R H D X
0
-
0
-
ns
Data float after RD
t
R H D Z
-
63
-
2t
C LC L
-20
ns
ALE to valid data in
t
LLD V
-
200
-
8t
C LC L
-133
ns
Address to valid data in
t
A VD V
-
220
-
9t
C LC L
-155
ns
ALE to WR or RD
t
LLW L
75
175
3t
C LC L
-50
3t
C LC L
+50
ns
Address valid to WR or RD
t
A VW L
67
-
4t
C LC L
-97
-
ns
WR or RD high to ALE high
t
W H LH
17
67
t
C LC L
-25
t
C LC L
+25
ns
Data valid to WR transition
t
Q VW X
5
-
t
C LC L
-37
-
ns
Data setup before WR
t
Q VW H
170
-
7t
C LC L
-122
-
ns
Data hold after WR
t
W H Q X
15
-
t
C LC L
-27
-
ns
Address float after RD
t
R LA Z
-
0
-
0
ns
Table 11.
Parameter
Symbol
Variable Oscillator
(Freq. = 3.5 to 24MHz)
Unit
Min.
Max.
Oscillator period
t
C LC L
41.7
285.7
ns
High time
t
C H C X
12
t
C LC L
- t
C LC X
ns
Low time
t
C LC X
12
t
C LC L
- t
C H C X
ns
Rise time
t
C LC H
-
12
ns
Fall time
t
C H C L
-
12
ns
GMS90C320
32
OCT. 2000 Ver 1.2
AC Characteristics for 40MHz version
V
C C
= 5V + 10%,
-
15%; V
S S
= 0V; T
A
= 0
C to 70
C
(C
L
for port 0. ALE and PSEN outputs = 100pF; C
L
for all other outputs = 80pF)
External Program Memory Characteristics
Parameter
Symbol
40 MHz Oscillator
Variable Oscillator
1/t
C LCL
= 3.5 to 40MHz
Unit
Min.
Max.
Min.
Max.
ALE pulse width
t
LH LL
35
-
2t
C LC L
-
15
-
ns
Address setup to ALE
t
A VLL
10
-
t
C LC L
-
15
-
ns
Address hold after ALE
t
LLA X
10
-
t
C LC L
-
15
-
ns
ALE low to valid instruction in
t
LLIV
-
55
-
4t
C LC L
-
45
ns
ALE to PSEN
t
LLP L
10
-
t
C LC L
-
15
-
ns
PSEN pulse width
t
P LP H
60
-
3t
C LC L
-
15
-
ns
PSEN to valid instruction in
t
P LIV
-
25
-
3t
C LC L
-
50
ns
Input instruction hold after PSEN
t
P XIX
0
-
0
-
ns
Input instruction float after PSEN
t
P XIZ
1)
1)
Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage
to port 0 Drivers.
-
15
-
t
C LC L
-
10
ns
Address valid after PSEN
t
P XA V
1)
20
-
t
C LC L
-
5
-
ns
Address to valid instruction in
t
A VIV
-
65
-
5t
C LC L
-
60
ns
Address float to PSEN
t
A ZP L
-5
-
-5
-
ns
GMS90C320
OCT. 2000 Ver 1.2
33
AC Characteristics for 40MHz
External Data Memory Characteristics
Advance Information (40MHz)
External Clock Drive
Parameter
Symbol
at 40 MHz Clock
Variable Clock
1/t
C LCL
= 3.5 to 40MHz
Unit
Min.
Max.
Min.
Max.
RD pulse width
t
R LR H
120
-
6t
C LC L
-30
-
ns
WR pulse width
t
W LW H
120
-
6t
C LC L
-30
-
ns
Address hold after ALE
t
LLA X 2
10
-
t
C LC L
-15
-
ns
RD to valid data in
t
R LD V
-
75
-
5t
C LC L
-50
ns
Data hold after RD
t
R H D X
0
-
0
-
ns
Data float after RD
t
R H D Z
-
38
-
2t
C LC L
-12
ns
ALE to valid data in
t
LLD V
-
150
-
8t
C LC L
-50
ns
Address to valid data in
t
A VD V
-
150
-
9t
C LC L
-75
ns
ALE to WR or RD
t
LLW L
60
90
3t
C LC L
-15
3t
C LC L
+15
ns
Address valid to WR or RD
t
A VW L
70
-
4t
C LC L
-30
-
ns
WR or RD high to ALE high
t
W H LH
10
40
t
C LC L
-15
t
C LC L
+15
ns
Data valid to WR transition
t
Q VW X
5
-
t
C LC L
-20
-
ns
Data setup before WR
t
Q VW H
125
-
7t
C LC L
-50
-
ns
Data hold after WR
t
W H Q X
5
-
t
C LC L
-20
-
ns
Address float after RD
t
R LA Z
-
0
-
0
ns
Parameter
Symbol
Variable Oscillator
(Freq. = 3.5 to 40MHz)
Unit
Min.
Max.
Oscillator period
t
C LC L
25
285.7
ns
High time
t
C H C X
10
t
C LC L
- t
C LC X
ns
Low time
t
C LC X
10
t
C LC L
- t
C H C X
ns
Rise time
t
C LC H
-
10
ns
Fall time
t
C H C L
-
10
ns
GMS90C320
34
OCT. 2000 Ver 1.2
AC Characteristics for 50MHz version
V
C C
= 5V + 10%,
-
15%; V
S S
= 0V; T
A
= 0
C to 70
C
(C
L
for port 0. ALE and PSEN outputs = 100pF; C
L
for all other outputs = 80pF)
Variable Clock : V
C C
= 5V, 1/
t
C LC L
= 3.5MHz to 50 MHz
External Program Memory Characteristics
Parameter
Symbol
50 MHz Oscillator
Variable Oscillator
1/t
C LCL
= 3.5 to 50MHz
Unit
Min.
Max.
Min.
Max.
ALE pulse width
t
LH LL
25
-
2t
C LC L
-
15
-
ns
Address setup to ALE
t
A VLL
5
-
t
C LC L
-
15
-
ns
Address hold after ALE
t
LLA X
5
-
t
C LC L
-
15
-
ns
ALE low to valid instruction in
t
LLIV
-
40
-
4t
C LC L
-
40
ns
ALE to PSEN
t
LLP L
5
-
t
C LC L
-
15
-
ns
PSEN pulse width
t
P LP H
45
-
3t
C LC L
-
15
-
ns
PSEN to valid instruction in
t
P LIV
-
20
-
3t
C LC L
-
40
ns
Input instruction hold after PSEN
t
P XIX
0
-
0
-
ns
Input instruction float after PSEN
t
P XIZ
1)
1)
Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage
to port 0 Drivers.
-
10
-
t
C LC L
-
10
ns
Address valid after PSEN
t
P XA V
1)
15
-
t
C LC L
-
5
-
ns
Address to valid instruction in
t
A VIV
-
45
-
5t
C LC L
-
55
ns
Address float to PSEN
t
A ZP L
-5
-
-5
-
ns
GMS90C320
OCT. 2000 Ver 1.2
35
AC Characteristics for 50MHz
External Data Memory Characteristics
Advance Information (50MHz)
External Clock Drive
Parameter
Symbol
at 50 MHz Clock
Variable Clock
1/t
C LCL
= 3.5 to 50MHz
Unit
Min.
Max.
Min.
Max.
RD pulse width
t
R LR H
90
-
6t
C LC L
-30
-
ns
WR pulse width
t
W LW H
90
-
6t
C LC L
-30
-
ns
Address hold after ALE
t
LLA X 2
25
-
2t
C LC L
-15
-
ns
RD to valid data in
t
R LD V
-
60
-
5t
C LC L
-40
ns
Data hold after RD
t
R H D X
0
-
0
-
ns
Data float after RD
t
R H D Z
-
28
-
2t
C LC L
-12
ns
ALE to valid data in
t
LLD V
-
120
-
8t
C LC L
-40
ns
Address to valid data in
t
A VD V
-
125
-
9t
C LC L
-55
ns
ALE to WR or RD
t
LLW L
45
75
3t
C LC L
-15
3t
C LC L
+15
ns
Address valid to WR or RD
t
A VW L
50
-
4t
C LC L
-30
-
ns
WR or RD high to ALE high
t
W H LH
5
35
t
C LC L
-15
t
C LC L
+15
ns
Data valid to WR transition
t
Q VW X
5
-
t
C LC L
-15
-
ns
Data setup before WR
t
Q VW H
100
-
7t
C LC L
-40
-
ns
Data hold after WR
t
W H Q X
5
-
t
C LC L
-15
-
ns
Address float after RD
t
R LA Z
-
0
-
0
ns
Parameter
Symbol
Variable Oscillator
(Freq. = 3.5 to 50MHz)
Unit
Min.
Max.
Oscillator period
t
C LC L
20
285.7
ns
High time
t
C H C X
10
t
C LC L
- t
C LC X
ns
Low time
t
C LC X
10
t
C LC L
- t
C H C X
ns
Rise time
t
C LC H
-
10
ns
Fall time
t
C H C L
-
10
ns
GMS90C320
36
OCT. 2000 Ver 1.2
Figure 4 External Program Memory Read Cycle
t
LH LL
t
P X AV
t
P X IZ
t
PX IX
t
LLAX
t
LLIV
t
PLIV
t
PLP H
t
AZP L
t
LL PL
t
AV LL
A0-A7
INSTR.
IN
A0-A7
A8-A15
A8-A15
t
AV IV
ALE
PSEN
PORT 0
PORT 2
GMS90C320
OCT. 2000 Ver 1.2
37
Figure 5 External Data Memory Read Cycle
Figure 6 External Data Memory Write Cycle
t
L H LL
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
ALE
PSEN
PORT 0
PORT 2
RD
t
LLW L
DATA IN
A0-A7 from PCL
INSTR. IN
A0-A7 from
t
LLA X 2
t
A VW L
t
AV LL
t
A V D V
t
R LA Z
t
LLD V
t
R LR H
t
R LD V
t
R H D X
t
R H D Z
t
W H LH
RI or DPL
t
LH LL
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
ALE
PSEN
PORT 0
PORT 2
WR
t
LLW L
DATA OUT
A0-A7 from PCL
INSTR. IN
A0-A7 from
t
LLA X
t
A VW L
t
A VLL
t
W L W H
t
W H Q X
t
W H LH
RI or DPL
t
Q V W X
t
Q V W H
GMS90C320
38
OCT. 2000 Ver 1.2
Figure 7 AC Testing: Input, Output Waveforms
Figure 8 Float Waveforms
Figure 9 External Clock Cycle
AC Inputs during testing are driven at V
C C
-
0.5V for a logic `1' and 0.45V for a logic `0'.
0.2V
C C
+
0.9
0.2V
C C
-
0.1
Test Points
V
C C
-
0.5V
0.45V
Timing measurements are made a V
IH m in
for a logic `1' and V
ILm ax
for a logic `0'.
V
LO A D
+
0.1
V
LO A D
-
0.1
Timing Reference Points
0.2V
C C
-
0.1
V
O H
-
0.1
V
O L
+
0.1
V
LO A D
For timing purposes a port pin is no longer floating when a 100mV change from load voltage
I
O L
/ I
O H
20mA.
occurs and begins to float when a 100mV change from the loaded V
O H
/ V
O L
level occurs.
t
C H C L
t
C LC H
t
C LC X
t
C LC L
t
C H C X
0.2 V
C C
-
0.1
0.7 V
C C
V
C C
-
0.5V
0.45V
GMS90C320
OCT. 2000 Ver 1.2
39
OSCILLATOR CIRCUIT
Figure 10 Recommended Oscillator Circuits
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic
resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external
components.
XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
CRYSTAL OSCILLATOR MODE
DRIVING FROM EXTERNAL SOURCE
XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
External Oscillator
Signal
N.C.
C2
C1
C1, C2 = 30pF
10pF for Crystals
For Ceramic Resonators, contact resonator manufacturer.
GMS90C320
40
OCT. 2000 Ver 1.2
Plastic Package P-LCC-44
(Plastic Leaded Chip-Carrier)
0.180
0.165
UNIT: INCH
44PLCC
0.012
0.0075
0.120
0.090
0.
0
3
2
0.
0
2
6
0.
630
0.
590
min. 0.020
0.656
0.650
0.695
0.685
0
.
656
0
.
650
0
.
695
0
.
685
0.050 BSC
0
.
021
0
.
013
GMS90C320
OCT. 2000 Ver 1.2
41
Plastic Package P-DIP-40
(Plastic Dual in-Line Package)
UNIT: INCH
2.075
2.045
0.
200
m
a
x.
0.022
0.015
0.065
0.045
0.100 BSC
0.550
0.530
0.600 BSC
0-15
0.012
0.008
40DIP
0.
140
0.
120
m
i
n.
0.
015
GMS90C320
42
OCT. 2000 Ver 1.2
Plastic Package P-MQFP-44
(Plastic Metric Quad Flat Package)
2.35 max.
SEE DETAIL "A"
1.03
0.73
0-7
0.
25
0.
10
1.60
REF
DETAIL "A"
UNIT: MM
0.45
0.30
0.80 BSC
2.
10
1.
95
P-MQFP-44
0
.
1
3
0
.
2
3
10.10
9.90
13.45
12.95
10.
10
9.
90
13.
45
12.
95