1
HDM8515 Users Manual
DVB/DSS Compliant Receiver
Dec. 2000
Priliminary
2
Direct Broadcast Satellite (DBS) has been one of the most successful new product
introductions in the history of consumer electronics. This product represents the first
application of digital video compression for broadcast television. Originally intended to
provide cable quality television services to remote areas, this product is now offering a
competitive replacement to cable services in many urban areas.
The first operational systems employ closed proprietary signaling structures. The
European Broadcasting Union (EBU) has developed the first open standard (DVB-S) for
DBS services. The broadcasting community has embraced this standard which is now
being adopted for new systems throughout the world. This widely accepted open
standard is essential for DBS to achieve full market potential.
The HDM8515
TM
is a fully DVB-S&DSS compliant ADC/QPSK demodulator/FEC device
which provides an MPEG-2 stream to be processed by the conditional access and video
decompression circuits. The demodulator clocked with a fixed frequency is true variable
rate over the range of 1 to 55M symbols-per-second. This product achieves the highest
performance and flexibility. It minimizes the cost of external circuits, thus reducing
overall system cost.
3
Hynix Semiconductor Co., Ltd reserves the right to make changes to its products or
specifications to improve performance, reliability, or manufacturability. Information
furnished by Hynix Semiconductor Co., Ltd is believed to be accurate and reliable.
However, no responsibility is assumed by Hynix Semiconductor Co., Ltd for its use; nor
for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by its implication or otherwise under any patent rights of
Hynix Semiconductor Co., Ltd.
For more information contact:
Address: Youngdong Bldg. 891, Daechi-dong, Kangnam-gu, Seoul, 135-738, Korea
Tel: 82-2-3459-3188
Fax: 82-2-3459-5843
E-mail: kosb@hynix.com
4
TABLE OF CONTENTS
1. INTRODUCTION TO THE HDM8515...................................................................................................................7
1.1 F
EATURES AND
B
ENEFITS
..................................................................................................................................8
2. HARDWARE SPECIFICATION..............................................................................................................................9
3. TECHNICAL OVERVIEW..................................................................................................................................... 19
3.1 D
UAL
C
HANNEL
A
NALOG TO
D
IGITAL
C
ONVERTER
.................................................................................. 19
3.2 V
ARIABLE
R
ATE
D
EMODULATOR
.................................................................................................................. 21
3.3 N
OISE
M
EASUREMENT
C
IRCUIT
.....................................................................................................................23
3.4 V
ITERBI
D
ECODER
.............................................................................................................................................25
3.5 A
UTONOMOUS
A
CQUISITION
..........................................................................................................................26
3.6 R
EED
S
OLOMON
D
ECODER
.............................................................................................................................. 28
3.7 C
LOCK
G
ENERATION
PLL.................................................................................................................................30
3.8 DBS R
ECEIVER
................................................................................................................................................... 35
3.9 D
I
SE
Q
C I
NTERFACE
...........................................................................................................................................36
4. MECHANICAL SPECIFICATIONS..................................................................................................................... 37
4.1 100 P
IN
Q
UAD
F
LAT
P
ACK
................................................................................................................................37
4.2 64 P
IN
T
HIN
Q
UAD
F
LAT
P
ACK
........................................................................................................................39
4.3 R
ECOMMENDED
A
NALOG
P
IN
C
ONNECTION
............................................................................................... 41
4.4 R
ECOMMENDED
C
LOCK
G
ENERATION
C
IRCUIT
...........................................................................................41
5. SIGNAL DESCRIPTION....................................................................................................................................... 42
5.1 I
NPUTS
..................................................................................................................................................................42
5.2 O
UTPUTS
............................................................................................................................................................. 42
5.3 M
ONIT OR AND
C
ONTROL
I
NTERFACE
...........................................................................................................45
5.4 I2C M
ODE
............................................................................................................................................................. 46
6. REGISTER DEFINITIONS..................................................................................................................................... 48
6.1 W
RITE
R
EGISTERS
..............................................................................................................................................48
6.2 R
EAD
R
EGISTERS
................................................................................................................................................61
APPENDIX.................................................................................................................................................................... 66
A1. L
OOP
F
ILTER
P
ROGRAMMING
A
PPLICATION
N
OTE
................................................................................67
A2. F
ALSE
L
OCK
E
SCAPE
A
PPLICATION
N
OTE
.................................................................................................70
A3. P
ERFORMANCE WITH
I
NTERFERENCE
.......................................................................................................... 71
A4. N
YQUIST
C
RITERIA
C
ONSIDERATIONS
......................................................................................................... 75
5
LIST OF FIGURES
F
IGURE
1: T
OP
L
EVEL
B
LOCK
D
IAGRAM
....................................................................................................................7
F
IGURE
2: I
NPUT
D
ATA
T
IMING
D
IAGRAM
.............................................................................................................10
F
IGURE
3: I
NTEL
80C88A R
EAD
T
IMING
D
IAGRAM
............................................................................................... 11
F
IGURE
4: I
NTEL
80C88A W
RITE
T
IMING
D
IAGRAM
............................................................................................. 12
F
IGURE
5: I
NTEL
8051 R
EAD
T
IMING
D
IAGRAM
.....................................................................................................13
F
IGURE
6: I
NTEL
8051 W
RITE
T
IMING
D
IAGRAM
...................................................................................................14
F
IGURE
7: M
OTOROLA
R
EAD
T
IMING
D
IAGRAM
....................................................................................................15
F
IGURE
8: M
OTOROLA
W
RITE
T
IMING
D
IAGRAM
.................................................................................................16
F
IGURE
9: O
UTPUT
T
IMING
D
IAGRAM FOR
N
ORMAL
P
ARALLEL
....................................................................... 17
F
IGURE
10: O
UTPUT
T
IMING
D
IAGRAM FOR
N
ORMAL
S
ERIAL
...........................................................................17
F
IGURE
11: O
UTPUT
T
IMING
D
IAGRAM FOR
R
EGULATED
P
ARALLEL
............................................................... 18
F
IGURE
12: O
UTPUT
T
IMING
D
IAGRAM FOR
R
EGULATED
S
ERIAL
.....................................................................18
F
IGURE
13: ADC B
LOCK
D
IAGRAM
............................................................................................................................ 20
F
IGURE
14 D
EMODULATOR
B
LOCK
D
IAGRAM
........................................................................................................ 21
F
IGURE
15: N
OISE
M
EASUREMENT
C
IRCUIT
...........................................................................................................23
F
IGURE
16: N
OISE
A
CCUMULATOR AS A FUNCTION OF
SNR
AND
T
IME
............................................................ 24
F
IGURE
17: V
ITERBI
D
ECODER
...................................................................................................................................25
F
IGURE
18: R
EED
S
OLOMON
D
ECODER
.................................................................................................................... 29
F
IGURE
19: T
YPICAL
S
ET
T
OP
B
OX
D
EMODULATOR
............................................................................................ 35
F
IGURE
20: M
ECHANICAL
C
ONFIGURATION
...........................................................................................................38
F
IGURE
21: M
ECHANICAL
C
ONFIGURATION
...........................................................................................................40
F
IGURE
22: A
NALOG
P
IN
C
ONNECTION
.................................................................................................................... 41
F
IGURE
23: CLOCK GENERATION CIRCUIT...........................................................................................................41
F
IGURE
24: I2C W
RITE TO THE
HDM8515..............................................................................................................46
F
IGURE
25: I2C R
EAD FROM THE
HDM8515............................................................................................................47
F
IGURE
A1: S
YMBOL
T
IMING
R
ECOVERY
T
RANSIENT
R
ESPONSE
....................................................................... 67
F
IGURE
A2: C
ARRIER
P
HASE
R
ECOVERY
T
RANSIENT
R
ESPONSE
........................................................................ 68
F
IGURE
A3: C
ARRIER
P
HASE
R
ECOVERY
T
RANSIENT
R
ESPONSE WITH
L
OW
SNR ..........................................69
F
IGURE
A4: A
DJACENT
C
HANNEL
I
NTERFERENCE OF
10
D
B, 1.35 S
PACING
.................................................... 72
F
IGURE
A5: P
ERFORMANCE WITH INTERFERER AT DIFFERENT CARRIER SPACINGS
.....................................73
F
IGURE
A6: P
ERFORMANCE WITH
+10
D
B I
NTERFERER
......................................................................................74
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