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1
HL14203
P r e l i m i n a r y
H L 1 4 2 0 3
2Q. 1999
Hyundai Electronics Industries
System IC Division
Preliminary
LCD Driver IC
2
HL14203
P r e l i m i n a r y
Contents
1. General Description
2. Features
3. Block Diagram
4. Pin Diagram
5. Pin Description
6. Serial I/O Data Format
7. Registers
8. Key Scan Function
9. LCD Function
10. Power On Reset
11. Power Down Mode
12. Oscillator Port
13. Electrical Characteristics
14. Application
3
HL14203
P r e l i m i n a r y
1. General Description
The HL14203 is 1/3 duty LCD display driver. It can drive directly maximum
126 segments. Also it has four general purpose output ports and a key scan
function that accepts input from up to 30 keys.
2. Features
LCD display ..................................... 42 segments x 3 commons
1/3 duty - 1/2 bias
1/3 duty - 1/3 bias
Key scan ............................................ Maximum 30 keys
Input 5 pins, Output 6 pins
Power down mode ............................. Sleep mode and all segments off mode
Port
Output .................................................. 4 pins
( Including the LCD segment port )
Serial I/O .............................................. Data transfer and receive
Power on reset ..................................... Supply voltage detection ( SVD )
RC oscillator
Package ............................................... 64QFP
17.2
14.0
(1.6)
0.15
1.0
0.1
2.7
0.35
1.0
0.8
1
16
17
32
33
48
49
64
17.2
14.0
0.8
1.0
1.0
12.0
10.0
0.15
1.7max
0.18
1
16
17
32
33
48
49
64
12.0
10.0
0.5
1.25
1.25
0.1
0.5
0.5
Package Dimensions
64QFP (14
14)
64QFP (10
10)
Unit : mm
Unit : mm
(1.6)
4
HL14203
P r e l i m i n a r y
3. Block Diagram
CLOCK
GENERATOR
KEY
SCAN
COMMOM
DRIVER
LCD
BIAS
SVD
OSC
SEGMENT
DRIVER
COM3
COM2
COM1
KS2 / SEG42
KS1 / SEG41
SEG40
SEG5
SEG4 / P4
SEG1 / P1
LCD
DISPLAY & CONTROL
REGISTER
SERIAL
I/O
SI
SO
SCK
CE
VDD
VSS
RESET
CLOCK
KS6
KS5
KS4
KS3
KS2
KS1
KIN5
KIN4
KIN3
KIN2
KIN1
TEST
CONTROL
TEST
VCL1
VCL2
5
HL14203
P r e l i m i n a r y
4. Pin Diagram
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
KS6
KIN1
KIN2
KIN3
KIN4
KIN5
TEST
VDD
VCL1
VCL2
VSS
OSC
SO
CE
SCK
SI
HL14203
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SEG1 / P1
SEG2 / P2
SEG3 / P3
SEG4 / P4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
KS5
KS4
KS3
KS2 / SEG42
KS1 / SEG41
COM3
COM2
COM1
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
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HL14203
P r e l i m i n a r y
5. Pin Description
PIN Name
I/O
Pin Number
Contents
SEG[42:1]
O
42
LCD SEG Pins share P1,P2,P3 and P4
COM [3:1]
O
3
LCD Common Pins
OSC
I/O
1
Oscillator Input Pin
KS[6:1]
O
6
Key Scan Output Pins
KIN[5:1]
I
5
Key Scan Input Pins
CE
I
1
Serial I/O Control Pin
SCK
I
1
Serial I/O Clock Pin
SO
O
1
Serial I/O Data Output Pin
VDD
I
1
Power Supply Pin
VSS
I
1
Ground Pin
VCL[2:1]
I
2
LCD Bias Pins
SI
I
1
Serial I/O Data Input Pin
TEST
I
1
Test Pin. "1" Test mode , "0" Normal Mode
P[4:1]
O
4
Output Port share SEG[4:1]
7
HL14203
P r e l i m i n a r y
6. Serial I/O Data Format
1) Writing Mode
CE
SCK
SI
SO
0
1
0
0
0
0
1
0
D1
D2
D3
XX
A0 A1 A2 A3 A4 A5 A6 A7
D41 D42
0
0
0
0
S0
S1
K0
K1
P0
P1
SC
DR
0
0
Display data
Control data
DD
CE
SCK
SI
SO
0
1
0
0
0
0
1
0
D43
D44 D45
XX
A0 A1 A2 A3 A4 A5 A6 A7
D83 D84
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Display data
Fixed data
DD
CE
SCK
SI
SO
0
1
0
0
0
0
1
0
D85
D86 D87
XX
A0 A1 A2 A3 A4 A5 A6 A7
D125
D126
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Display data
Fixed data
DD
i )SCK is stopped at the low level
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HL14203
P r e l i m i n a r y
A7~A0 : 42H address
D126~D1 : Data of LCD display registers
S0, S1 : Sleep control data
K0, K1 : Key scan output / Segment output selection data
P0, P1 : Segment output / general-purpose output port selection data
SC : Segment on / off control data
DR : 1/2 bias or 1/3 bias drive selection data
ii )SCK is stopped at the high level
CE
SCK
SI
SO
1
0
0
0
0
1
0
0
D2
D3
XX
A0 A1 A2 A3 A4 A5 A6
A7
D41 D42
0
0
0
0
S0
S1
K0
K1
P0
P1
SC
DR
0
0
Display data
Control data
DD
D1
CE
SCK
SI
SO
1
0
0
0
0
1
0
0
D44 D45
XX
A0 A1 A2 A3 A4 A5 A6
A7
D83 D84
0
0
0
0
S0
S1
K0
K1
P0
P1
SC
DR
0
1
Display data
Fixed data
DD
D43
CE
SCK
SI
SO
1
0
0
0
0
1
0
0
D86 D87
XX
A0 A1 A2 A3 A4 A5 A6
A7
D125 D126
0
0
0
0
S0
S1
K0
K1
P0
P1
SC
DR
1
0
Display data
Fixed data
DD
D85
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HL14203
P r e l i m i n a r y
2) Reading Mode
A7 ~ A0 : 43H address
K30 ~ K1 : Key data
SA : Sleep acknowledge
i ) SCK is stopped at the low level
CE
SCK
SI
SO
0
1
0
0
0
0
1
1
XX
XX
K1 K2 K3 K4 K5 K6 K7 K8 K9
K11
K29
K10
K30
XX
K12
SA
XX
A7
A5
A3
A1
A6
A4
A2
A0
Output data
X : don't care
CE
SCK
SI
SO
1
0
0
0
0
1
1
XX
XX
K1
K2 K3 K4 K5 K6 K7 K8 K9
K11
K29
K10
K30
XX
K12
SA
XX
A7
A5
A3
A1
A6
A4
A2
A0
Output data
X : don't care
ii ) SCK is stopped at the high level
0
10
HL14203
P r e l i m i n a r y
7. Registers
1) Display Registers
Output Pin
COM1
COM2
COM3
SEG1
D1
D2
D3
SEG2
D4
D5
D6
SEG3
D7
D8
D9
SEG4
D10
D11
D12
SEG5
D13
D14
D15
SEG6
D16
D17
D18
SEG7
D19
D20
D21
SEG8
D22
D23
D24
SEG9
D25
D26
D27
SEG10
D28
D29
D30
SEG11
D31
D32
D33
SEG12
D34
D35
D36
SEG13
D37
D38
D39
SEG14
D40
D41
D42
SEG15
D43
D44
D45
SEG16
D46
D47
D48
SEG17
D49
D50
D51
SEG18
D52
D53
D54
SEG19
D55
D56
D57
SEG20
D58
D59
D60
SEG21
D61
D62
D63
SEG22
D64
D65
D66
SEG23
D67
D68
D69
SEG24
D70
D71
D72
SEG25
D73
D74
D75
SEG26
D76
D77
D78
SEG27
D79
D80
D81
SEG28
D82
D83
D84
SEG29
D85
D86
D87
SEG30
D88
D89
D90
SEG31
D91
D92
D93
SEG32
D94
D95
D96
SEG33
D100
D101
D102
SEG34
D103
D104
D105
SEG35
D106
D107
D108
SEG36
D109
D110
D111
SEG37
D112
D113
D114
SEG38
D115
D116
D117
SEG39
D118
D119
D120
SEG40
D121
D122
D123
SEG41
D124
D125
D126
SEG42
D97
D98
D99
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HL14203
P r e l i m i n a r y
2) Control Registers
Bias Selection
1/3 Bias
Bias Selection Register
Sleep Mode Control Register
DR
0
1
1/2 Bias
Key Scan / Segment output Selection Register
Port Mode Register
Port Data Register
Maximum number of Input Pins
Control Data
K0
K1
0
0
0
1
1
X
Output Pin Status
KS1/SEG41 KS2/SEG42
KS1
KS2
SEG41
KS2
SEG41
SEG42
30
25
20
Control Data
P0
P1
0
0
0
1
1
0
Output Pin Status
SEG1/ P1
SEG2/ P2
SEG1
SEG2
P1
P2
P1
P2
1
1
SEG3/ P3
SEG4/ P4
SEG3
SEG4
SEG3
SEG4
P3
SEG4
P1
P2
P3
P4
Output Pin
SEG1 / P1
SEG2 / P2
SEG3 / P3
SEG4 / P4
Port Data Register
D1
D4
D7
D10
Control Data
S0
S1
0
0
0
1
1
0
1
1
Operating
Stopped
Stopped
Stopped
Normal
Sleep
Sleep
Sleep
Mode
OSC
Oscillator
Output Pin Status
KS1 KS2
H
H
L
L
L
L
H
H
KS3 KS4
H
H
L
L
L
L
H
H
KS5 KS6
H
H
L
H
H
H
H
H
Operating
L
L
L
SEG / COMMON
Output
12
HL14203
P r e l i m i n a r y
Display On/Off Control Register
ADDRESS
Read Data
K1 ~ K30, SA
43H
Key Scan Data & Sleep Acknowledge Read
Control Data
SC
0
1
Display Status
On
Off
SEG1 ~ SEG42
KS1 / SEG41
KS2 / SEG42
KS3
KS4
KS5
KS6
KIN1
KIN1
KIN1
KIN1
KIN1
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
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HL14203
P r e l i m i n a r y
8. Key Scan Function
1) Key Scan Timing
The key scan period is 384T. The HL14203 scans the key twice and determines
that a key has been pressed when the key data agrees. It outputs a key data read
request 800T after starting a key scan. If the key data does not agree and a key
was pressed at that point, it scans the key again.Thus the HL14203 cannot detect
a key press shorter than 800T.
768T
KS1
KS2
KS3
KS4
KS5
KS6
1
2
3
4
5
6
1
2
3
4
5
6
Key on
*)
*)
*)
*)
*)
*)
*)
*)
*)
*)
*)
*)
*) In sleep mode the high / low state of these pins is determined by the S0,S1 bits in the control data.
Key scan output signals are not output from pins that are set low.
2) In normal mode
The pins KS1 to KS6 are set high.
When a key is pressed a key scan is started and the keys are scanned until all
keys are released. Multiple key presses are recognized by determining whether
multiple key data bits are set.
If a key is pressed for longer than 800T ( where T=1/fosc ) the HL14203
outputs a key data read request (a low level on SO pin) to the controller. The
controller acknowledges this request and reads the key data. However, if CE
is high during a serial data transfer, SO will be set high.
After the controller reads the key data, the key data read requests is cleared (
SO pin is set high ) and the HL14203 performs another key scan. Also note
that SO pin, being an open-drain output, requires a pull-up resistor.
14
HL14203
P r e l i m i n a r y
Key input 1
3) In sleep mode
The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the
sleep mode control register.
If a key on one of the lines corresponding to a KS1 to KS6 pin which is set
high is pressed, the oscillator on the OSC pin is started and a key scan is
performed. Keys are scanned until all keys are released. Multiple key pre-
sses are recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 800T ( where T=1/fosc ) the HL14203
outputs a key data read request (a low level on SO) to the controller. The
controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, SO will be set high.
After the controller reads the key data, the key data read request is cleared
( SO is set high ) and the HL14203 performs another key scan. However
this does not clear sleep mode. Also note that SO, being an open-drain
output, requires a pull-up resistor ( between 1 and 10 K).
Sleep mode key scan example
Example : S0 = 0, S1 = 1 ( sleep with only KS6 high )
Key input 2
Key Scan
CE
SI
SO
800T
800T
800T
Write
address
Write
address
Read
address
Write
address
Read
address
Read
address
Key data read request
Key data read
Key data read
Key data read
Key data read request
Key data read request
15
HL14203
P r e l i m i n a r y
Key input
(KS6 line)
Key Scan
CE
SI
SO
800T
800T
Write
address
Write
address
Read
address
Write
address
Read
address
Key data read request
Key data read
Key data read
Key data read request
"L" KS1
"L" KS2
"L" KS3
"L" KS4
"L" KS5
"H" KS6
KIN1
KIN2
KIN3
KIN4
KIN5
*)
When any one of these keys is pressed, the
oscillator on the OSC pin is started and the keys
are scanned.
*) These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only
KS6 high, as in the above example. That is, these diodes prevent incorrect operation due to sneak currents in the KS6
key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.
Multiple Key Presses
Although the HL14203 is capable of key scanning without inserting diodes for
dual key presses, triple key presses on the KIN1 to KIN5 input pin lines, or mult-
iple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been
pressed. Therefore, a diode must be inserted in series with each key. Application
that do not recognize multiple key presses of threes or keys should check the key
data for three or more 1 bits and ignore such data.
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HL14203
P r e l i m i n a r y
9. LCD Display Function
COM1
1) 1/3 Duty 1/2 Bias Waveforms
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
COM2
VCL1,VCL2
0
VDD
COM3
VCL1,VCL2
0
VDD
SEG1 ~ SEG42
"Off" at COM1
~ COM3
SEG1 ~ SEG42
"On" at COM1
~ COM3
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
SEG1 ~ SEG42
"On" at COM1
only
SEG1 ~ SEG42
"On" at COM2
only
SEG1 ~ SEG42
"On" at COM3
only
SEG1 ~ SEG42
"On" at COM1
and COM2
SEG1 ~ SEG42
"On" at COM1
and COM3
SEG1 ~ SEG42
"On" at COM2
and COM3
17
HL14203
P r e l i m i n a r y
COM1
2) 1/3 Duty 1/3 Bias Waveforms
COM2
COM3
SEG1 ~ SEG42
"Off" at COM1
~ COM3
SEG1 ~ SEG42
"On" at COM1
~ COM3
SEG1 ~ SEG42
"On" at COM1
only
SEG1 ~ SEG42
"On" at COM2
only
SEG1 ~ SEG42
"On" at COM3
only
SEG1 ~ SEG42
"On" at COM1
and COM2
SEG1 ~ SEG42
"On" at COM1
and COM3
SEG1 ~ SEG42
"On" at COM2
and COM3
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
18
HL14203
P r e l i m i n a r y
10. Power On Reset
1) Supply Voltage Detection ( SVD )
The SVD generates an output signal and resets the system when power is
first applied and when the voltage drops, I.e.,when the power supply voltage is
less than or equal to the power down detection voltage, which is 2.5V, typical.
To assure that this function operates reliably, a capacitor must be added to the
power supply voltage Vdd rise time when power is first applied and the power
supply voltage Vdd fall time when the voltage drops are both at least 1ms.
2) System Reset
If at least 1ms is assured as the supply voltage Vdd rise time when power is
applied, a system reset will be applied by the SVD output signal when the supply
voltage is brought up. If at least 1ms is assured as the supply voltage Vdd fall
time when power drops, a system reset will be applied in the same manner by
the SVD output signal when the supply voltage is lowered.
t1
t2
Power supply voltage Vdd rise time : t1 > 1ms
Power supply voltage Vdd fall time : t2 > 1ms
3) Internal block states during the reset period
Clock generator
Reset is applied and the base clock is stopped and OSC pin state is low.
Common , segment drive and display data
Reset is applied and the display is turned off but display data is not cleared.
Key scan
Reset is applied and all the key data is set to low.
Display and control data transfer
Undefined
System reset period
Defined
VDD
CE
Internal data
SVD
SVD
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HL14203
P r e l i m i n a r y
11. Power Down Mode
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment
outputs will all go low and the common outputs will also go low, and the oscillator
on the OSC pin will stop ( it will be started by a key press). This reduces power
dissipation. This mode is cleared by sending control data with both S0 and S1 set
to 0. Note that the SEG1/P1 to SEG4/P4 outputs can be used as general purpose
output ports according to the state of the P0 and P1 control data bits, even in
sleep mode.
4) Output pin states during the reset period
SEG1/P1 to SEG4/P4 : Low *)
SEG5 to SEG40 : Low
COM1 to COM3 : Low
KS1/SEG41, KS2/SEG42 : Low *)
KS3 to KS5 : X
KS6 : High
SO : High
*) These output pins are forcibly set to the segment output function and held low.
20
HL14203
P r e l i m i n a r y
OSC
SLEEP
OSC Pin Diagram
12. Oscillator Port
Internal clock
C
R
Oscillator circuit consists of internal R and C.
No Capacitor
OSC
Open
OSC
Using Capacitor
C
HL14203 has internal resistor and capacitor, so it can be oscillation without external capacitor.
If you want to adjust the clock period then you can adjust it using external capacitor.
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HL14203
P r e l i m i n a r y
Absolute
Maximum
Rating at Ta=25
, Vss = 0V
13. Electrical Characteristics
Parameter
Symbol
Condition
Maximum supply voltage
VDD max
VDD
Rating
unit
-0.3 to +7.0
V
Input voltage
Vin1
CE,SCK,SI
-0.3 to +7.0
V
Vin2
OSC,KIN1 to KIN5, TEST,VCL1,2
-0.3 to VDD+0.3
V
Output voltage
Vout1
SO
-0.3 to +7.0
V
Vout2
OSC, SEG1 to SEG42, COM1 to
COM3, KS1 to KS6, P1 to P4
-0.3 to VDD+0.3
V
Output current
Iout1
SEG1 to SEG42
300
uA
Iout2
COM1 to COM3
3
mA
Iout3
KS1 to KS6
1
mA
Iout4
P1 to P4
5
mA
Allowable power dissipation
Pd max
Ta = 85
200
mW
Operating temperature
Topr
-40 to +85
Storage temperature
Tstg
-55 to +125
Recommend operating ranges at Ta= -40
to +85
, Vss = 0V
Note : *1.Since SO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and
load capacitance CL .
Parameter
Symbol
Condition
Supply voltage
VDD
unit
V
Input voltage
VCL1
V
VCL2
V
Input high level voltage
VIH1
V
VIH2
pF
COSC
Guaranteed oscillation range
KHz
Data setup time
ns
Data hold time
ns
VIL
Input low level voltage
Recommended external
capacitance
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
Fall time
SO output delay time
SO rise time
fOSC
tds
tdh
tcp
tcs
tch
t0H
toL
tr
tf
tdc
tdr
V
V
max
6.0
VDD
VDD
6.0
TBD
VDD
0.2VDD
typ
2/3VDD
1/3VDD
TBD
38
min
4.5
0.8VDD
TBD
160
160
0.6VDD
0
VDD
VCL1
VCL2
CE,SCK,SI
KIN1 to KIN5
CE,SCK,SI,KIN1 to KIN5
OSC
SO,RPU = 4.7k
,
CL = 10pF*1
SO,RPU = 4.7k
,
CL = 10pF*1
OSC
SCK,SI
SCK,SI
CE,SCK
CE,SCK
CE,SCK
SCK
SCK
CE,SCK,SI
CE,SCK,SI
ns
ns
ns
ns
ns
160
160
160
160
160
ns
160
ns
160
s
1.5
s
1.5
22
HL14203
P r e l i m i n a r y
Note : *2. Excluding the bias voltage generation divider resistor built into VCL1 and VCL2
Parameter
Symbol
Condition
Hysteresis
VH
unit
V
Supply voltage detection
SVD
V
IIH
A
Input high level current
IIL
A
VIF
Input floating voltage
A
Pull-down resistance
V
Output off leakage current
V
RPD
Input low level current
Output high level voltage
Output low level voltage
Output middle level voltage*2
IOFFH
VOH1
VOH2
VOH3
VOH4
VOL1
VOL2
VOL3
VOL4
VOL5
VMID1
VMID2
V
k
max
TBD
5.0
6.0
VDD -0.2
0.05VDD
250
min
TBD
-5.0
VDD -1.2
VDD -1.0
50
CE,SCK,SI
CE,SCK,SI : V1 = 6.0V
CE,SCK,SI : V1 = 0V
KIN1 to KIN5
KIN1 to KIN5 : VDD = 5.0V
COM to COM3 : 1/2 bias,
Io =
100A
SEG1 to SEG42 : 1/3 bias,
Io =
20A
SO : VO = 6.0V
KS1 to KS6 : I0 = -500A
P1 to P4 : I0 = -1mA
SEG1 to SEG42 : I0 = -20A
COM1 to COM3 : I0= -100A
SO : I0 = 1 mA
V
V
V
V
V
1.5
1.0
1.0
VDD -1.0
0.2
V
1.0
V
0.5
V
1/2 VDD
-1.0
V
2/3VDD
-1.0
Electrical Characteristics for the Allowable Operating Ranges
KS1 to KS6 : I0 = 25A
P1 to P4 : I0 = 1mA
SEG1 to SEG42 : I0 = 20A
COM1 to COM3 : I0 = 100A
SEG1 to SEG42 : 1/3 bias,
Io =
20A
COM to COM3 : 1/3 bias,
Io =
100A
COM to COM3 : 1/3 bias,
Io =
100A
VMID3
VMID4
VMID5
V
1/3VDD
-1.0
V
2/3VDD
-1.0
V
1/3VDD
-1.0
Oscillator frequency
fOSC
KHz
TBD
TBD
OSC : C = TBD
typ
O.1VDD
2.5
VDD -0.5
100
0.5
0.1
38
VDD -1.0
1/2VDD
+1.0
2/3VDD
+1.0
1/3VDD
+1.0
2/3VDD
+1.0
1/3VDD
+1.0
Current drain
IDD1
A
100
Sleep mode
IDD2
A
700
VDD = 6.0V, output open,
1/2 bias,fOSC = 38 KHz
350
IDD3
A
600
VDD = 6.0V, output open,
1/3 bias,fOSC = 38 KHz
300
23
HL14203
P r e l i m i n a r y
Timing diagram of SIO
CE
t0H
t0L
SCK
tr
tf
tds
tdh
SI
CE
SCK
SI
SO
VIH1
tcp
tcs
tdc
tdr
VIL
tch
SO
24
HL14203
P r e l i m i n a r y
14. Application
LCD panel (up to 126 segments
.
.
.
.
.
COM1
COM2
COM3
P1 / SEG1
P2 / SEG2
P3 / SEG3
P4 / SEG4
SEG5
SEG40
S
E
G
4
1
/
K
S
1
S
E
G
4
2
/
K
S
2
K
S
6
K
S
5
K
S
4
K
S
3
(SEG41)
(SEG42)
CE
SCK
SI
SO
VCL1
VCL2
VDD
VSS
TEST
OSC
K
I
N
5
K
I
N
4
K
I
N
3
K
I
N
2
K
I
N
1
+5V
From the controller
To the controller
To the controller
power supply
*2)
(p 1)
(p 2)
(p 3)
(p 4)
(general-purpose
output ports)
Used with the
backlight controller
or other circuit.
.
.
.
.
.
Key matrix
(up to 30 keys)
Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the
HL14203 is reset by the SVD.
*2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k
)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
1/2 bias ( for use with normal panels )
C
0.047uF
*1)
C
25
HL14203
P r e l i m i n a r y
LCD panel (up to 126 segments
.
.
.
.
.
COM1
COM2
COM3
P1 / SEG1
P2 / SEG2
P3 / SEG3
P4 / SEG4
SEG5
SEG40
S
E
G
4
1
/
K
S
1
K
S
6
K
S
5
K
S
4
K
S
3
CE
SCK
SI
SO
VCL1
VCL2
VDD
VSS
TEST
OSC
K
I
N
5
K
I
N
4
K
I
N
3
K
I
N
2
K
I
N
1
+5V
From the controller
To the controller
To the controller
power supply
*2)
(p 1)
(p 2)
(p 3)
(p 4)
(general-purpose
output ports)
Used with the
backlight controller
or other circuit.
.
.
.
.
.
Key matrix
(up to 30 keys)
Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the
HL14203 is reset by the SVD.
*2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k
)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
1/3 bias ( for use with normal panels )
C
0.047uF
*1)
C
C
S
E
G
4
1
/
K
S
2
(SEG42)
(SEG41)
26
HL14203
P r e l i m i n a r y
LCD panel (up to 126 segments
.
.
.
.
.
COM1
COM2
COM3
P1 / SEG1
P2 / SEG2
P3 / SEG3
P4 / SEG4
SEG5
SEG40
K
S
6
K
S
5
K
S
4
K
S
3
CE
SCK
SI
SO
VCL1
VCL2
VDD
VSS
TEST
OSC
K
I
N
5
K
I
N
4
K
I
N
3
K
I
N
2
K
I
N
1
+5V
From the controller
To the controller
To the controller
power supply
*2)
(p 1)
(p 2)
(p 3)
(p 4)
(general-purpose
output ports)
Used with the
backlight controller
or other circuit.
.
.
.
.
.
Key matrix
(up to 30 keys)
Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is
applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the
HL14203 is reset by the SVD.
*2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k
)
appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
1/3 bias ( for use with large panels )
C
0.047uF
*1)
S
E
G
4
1
/
K
S
1
S
E
G
4
1
/
K
S
2
C
C
R
R
R
(SEG42)
(SEG41)
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