HL15203
P r e l i m i n a r y
1
H L 1 5 2 0 3
2Q. 1999
Hyundai Electronics Industries
System IC Division
Preliminary
LCD Driver IC
HL15203
P r e l i m i n a r y
2
Contents
1. General Description
2. Features
3. Block Diagram
4. Pin Diagram
5. Pin Description
6. Serial I/O Data Format
7. Registers
8. Key Scan Function
9. LCD Function
10. INH and Display Control
11. Power Down Mode
12. Oscillator Port
13. Electrical Characteristics
14. Application
HL15203
P r e l i m i n a r y
3
1. General Description
The HL15203 is 1/3 duty LCD display driver. It can drive directly maximum
156 segments.
2. Features
LCD display ..................................... 52 segments x 3 commons
1/3 duty - 1/2 bias
1/3 duty - 1/3 bias
Power down mode .............................. Sleep mode and all segments off mode
Serial I/O .............................................. Data transfer and receive
RC oscillator
Package ............................................... 64QFP
0.15
0.1
Package Dimensions
64QFP(14
14)
Unit : mm
2.70
17.2
0.8
17.2
14.0
1.0
1
16
17
32
33
48
64
1.0
0.8
1.0
1.0
1.6
0.35
49
1.6
0.15
0.1
0.5
1.25
1.25
0.35
1.7max
0.5
0.5
14.0
12.0
10.0
12.0
10.0
Unit : mm
64QFP(12
12)
16
17
32
33
48
49
64
1
HL15203
P r e l i m i n a r y
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3. Block Diagram
COMMON
DRIVER
CLOCK
GENERATOR
LATCH & DRIVER
SHIFT REGISTER
ADDRESS
DETECTOR
VCL1
VCL2
INH
VDD
VSS
OSC
COM1
COM2
COM3
SEG52
SEG51
.
.
.
.
.
.
.
.
.
.
.
SEG1
SI
SCK
CE
4. Pin Diagram
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG49
SEG50
SEG51
SEG52
COM1
COM2
COM3
VDD
INH
VCL1
VCL2
VSS
OSC
CE
SCK
SI
1
32
16
17
64
33
48
49
HL15203
HL15203
P r e l i m i n a r y
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5. Pin Description
PIN Name
I/O
Pin Number
Contents
SEG[52:1]
O
52
LCD SEG Pins
COM [3:1]
O
3
LCD Common Pins
OSC
I
1
Oscillator Input Pin
CE
I
1
Serial I/O Control Pin
SCK
I
1
Serial I/O Clock Pin
VDD
I
1
Power Supply Pin
VSS
I
1
Ground Pin
VCL[2:1]
I
2
LCD Bias Pins
INH
I
1
Display off control pin
SI
I
1
Serial I/O Data Input Pin
HL15203
P r e l i m i n a r y
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DATA Writing
ADDRESS : 41H
D1 ~ D156 : Display data
Dn(n=1~156)=1 ... ... ...
.. Display on
Dn(n=1~156)=0 ... ... ...
.. Display off
DR : 1/2-bias drive or 1/3-bias drive switching control data
SC : Segments on/off control data
BU : Normal mode/power-saving mode control data
i ) SCK is stopped at the low level
CE
SCK
SI
0
1
0
0
0
0
1
1
XX
D2
D3
A7
A5
A3
A1
A6
A4
A2
A0
ii ) SCK is stopped at the high level
D154 D155 D156
DR
BU
SC
D1
Address
8 bits
Display data
156bits
Control data
4 bits
CE
SCK
SI
0
1
0
0
0
0
0
1
XX
D2
D3
A7
A5
A3
A1
A6
A4
A2
A0
D154 D155 D156
DR
BU
SC
D1
Address
8 bits
Display data
156bits
Control data
4 bits
HL15203
P r e l i m i n a r y
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DATA Writing Examples
CE
SCK
SI
0
1
0
0
0
0
1
1
XX
D12 D13
A7
A5
A3
A1
A6
A4
A2
A0
D154 D155 D156
DR
BU
SC
D11
Address
8 bits
Display data
146bits
Control data
4 bits
CE
SCK
SI
0
1
0
0
0
0
0
1
XX
D121 D122
A7
A5
A3
A1
A6
A4
A2
A0
D154 D155 D156
DR
BU
SC
D120
Address
8 bits
Display data
37bits
Control data
4 bits
CE
SCK
SI
0
1
0
0
0
0
1
1
XX
D36 D37
A7
A5
A3
A1
A6
A4
A2
A0
D154 D155 D156
DR
BU
SC
D35
Address
8 bits
Display data
122bits
Control data
4 bits
i ) When 146 segments are used 146bits of display data (D11 to D156) must be sent.
ii ) When 122 segments are used 122bits of display data (D35 to D156) must be sent.
iii ) When 37 segments are used 37bits of display data (D120 to D156) must be sent.
HL15203
P r e l i m i n a r y
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7. Registers
1) Display Registers
Output Pin
COM3
COM2
COM1
SEG1
D1
D2
D3
SEG2
D4
D5
D6
SEG3
D7
D8
D9
SEG4
D10
D11
D12
SEG5
D13
D14
D15
SEG6
D16
D17
D18
SEG7
D19
D20
D21
SEG8
D22
D23
D24
SEG9
D25
D26
D27
SEG10
D28
D29
D30
SEG11
D31
D32
D33
SEG12
D34
D35
D36
SEG13
D37
D38
D39
SEG14
D40
D41
D42
SEG15
D43
D44
D45
SEG16
D46
D47
D48
SEG17
D49
D50
D51
SEG18
D52
D53
D54
SEG19
D55
D56
D57
SEG20
D58
D59
D60
SEG21
D61
D62
D63
SEG22
D64
D65
D66
SEG23
D67
D68
D69
SEG24
D70
D71
D72
SEG25
D73
D74
D75
SEG26
D76
D77
D78
SEG27
D79
D80
D81
SEG28
D82
D83
D84
SEG29
D85
D86
D87
SEG30
D88
D89
D90
SEG31
D91
D92
D93
SEG32
D94
D95
D96
SEG33
D100
D101
D102
SEG34
D103
D104
D105
SEG35
D106
D107
D108
SEG36
D109
D110
D111
SEG37
D112
D113
D114
SEG38
D115
D116
D117
SEG39
D118
D119
D120
SEG40
D121
D122
D123
SEG41
D124
D125
D126
SEG42
D97
D98
D99
HL15203
P r e l i m i n a r y
9
Output Pin
COM3
COM2
COM1
SEG43
D127
D128
D129
SEG44
D130
D131
D132
SEG45
D133
D134
D135
SEG46
D136
D137
D138
SEG47
D139
D140
D141
SEG48
D142
D143
D144
SEG49
D145
D146
D147
SEG50
D148
D149
D150
SEG51
D151
D152
D153
SEG52
D154
D155
D156
2) Control Registers
Bias Selection
1/3 Bias
i) 1/2-bias drive or 1/3-bias drive switching control data
DR
0
1
1/2 Bias
ii) Segments on/off control data
Control Data
SC
0
1
Display Status
On
Off
SEG1 ~ SEG52
Mode
Normal Mode
BU
0
1
Power-saving mode. In this mode the OSC pin oscillator is stopped
and the common and segment pins output Vss levels.
iii) Normal mode/power-saving mode control data
HL15203
P r e l i m i n a r y
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9. LCD Display Function
COM1
1) 1/2 Bias, 1/3 Duty Waveforms
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
COM2
VCL1,VCL2
0
VDD
COM3
VCL1,VCL2
0
VDD
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are turned off.
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
VCL1,VCL2
0
VDD
LCD driver output when all
LCD segments corresponding
to COM1 are on.
LCD driver output when all
LCD segments corresponding
to COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are on.
HL15203
P r e l i m i n a r y
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COM1
2) 1/3 Duty 1/3 Bias Waveforms
COM2
COM3
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
VDD
VCL1
VCL2
0
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are turned off.
LCD driver output when all
LCD segments corresponding
to COM1 are on.
LCD driver output when all
LCD segments corresponding
to COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when all
LCD segments corresponding
to COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when all
LCD segments corresponding
to COM1, COM2, and COM3
are on.
HL15203
P r e l i m i n a r y
12
10. INH and Display Control
Since the LSI internal data (D1 to D156, DR, SC, and BU) is undefined when
power is first applied, then display is off(SEG1 to SEG52,COM1 to COM3=low)
by setting the INH pin low at the same time as power is applied.Then meaningless
display at the power-on can be prevented by transferring serial data from the
controller while the display is off and setting INH pin high after the transfer completes.
Transfer of display
and control data
Undefined
Defined
VDD
CE
Internal data
INH
VDD
R
C
INH
VIL
VIL
t1
t2
t1 : Determined by the value of C and R
t2 : 10
s(minimum)
HL15203
P r e l i m i n a r y
13
11. Power Down Mode
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment
outputs will all go low and the common outputs will also go low, and the oscillator
on the OSC pin will stop ( it will be started by a key press). This reduces power
dissipation. This mode is cleared by sending control data with both S0 and S1 set
to 0. Note that the SEG1 to SEG4 outputs can be used as general purpose output
ports according to the state of the P0 and P1 control data bits, even in sleep
mode.
HL15203
P r e l i m i n a r y
14
OSC
SLEEP
OSC Pin Diagram
12. Oscillator Port
Internal clock
C
R
Oscillator circuit consists of internal R and C.
No Capacitor
OSC
Open
OSC
Using Capacitor
C
HL15203 has internal resistor and capacitor, so it can be oscillation without external capacitor.
If you want to adjust the clock period then you can adjust it using external capacitor.
HL15203
P r e l i m i n a r y
15
Absolute
Maximum
Rating at Ta=25
, Vss = 0V
13. Electrical Characteristics
Parameter
Symbol
Condition
Maximum supply voltage
VDD max
VDD
Rating
unit
-0.3 to +6.5
V
Input voltage
Vin1
CE,SCK,SI,INH
-0.3 to +6.5
V
Vin2
OSC
-0.3 to VDD+0.3
V
Output voltage
Vout
OSC
-0.3 to VDD+0.3
V
Output current
Iout1
SEG1 to SEG52
300
uA
Iout2
COM1 to COM3
3
mA
Allowable power dissipation
Pd max
Ta = 85
200
mW
Operating temperature
Topr
-40 to +85
Storage temperature
Tstg
-55 to +125
Recommend operating ranges at Ta= -40
to +85
, Vss = 0V
Parameter
Symbol
Condition
Supply voltage
VDD
unit
V
Input voltage
VCL1
V
VCL2
V
Input high level voltage
VIH
V
pF
COSC
Guaranteed oscillation range
KHz
Data setup time
ns
Data hold time
ns
VIL
Input low level voltage
Recommended external
capacitance
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
Fall time
INH switching time
f
OSC
tds
tdh
tcp
tcs
tch
t0h
tol
tr
tf
t2
V
max
6.0
6.0
6.0
6.0
76
0.7
typ
2/3VDD
1/3VDD
TBD
38
min
4.5
4.0
19
100
100
0
VDD
VCL1
VCL2
CE,SCK,SI,INH
CE,SCK,SI,INH
OSC
INH,CE
OSC
SCK,SI
SCK,SI
CE,SCK
CE,SCK
CE,SCK
SCK
SCK
CE,SCK,SI
CE,SCK,SI
ns
ns
ns
ns
ns
100
100
100
100
100
ns
100
ns
100
s
10
HL15203
P r e l i m i n a r y
16
Note : *2. Except the bias voltage generation divider resistor that are built into VCL1 and VCL2
Parameter
Symbol
Condition
Hysteresis width
VH
unit
V
I
IH
A
Input high level current
I
IL
A
V
V
Input low level current
Output high level voltage
Output low level voltage
Intermediate level voltage*
VOH1
VOH2
VOL1
VOL2
VMID1
VMID2
max
5.0
min
-5.0
VDD -1.0
VDD -1.0
CE,SCK,SI,INH,VDD=5V
CE,SCK,SI,INH : V1 = 6.0V
CE,SCK,SI INH: V1 = 0V
1/2 bias, COM1 to COM3:
Io =
100A
1/3 bias, COM1 to COM3:
Io =
100A
SEG1 to SEG52 : IO = -20 A
SEG1 to SEG52 : IO = 20 A
V
V
1.0
1.0
V
1/2 VDD
1.0
V
2/3VDD
1.0
Electrical Characteristics for the Allowable Operating Ranges
COM1 to COM3 : IO = -100 A
COM1 to COM3 : IO = 100 A
1/2 bias, COM1 to COM3:
Io =
100A
1/3 bias ,SEG1 to SEG52 :
Io =
20A
1/3 bias ,SEG1 to SEG52 :
Io =
20A
VMID3
VMID4
VMID5
V
1/3VDD
1.0
V
2/3VDD
1.0
V
1/3VDD
1.0
Oscillator frequency
f
OSC
kHz
OSC : C = TBD
typ
38
Supply Current
IDD1
A
5
Power saving mode
IDD2
A
800
f
OSC
= 38 kHz,1/2bias,VDD = 5V
400
IDD2
A
1300
f
OSC
= 38 kHz,1/2bias,VDD = 6V
650
IDD3
A
600
f
OSC
= 38 kHz,1/3bias,VDD = 5V
300
IDD3
A
1200
f
OSC
= 38 kHz,1/3bias,VDD = 6V
580
0.3
HL15203
P r e l i m i n a r y
17
Timing diagram of SIO
CE
t0h
t0l
SCK
tr
tf
tds
tdh
SI
CE
SCK
SI
VIH
tcp
tcs
VIL
tch
VIH
VIL
VIL
VIH
HL15203
P r e l i m i n a r y
18
14. Application
LCD panel (up to 156 segments)
COM1
COM2
COM3
SCK
SI
VCL1
VCL2
VDD
INH
VSS
OSC
VDD
From the
microcontroller
1/3 bias ( for use with small panels )
OPEN
CE
SEG1
.
.
.
.
.
.
SEG52
LCD panel (up to 156 segments)
COM1
COM2
COM3
SCK
SI
VCL1
VCL2
VDD
INH
VSS
OSC
VDD
From the
microcontroller
1/3 bias ( for use with normal panels )
C
0.047uF
C
CE
C
SEG1
.
.
.
.
.
.
SEG52
HL15203
P r e l i m i n a r y
19
1/3 bias ( for use with large panels )
LCD panel (up to 156 segments)
COM1
COM2
COM3
SCK
SI
VCL1
VCL2
VDD
INH
VSS
OSC
VDD
From the
microcontroller
10 K
R
1 K
C
0.047uF
CE
C
SEG1
.
.
.
.
.
.
SEG52
C
R
R
R
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