HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Table of Contents

1. OVERVIEW ...........................................1

Description .........................................................1
Features .............................................................1
Development Tools ............................................ 2

2. BLOCK DIAGRAM ..............................3
3. PIN ASSIGNMENT (Top View) ........... 4
4. PACKAGE DIMENSION .......................5
5. PIN FUNCTION .....................................8
6. PORT STRUCTURES .........................10
7. ELECTRICAL CHARACTERISTICS ...12

Absolute Maximum Ratings .............................12
Recommended Operating Conditions ..............12
DC Electrical Characteristics ............................12
REMOUT Port Ioh Characteristics Graph ........13
REMOUT Port Iol Characteristics Graph .........14
AC Characteristics ...........................................14

8. MEMORY ORGANIZATION ................16

Registers ..........................................................16
Program Memory .............................................19
Data Memory ....................................................22
List for Control Registers.................................. 23
Addressing Mode .............................................25

9. I/O PORTS ..........................................30

R0 Ports ........................................................... 30
R1 Ports ...........................................................30
R2 Port .............................................................32

10. CLOCK GENERATOR ......................33

Oscillation Circuit .......................................... 34

11. BASIC INTERVAL TIMER ................36
12. WATCH DOG TIMER .......................38
13. Timer0, Timer1, Timer2 ....................39
14. INTERRUPTS ...................................47

Interrupt priority and sources ........................ 48
Interrupt control register ................................ 48
Interrupt accept mode ................................... 49
Interrupt Sequence ........................................ 50
BRK Interrupt ................................................ 52
Multi Interrupt ................................................ 52
External Interrupt ........................................... 52
Key Scan Input Processing ........................... 53

15.STANDBY FUNCTION ......................55

Sleep Mode .................................................... 55
STOP MODE .................................................. 55
STANDBY MODE RELEASE ......................... 56
RELEASE OPERATION OF STANDBYMODE58

16. RESET FUNCTION ..........................60

EXTERNAL RESET ...................................... 60
POWER ON RESET ..................................... 60
Low Voltage Detection Mode ........................ 62

A. MASK ORDER SHEET ........................ i
B. INSTRUCTION .................................... ii

Terminology List ...............................................ii

Instruction Map ................................................. iii
Instruction Set ..................................................iv

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

HMS81004E/08E/16E/24E/32E

CMOS SINGLE- CHIP 8-BIT MICROCONTROLLER

FOR UNIVERSAL REMOTE CONTROLLER

1. OVERVIEW

1.1 Description

The HMS81004E/08E/16E/24E/32E is an advanced CMOS 8-bit microcontroller with 4/8/16/24/32K bytes of ROM. The
device is one of GMS800 family. The HYNIX HMS81004E/08E/16E/24E/32E is a powerful microcontroller which provides
a highly flexible and cost effective solution to many UR applications.The HMS81004E/08E/16E/24E/32E provides the fol-
lowing standard features: 4/8/16/24/32K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock
circuitry. In addition, the HMS81004E/08E/16E/24E/32E supports power saving modes to reduce power consumption.

1.2 Features

· Instruction Cycle Time:

- 1us at 4MHz

· Programmable I/O pins

· Operating Voltage

- 2.0 ~ 3.6 V @ 4MHz (MASK)
- 2.0 ~ 4.0 V @ 4MHZ (OTP)

· Timer

- Timer / Counter ......... 16Bit * 1ch
......... 8Bit * 2ch
- Basic Interval Timer ...... 8Bit * 1ch

- Watch Dog Timer ............ 6Bit * 1ch

· 8 Interrupt sources

- Nested Interrupt control is available.
- External input: 2
- Keyscan input
- Basic Interval Timer
- Watchdog timer
- Timer : 3

· Power On Reset

· Power saving Operation Modes

- STOP Operation
- SLEEP Operation

· Low Voltage Detection Circuit

· Watch Dog Timer Auto Start (During 1second

after Power on Reset)

Device Name

ROM Size

EPROM Size

RAM Size

Package

HMS81004E

4K Bytes

448 Bytes
( included

256 bytes

stack memory )

20 SOP/PDIP

24 SOP/Skinny DIP
28 SOP/Skinny DIP

HMS81008E

8K Bytes

HMS81016E

16K Bytes

HMS81024E

24K Bytes

HMS81032E

32K Bytes

HMS81020TL

20K Bytes

HMS81032TL

32K Bytes

20 PIN

24 PIN

28 PIN

INPUT

OUTPUT

I/O

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

5. PIN FUNCTION

: Supply voltage.

: Circuit ground.

TEST: Used for shipping inspection of the IC. For normal
operation, it should be connected to V

RESET: Reset the MCU.

: Input to the inverting oscillator amplifier and input to

the internal main clock operating circuit.

OUT

: Output from the inverting oscillator amplifier.

R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be

used as outputs or inputs.

In addition, R1 serves the functions of the various follow-
ing special features .

R20~R24: R2 is an 8-bit CMOS bidirectional I/O port. R2
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs .

Port pin

Alternate function

R11
R12
R14
R15
R16
R17

INT1 (External Interrupt input 1)
INT2 (External Interrupt input 2)
EC (Event Counter input )
T2 (Timer / Counter input 2)
T1 (Timer / Counter input 1)
T0 (Timer / Counter input 0)

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PIN NAME

INPUT/

OUTPUT

Function

@RESET

@STOP

R00

I/O

- Each bit of the port can be individually configured as
an input or an output by user software
- Push-pull output
- CMOS input with pull-up resister (option)
- Can be programmable as key scan input
- Pull-up resisters are automatically disabled at output
mode

INPUT

State of
before
Stop

R01

I/O

R02

I/O

R03

I/O

R04

I/O

R05

I/O

R06

I/O

R07

I/O

R10

I/O

- Each bit of the port can be individually configured as
an input or an output by user software
- Push-pull output
- CMOS input with pull-up resister (option)
- Can be programmable as key scan input or open
drain output
- Pull-up resisters are automatically disabled at output
mode
- Direct driving of LED(N-Tr.)

INPUT

State of
before
Stop

R11/INT1

I/O

R12/INT2

I/O

R13

I/O

R14/EC

I/O

R15/T2

I/O

R16/T1

I/O

R17/T0

I/O

R20

I/O

- Each bit of the port can be individually configured as
an input or an output by user software
- Push-pull output
- CMOS input with pull-up resister (option)
- Pull-up resisters are automatically disabled at output
mode
- Direct driving of LED(N-Tr.)

INPUT

State of
before
Stop

R21

I/O

R22

I/O

R23

I/O

R24

I/O

XIN

Oscillator input

Low

XOUT

Oscillator output

High

REMOUT

High current output

`L' output

RESET

Includes pull-up resistor

`L' level

state of
before stop

TEST

Includes pull-up resistor

VDD

Positive power supply

VSS

Groud

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JUNE 2001 Ver 1.00

6. PORT STRUCTURES

R0[0:7]

R10, R13

R11/INT1, R12/INT2, R14/EC

Data Reg.

Dir. Reg.

Key Scan

Pull up

Reg.

Pull-up Tr.

Input

Open Drain

Reg.

Tr.: Transistor
Reg.: Register

LVD

Circuit

OTP : connected
MASK : option (default connected)

KS_EN

Standby Release Level Control Register

MUX

Data Reg.

Function Sele-

Key Scan

Pull up

Reg.

Pull-up Tr.

Input

Open Drain

Reg.

Data

Tr.: Transistor
Reg.: Register

LVD

Circuit

OTP : connected
MASK : option (default connected)

KS_EN

Standby Release Level Control Register

ction Reg.

D ir R eg.

MUX

Data Reg.

Function Sele-

Key Scan

Pull up

Reg.

Pull-up Tr.

Input

Open Drain

Reg.

ta B

Tr.: Transistor
Reg.: Register

LVD

Circuit

OTP : connected
MASK : option (default connected)

KS_EN

Standby Release Level Control Register

ction Reg.

D ir R eg.

MUX

Noise

Filter

to R11...INT1
to R12...INT2
to R14...EC

MUX

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JUNE 2001 Ver 1.00

R15/T2, R16/T1, R17/T0

R2[0:4]

TEST

REMOUT

XIN, XOUT

RESET

Data Reg.

Function Sele-

Key Scan

Pull up

Reg.

Pull-up Tr.

Input

Open Drain

Reg.

Data

Tr.: Transistor
Reg.: Register

LVD

Circuit

OTP : connected
MASK : option (default connected)

KS_EN

Standby Release Level Control Register

ction Reg.

D ir R eg.

MUX

to R15...T2
to R16...T1
to R17...T0

MUX

Data Reg.

Dir. Reg.

Pull up

Reg.

Pull-up Tr.

Open Drain

Reg.

Data

Tr.: Transistor
Reg.: Register

LVD

Circuit

OTP : connected
MASK : option (default connected)

MUX

Noise

Filter

Internal Signal

XIN

XOUT

Noise

Filter

from STOP circuit

Noise

Filter

from Power On Reset

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage ........................................... -0.3 to +5.0 V

Input Voltage .....................................-0.3 to V

+0.3 V

Output Voltage ...................................-0.3 to V

+0.3 V

Operating Temperature........................................ 0~70

Storage Temperature ...................................... -65~150

Power Dissipation................................................700 mA

Note: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.

7.2 Recommended Operating Conditions

7.3 DC Electrical Characteristics

=-0~70

C, V

=2.0~3.6V, GND=0V)

Parameter

Symbol

Condition

Specifications

Unit

Min.

Max.

Supply Voltage

XIN

=4MHz

2.0

3.6

Operating Frequency

XIN

=2.0~3.6V

1.0

4.0

MHz

Operating Temperature

OPR

+70

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

High level
input Voltage

IH1

R11,R12,R14,RESET

0.8 V

IH2

R0,R1(except R11,R12,R14), R2

0.7 V

Low level
input Voltage

IL1

R11,R12,R14,RESET

0.2 V

IL2

R0,R1(except R11,R12,R14), R2

0.3 V

Hign level input
Leakage Current

R0,R1,R2,RESET ,V

= VDD

Low level input
Leakage Current

R0,R1,R2,RESET (without pull-up),V

= 0

-1

High level
output Voltage

OH1

R0, I

=-0.5mA

VDD-0.4

OH2

R1[6:0], R2, I

=-1.0mA

VDD-0.4

OH3

XIN, XOUT,I

=-200

VDD-0.9

Low level
output Voltage

OL1

R0, I

=1mA

0.4

OL2

R1, R2, I

=5mA

0.8

OL3

XIN, XOUT,I

=200

0.8

Hign level output
Leakage Current

OHL

R0,R1,R2, V

= VDD

Low level output
Leakage Current

OLL

R0,R1,R2, V

= 0

-1

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JUNE 2001 Ver 1.00

7.4 REMOUT Port Ioh Characteristics Graph

(typical process & room temperature)

High Level
output current

REMOUT, R17, V

=2V

-30

-12

-5

Low Level
output cruuent

REMOUT, V

=1V

0.5

Input pull-up current

R0,R1,R2, RESET, VDD=3V

Power Supply Current

DD1

Operating current ,fxin=4Mhz, VDD=2.0V

2.4

DD2

Operating current ,fxin=4Mhz, VDD=3.6V

SLP1

Sleep mode current ,fxin=4Mhz,
VDD=2.0V

SLP2

Sleep mode current ,fxin=4Mhz,
VDD=3.6V

STP1

Stop mode current ,Oscillator Stop
VDD=2.0V

STP2

Stop mode current ,Oscillator Stop
VDD=3.6V

RAM retention
supply voltage

RET

0.7

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

Figure 7-1 Ioh vs Voh

Ioh(mA)

Voh (

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

-5

-10

-15

-20

-25

-30

Vdd 2V

Vdd 3V

Vdd 4V

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

7.5 REMOUT Port Iol Characteristics Graph

(typical process & room temperature)

7.6 AC Characteristics

=0~+70

°
°
°
°

C, V

=2.0~3.6V

=0V)

Figure 7-2 Iol vs Vol

Iol(mA)

Vol (

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

-1

Vdd 3V

Vdd 4V

Vdd 2V

Parameter

Symbol

Pins

Specifications

Unit

Min.

Typ.

Max.

External clock input cycle time

250

500

1000

System clock cycle time

SYS

500

1000

2000

External clock pulse width High

CPH

External clock pulse width Low

CPL

External clock rising time

RCP

External clock falling time

FCP

Interrupt pulse width High

INT1, INT2

SYS

Interrupt pulse width Low

INT1, INT2

SYS

RESET Input pulse width low

RSTL

RESET

SYS

Event counter input pulse width high

ECH

SYS

Event counter input pulse width low

ECL

SYS

Event counter input pulse rising time

REC

Event counter input pulse falling time

FEC

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

8. MEMORY ORGANIZATION

The HMS81004E/08E/16E/24E/32E has separate address
spaces for Program memory and Data Memory. Program
memory can only be read, not written to. It can be up to

32K bytes of Program memory. Data memory can be read
and written to up to 448 bytes including the stack area.

8.1 Registers

This device has six registers that are the Program Counter
(PC), an Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.

Figure 8-1 Configuration of Registers

Accumulator:

The Accumulator is the 8-bit general purpose register, used
for data operation such as transfer, temporary saving, and
conditional judgement, etc. The Accumulator can be used
as a 16-bit register with Y Register as shown below.

In the case of multiplication instruction, execute as a mul-
tiplier register. After multiplication operation, the lower 8-
bit of the result enters. (Y*A => YA). In the case of divi-
sion instruction, execute as the lower 8-bit of dividend. Af-
ter division operation, quotient enters.

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers:

In the addressing mode which uses these index registers,
the register contents are added to the specified address,
which becomes the actual address. These modes are ex-
tremely effective for referencing subroutine tables and
memory tables. The index registers also have increment,
decrement, comparison and data transfer functions, and
they can be used as simple accumulators.

· X Register

In the case of division instruction, execute as register.

· Y Register

In the case of 16-bit operation instruction, execute as the
upper 8-bit of YA. (16-bit accumulator). In the case of
multiplication instruction, execute as a multiplicand regis-
ter. After multiplication operation, the upper 8-bit of the
result enters. In the case of division instruction, execute as
the upper 8-bit of dividend. After division operation, re-
mains enters. Y register can be used as loop counter of
conditional branch command. (e.g.DBNE Y, rel)

Stack Pointer:

The Stack Pointer is an 8-bit register used for occurrence
interrupts, calling out subroutines and PUSH, POP, RETI,
RET instruction. Stack Pointer identifies the location in the
stack to be accessed (save or restore).

Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost. The SP is post-decremented when a subrou-
tine call or a push instruction is executed, or when an inter-
rupt is accepted. The SP is pre-incremented when a return
or a pop instruction is executed.

The stack can be located at any position within 100

1FF

of the internal data memory. The SP is not initialized

by hardware, requiring to write the initial value (the loca-
tion with which the use of the stack starts) by using the ini-
tialization routine. Normally, the initial value of "FF

" is

ACCUMULATOR

X REGISTER

Y REGISTER

STACK POINTER

PROGRAM COUNTER

PROGRAM STATUS
WORD

PCL

PCH

PSW

Two 8-bit Registers can be used as a "YA" 16-bit Register

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

used.

Figure 8-3 Stack Operation

Program Counter:

The Program Counter is a 16-bit wide which consists of
two 8-bit registers, PCH and PCL. This counter indicates
the address of the next instruction to be executed. In reset
state, the program counter has reset routine address
(PC

:0FF

, PC

:0FE

Program Status Word:

The Program Status Word (PSW) contains several bits that

reflect the current state of the CPU. The PSW is described
in Figure 8-4 . It contains the Negative flag, the Overflow
flag, the Break flag the Half Carry (for BCD operation),
the Interrupt enable flag, the Zero flag, and the Carry flag.

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.

Stack Address ( 100

~ 1FF

)

Hardware fixed

Caution:

The Stack Pointer must be initialized by software be-
cause its value is undefined after RESET.

Example: To initialize the SP

LDX

#0FFH

TXSP

; SP

At execution of
a CALL/TCALL/PCALL

PCL

PCH

01FF

SP after
execution

SP before
execution

01FD

01FE

01FD

01FC

01FF

Push
down

At acceptance
of interrupt

PCL

PCH

01FF

01FC

01FE

01FD

01FC

01FF

Push
down

PSW

At execution
of RET instruction

PCL

PCH

01FF

01FE

01FD

01FC

01FD

Pop
up

At execution
of RETI instruction

PCL

PCH

01FF

01FE

01FD

01FC

Pop
up

PSW

0100H

01FFH

Stack
depth

At execution
of PUSH instruction

01FF

01FE

01FD

01FC

01FF

Push
down

SP after
execution

SP before
execution

PUSH A (X,Y,PSW)

At execution
of POP instruction

01FF

01FE

01FD

01FC

01FE

Pop
up

POP A (X,Y,PSW)

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JUNE 2001 Ver 1.00

[Zero flag Z]

This flag is set when the result of an arithmetic operation
or data transfer is "0" and is cleared by any other result.

Figure 8-4 PSW (Program Status Word) Register

[Interrupt disable flag I]

This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to "0". This flag immedi-
ately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.

[Half carry flag H]

After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
dress.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In

the direct addressing mode, addressing area is from zero
page 00

to 0FF

when this flag is "0". If it is set to "1",

addressing area is 1 Page. It is set by SETG instruction and
cleared by CLRG.

[Overflow flag V]

This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
ceeds +127(7F

) or -128(80

). The CLRV instruction

clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.

NEGATIVE FLAG

MSB

LSB

RESET VALUE : 00

PSW

OVERFLOW FLAG

BRK FLAG

CARRY FLAG RECEIVES

ZERO FLAG

INTERRUPT ENABLE FLAG

CARRY OUT

HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS

SELECT DIRECT PAGE

when g=1, page is addressed by RPR

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8.2 Program Memory

A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 4/8/16/24/32K bytes pro-
gram memory space only physically implemented. Ac-
cessing a location above FFFF

will cause a wrap-around

to 0000

Figure 8-5 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFE

and FFFF

as shown in Figure 8-6 .

As shown in Figure 8-5 , each area is assigned a fixed lo-
cation in Program Memory. Program Memory area con-
tains the user program.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL in-
stead of 3 bytes CALL instruction. If it is frequently
called, it is more useful to save program byte length.

Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0

for TCALL15, 0FFC2

for

TCALL14, etc., as shown in Figure 8-7 .

Example: Usage of TCALL

The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to loca-
tion 0FFFA

. The interrupt service locations spaces 2-byte

interval: 0FFF8

and 0FFF9

for External Interrupt 1,

0FFFA

and 0FFFB

for External Interrupt 0, etc.

Any area from 0FF00

to 0FFFF

, if it is not going to be

used, its service location is available as general purpose
Program Memory.

Figure 8-6 Interrupt Vector Area

TCALL

AREA

INTERRUPT

VECTOR AREA

FF00

FFC0

FFE0

FFFF

PCALL

AREA

A000

8000

F000

E000

C000

04E

KROM

100

016

102

KROM

810

KRO

LDA

#5
TCALL

0FH

;

1BYTE INSTR UCTIO N

;

INSTEAD O F 2 BYTES

;

NO R M AL C ALL

;
;TABLE CALL ROUTINE
;
FUNC_A:

LDA

LRG0

RET

;
FUNC_B:

LDA

LRG1

RET

;
;TABLE CALL ADD. AREA
;

ORG

0FFC0H

;

TCALL ADDRESS AREA

FUNC_A

FUNC_B

Address

Vector Area Memory

Basic Interval Timer Interrupt Vector Area

Timer2 Interrupt Vector Area

Timer0 Interrupt Vector Area

External Interrupt 2 Vector Area

Key Scan Interrupt Vector Area

RESET Vector Area

External Interrupt 1 Vector Area

Timer1 Interrupt Vector Area

Watch Dog Timer Interrupt Vector Area

"-" means reserved area.

NOTE:

0FFDE

S/W Interrupt Vector Area

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Figure 8-7 PCALL and TCALL Memory Area

PCALL

rel

4F35

PCALL 35H

TCALL

TCALL

0FFC0

Address

Program Memory

0FF00

Address

PCALL Area Memory

0FFBF

PCALL Area

(192 Bytes)

* means that the BRK software interrupt is using
same address with TCALL0.

NOTE:

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

TCALL 8

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

0FF35H

0FF00H

0FFFFH

11111111 11010110

01001010

PC:

0FFD6H

0FF00H

0FFFFH

0FFD7H

0D125H

Reverse

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Example: The usage software example of Vector address and the initialize part.

ORG

0FFE0H

NOT_USED

BIT_INT

; BIT

WDT_INT

; Watch Dog Timer

NOT_USED

TMR2_INT

; Timer-2

TMR1_INT

; Timer-1

TMR0_INT

; Timer-0

NOT_USED

;

INT2

; Int.2

INT1

; Int.1

KEY_INT

; Key Scan

NOT_USED

;

RESET

; Reset

ORG

08000H

;HMS81032E Program start address

;********************************************
;

MAIN PROGRAM

;********************************************
;
RESET:

NOP
CLRG
DI

;Disable All Interrupts

LDX

RAM_CLR:

LDA

;RAM Clear(!0000H->!00BFH)

STA

{X}+

CMPX

#0C0H

BNE

RAM_CLR

;

LDX

#0FFH

;Stack Pointer Initialize

TXSP

LDM

R0, #0

;Normal Port 0

LDM

R0DD,#1000_0010B

;Normal Port Direction

LDM

P0PC,#1000_0010B

;Pull Up Selection Set

LDM

PMR1,#0000_0010B

;R1 port / int

:
:
LDM

CKCTLR,#0011_1101B

;WDT ON , 16mS Time delay after stop mode release

:
:

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa-
ble. Data Memory is divided into 3 groups, a user RAM,
control registers, Stack.

Figure 8-8 Data Memory Map

User Memory

The HMS81004E/08E/16E/24E/32E has 448

8 bits for

the user memory (RAM).

Control Registers

The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0

to 0FF

Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.

More detailed informations of each register are explained
in each peripheral section.

Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write instruc-
tion. Use byte manipulation instruction.

Example; To write at CKCTLR

LDM

CLCTLR,#09H ;Divide ratio

÷16

Stack Area

The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.

When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.

The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-3 on page 17.

RAM

(192 Bytes)

CONTROL

REGISTERS

0000H

00BFH

00C0H

00FFH

0100H

01FFH

PAGE0

PAGE1

RAM (STACK)
(256 Bytes)

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

8.4

List for Control Registers

Address

Function Register

Symbol

Read
Write

RESET Value

00C0h

PORT R0 DATA REG.

R/W

undefined

00C1h

PORT R0 DATA DIRECTION REG.

R0DD

00000000b

00C2h

PORT R1 DATA REG.

R/W

undefined

00C3h

PORT R1 DATA DIRECTION REG.

R1DD

00000000b

00C4h

PORT R2 DATA REG.

R/W

undefined

00C5h

PORT R2 DATA DIRECTION REG.

R2DD

00000000b

00C6h

reserved

00C7h

CLOCK CONTROL REG.

CKCTLR

--110111b

BASIC INTERVAL REG.

BTR

undefined

00C8h

WATCH DOG TIMER REG.

WDTR

-0001111b

00C9h

PORT R1 MODE REG.

PMR1

00000000b

00CAh

INT. MODE REG.

IMOD

R/W

-0000000b

00CBh

EXT. INT. EDGE SELECTION

IEDS

00000000b

00CCh

INT. ENABLE REG. LOW

IENL

R/W

-00-----b

00CDh

INT. REQUEST FLAG REG. LOW

IRQL

R/W

-00-----b

00CEh

INT. ENABLE REG. HIGH

IENH

R/W

000-000-b

00CFh

INT. REQUEST FLAG REG. HIGH

IRQH

R/W

000-000-b

00D0h

TIMER0 (16bit) MODE REG.

TM0

R/W

00000000b

00D1h

TIMER1 (8bit) MODE REG.

TM1

R/W

00000000b

00D2h

TIMER2 (8bit) MODE REG.

TM2

R/W

00000000b

00D3h

TIMER0 HIGH-MSB DATA REG.

T0HMD

undefined

00D4h

TIMER0 HIGH-LSB DATA REG.

T0HLD

undefined

00D5h

TIMER0 LOW-MSB DATA REG.

T0LMD

undefined

TIMER0 HIGH-MSB COUNT REG.

undefined

00D6h

TIMER0 LOW-LSB DATA REG.

T0LLD

undefined

TIMER0 LOW-LSB COUNT REG.

undefined

00D7h

TIMER1 HIGH DATA REG.

T1HD

undefined

00D8h

TIMER1 LOW DATA REG.

T1LD

undefined

TIMER1 LOW COUNT REG.

undefined

00D9h

TIMER2 DATA REG.

T2DR

undefined

TIMER2 COUNT REG.

undefined

00DAh

TIMER0 / TIMER1 MODE REG.

TM01

R/W

00000000b

00DBh

Reserved

00DCh

STANDBY MODE RELEASE REG0

SMPR0

R/W

00000000b

00DDh

STANDBY MODE RELEASE REG0

SMPR1

R/W

00000000b

00DEh

PORT R1 OPEN DRAIN ASSIGN REG.

R1ODC

R/W

00000000b

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JUNE 2001 Ver 1.00

00DFh

PORT R2 OPEN DRAIN ASSIGN REG.

R2ODC

R/W

00000000b

00E0h

Reserved

00E1h

Reserved

00E2h

Reserved

00E3h

Reserved

00E4h

PORT R0 OPEN DRAIN ASSIGN REG.

R0ODC

R/W

00000000b

00E5h

Reserved

00E6h

Reserved

00E7h

Reserved

00E8h

Reserved

00E9h

Reserved

00EAh

Reserved

00EBh

Reserved

00ECh

Reserved

00EDh

Reserved

00EEh

Reserved

00EFh

Reserved

00F0h

SLEEP MODE REG.

SLPM

- - - - - - - 0b

00F1h

Reserved

00F2

Reserved

00F3h

Reserved

00F4h

Reserved

00F5h

Reserved

00F6h

STANDBY RELEASE LEVEL CONT. REG. 0

SRLC0

00000000b

00F7h

STANDBY RELEASE LEVEL CONT. REG. 1

SRLC1

00000000b

00F8h

PORT R0 PULL-UP REG. CONT. REG.

R0PC

00000000b

00F9h

PORT R1 PULL-UP REG. CONT. REG.

R1PC

00000000b

00FAh

PORT R2 PULL-UP REG. CONT. REG.

R2PC

00000000b

00FBh

Reserved

00FCh

Reserved

00FDh

Reserved

00FEh

Reserved

00FFh

Reserved

Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation

Registers are controlled by both bit and byte manipulation instruction.

R/W

instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.

- : this bit location is reserved.

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

8.5 Addressing Mode

The HMS81004E/08E/16E/24E/32E uses six addressing
modes;

· Register addressing

· Immediate addressing

· Direct page addressing

· Absolute addressing

· Indexed addressing

· Register-indirect addressing

(1) Register Addressing

(2) Immediate Addressing

#imm

In this mode, second byte (operand) is accessed as a data
immediately.

Example:

0435

ADC

#35H

When G-flag is 1, then RAM address is difined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.

Example: G=1, RPR=0CH

E45535

LDM

35H,#55H

(3) Direct Page Addressing

In this mode, a address is specified within direct page.

Example; G=0

C535

LDA

35H

RAM[35H]

(4) Absolute Addressing

!abs

Absolute addressing sets corresponding memory data to
Data , i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY

Example;

A+35H+C

MEMORY

0F100

data

55H

data

0C35

0F102

0F101

data

0E551

data

0E550

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JUNE 2001 Ver 1.00

The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

regard-

less of G-flag and RPR.

983501

INC

!0135H

ROM[135H]

(5) Indexed Addressing

X indexed direct page (no offset)

{X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15

, G=1, RPR=01

LDA

{X}

;ACC

RAM[X].

X indexed direct page, auto increment

{X}+

In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.

LDA, STA

Example; G=0, X=35

LDA

{X}+

X indexed direct page (8 bit offset)

dp+X

This address value is the second byte (Operand) of com-
mand plus the data of

-register. And it assigns the mem-

ory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5

C645

LDA

45H+X

0F100

data

135

0F102

0F101

data+1

data

address: 0135

data

115

0E550

data

36H

data

0E551

data

0E550

45H+0F5H=13AH

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Y indexed direct page (8 bit offset)

dp+Y

This address value is the second byte (Operand) of com-
mand plus the data of Y-register, which assigns Memory in
Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute

!abs+Y

Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify mem-
ory in whole area.

Example; Y=55

D500FA

LDA

!0FA00H+Y

(6) Indirect Addressing

Direct page indirect

[dp]

Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.

JMP, CALL

Example; G=0

3F35

JMP

[35H]

X indexed indirect

[dp+X]

Processes memory data as Data, assigned by 16-bit pair
m e m o r y w h i c h i s d e t e r m i n e d b y p a i r d a t a
[dp+X+1][dp+X] Operand plus

X-register data in Direct

page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10

1625

ADC

[25H+X]

0F100

data

0FA55

0FA00H+55H=0FA55H

0F102

0F101

jump to address 0E30A

0FA00

0E30A

0E005

0FA00

0E005

data

A + data + C

25 + X(10) = 35

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Y indexed indirect

[dp]+Y

Processes momory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Di-
rect page

plus Y-register data.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, Y=10

1725

ADC

[25H]+Y

Absolute indirect

[!abs]

The program jumps to address specified by 16-bit absolute
address.

JMP

Example; G=0

1F25E0

JMP

[!0C025H]

0E005

+ Y(10) = 0E015

0FA00

0E015

data

A + data + C

0E025

jump to

0FA00

0E026

0E725

PROGRAM MEMORY

address 0E30A

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JUNE 2001 Ver 1.00

9. I/O PORTS

The HMS81004E/08E/16E/24E/32E has 24 I/O ports
which are PORT0(8 I/O), PORT1 (8 I/O), PORT2 (8 I/O).
Pull-up resistor of each port can be selectable by program.
Each port contains data direction register which controls I/
O and data register which stores port data.

9.1 R0 Ports

R0 is an 8-bit CMOS bidirectional I/O port (address
0C0

). Each I/O pin can independently used as an input or

an output through the R0DD register (address 0C1

R0 has internal pull-ups that is independently connected or
disconnected by R0PC. The control registers for R0 are
shown below.

(1) R0 I/O Data Direction Register (R0DD)

R0 I/O Data Direction Register (R0DD) is 8-bit register,
and can assign input state or output state to each bit. If
R0DD is "1", port R0 is in the output state, and if "0", it is
in the input state. R0DD is write-only register. Since
R0DD is initialized as "00h" in reset state, the whole port
R0 becomes input state.

(2) R0 Data Register (R0)

R0 data register (R0) is 8-bit register to store data of port
R0. When set as the output state by R0DD, and data is writ-
ten in R0, data is outputted into R0 pin. When set as the in-
put state, input state of pin is read. The initial value of R0
is unknown in reset state.

(3) R0 Open drain Assign Register (R0ODC)

R0 Open Drain Assign Register (R0ODC) is 8bit register,
and can assign R0 port as open drain output port each bit,
if corresponding port is selected as output. If R0ODC is
selected as "1", port R0 is open drain output, and if select-
ed as, "0" it is push-pull output. R0ODC is write-only reg-
ister and initialized as "00h" in reset state.

(4) R0 Pull-up Control Register (R0PC)

R0 Pull-up Control Register (R0PC) is 8-bit register and
can control pull-up on or off each bit, if corresponding port
is selected as input. If R0PC is selected as "1", pull-up ia
disabled and if selected as "0", it is enabled. R0PC is write-
only register and initialized as "00h" in reset state. The
pull-up is automatically disabled, if corresponding port is
selected as output.

9.2 R1 Ports

R1 is an 8-bit CMOS bidirectional I/O port (address
0C2

). Each I/O pin can independently used as an input or

an output through the R1DD register (address 0C3

R1 has internal pull-ups that is independently connected or
disconnected by register R1PC. The control registers for
R1 are shown below.

R0 Data Register (R/W)

ADDRESS : 0C0

RESET VALUE : Undefined

R07 R06 R05 R04 R03 R02 R01 R00

Port Direction

R0 Direction Register (W)

R0DD

ADDRESS : 0C1

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R0 Pull-up Control Register (W)

R0PC

ADDRESS :0F8

RESET VALUE : 00

1: Without pull-up
0: With pull-up

Open drain select

R0 Open drain Assign Register (W)

R0ODC

ADDRESS :0E4

RESET VALUE : 00

0: Push-pull
1: Open drain

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JUNE 2001 Ver 1.00

(1) R1 I/O Data Direction Register (R1DD)

R1 I/O Data Direction Register (R1DD) is 8-bit register,
and can assign input state or output state to each bit. If
R1DD is "1", port R1 is in the output state, and if "0", it is
in the input state. R1DD is write-only register. Since
R1DD is initialized as "00h" in reset state, the whole port
R1 becomes input state.

(2) R1 Data Register (R1)

R1 data register (R1) is 8-bit register to store data of port
R1. When set as the output state by R1DD, and data is
written in R1, data is outputted into R1 pin. When set as
the input state, input state of pin is read. The initial value
of R1 is unknown in reset state.

(3) R1 Open drain Assign Register (R1ODC)

R1 Open Drain Assign Register (R1ODC) is 8bit register,

and can assign R1 port as open drain output port each bit,
if corresponding port is selected as output. If R1ODC is
selected as "1", port R1 is open drain output, and if select-
ed as "0", it is push-pull output. R1ODC is write-only reg-
ister and initialized as "00h" in reset state.

(4) R1 Port Mode Register (PMR1)

R1 Port Mode Register (PMR1) is 8-bit register, and can
assign the selection mode for each bit. When set as "0",
corresponding bit of PMR1 acts as port R1 selection mode,
and when set as "1", it becomes function selection mode.

PMR1 is write-only register and initialized as "00h" in re-
set state. Therefore, becomes Port selection mode. Port
R1 can be I/O port by manipulating each R1DD bit, if cor-
responding PMR1 bit is selected as "0".

(5) R1 Pull-up Control Register (R1PC)

R1 Pull-up Control Register (R1PC) is 8-bit register and
can control pull-up on or off each bit, if corresponding port
is selected as input. If R1PC is selected as "1", pull-up ia
disabled and if selected as "0", it is enabled. R1PC is write-
only register and initialized as "00h" in reset state. The

R1 Data Register (R/W)

ADDRESS : 0C2

RESET VALUE : Undefined

R17 R16 R15 R14 R13 R12 R11 R10

Port Direction

R1 Direction Register (W)

R1DD

ADDRESS : 0C3

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R1 Pull-up Control Register (W)

R1PC

ADDRESS : 0F9

RESET VALUE : 00

1: Without pull-up
0: With pull-up

Open drain select

R1 Open drain Assign Register (W)

P1ODC

ADDRESS : 0DE

RESET VALUE : 00

0: Push-pull
1: Open drain

Mode select

R1 Port Mode Register (W)

PMR1

ADDRESS : 0C9

RESET VALUE : 00

0: Port R1 selection
1: Function selection

Pin Name

PMR1

Selection

Mode

Remarks

T0S

R17 (I/O)

T0 (O)

Timer0

T1S

R16 (I/O)

T1 (O)

Timer1

T2S

R15 (I/O)

T2 (O)

Timer2

ECS

R14 (I/O)

EC (I)

Timer0 Event

INT2S

R12 (I/O)

INT2 (I)

Timer0 Input Cap-

ture

INT1S

R11 (I/O)

INT1 (I)

Table 9-1 Selection mode of PMR1

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

pull-up is automatically disabled, if corresponding port is
selected as output.

9.3 R2 Port

R2 is an 8-bit CMOS bidirectional I/O port (address
0C4

). Each I/O pin can independently used as an input or

an output through the R2DD register (address 0C5

R2 has internal pujll-ups that is independently connected
or disconnected by R2PC (address 0FA

). The control reg-

isters for R2 are shown as below.

(1) R2 I/O Data Direction Register (R2DD)

R2 I/O Data Direction Register (R2DD) is 8-bit register,
and can assign input state or output state to each bit. If
R2DD is "1", port R2 is in the output state, and if "0", it is
in the input state. R2DD is write-only register. Since
R2DD is initialized as "00h" in reset state, the whole port
R2 becomes input state.

(2) R2 Data Register (R2)

R2 data register (R2) is 8-bit register to store data of port
R2. When set as the output state by R2DD, and data is writ-
ten in R2, data is outputted into R2 pin. When set as the in-
put state, input state of pin is read. The initial value of R2
is unknown in reset state.

(3) R2 Open drain Assign Register (R2ODC)

R2 Open Drain Assign Register (R2ODC) is 8bit register,
and can assign R2 port as open drain output port each bit,
if corresponding port is selected as output. If R2ODC is
selected as "1", port R2 is open drain output, and if select-
ed as "0", it is push-pull output. R2ODC is write-only reg-
ister and initialized as "00h" in reset state.

(4) R2 Pull-up Control Register (R2PC)

R2 Pull-up Control Register (R2PC) is 8-bit register and
can control pull-up on or off each bit, if corresponding port
is selected as input. If R2PC is selected as "1", pull-up ia
disabled and if selected as "0", it is enabled. R2PC is write-
only register and initialized as "00h" in reset state. The
pull-up is automatically disabled, if corresponding port is
selected as output.

R2 Data Register (R/W)

ADDRESS : 0C4

RESET VALUE : Undefined

R24 R23 R22 R21 R20

Port Direction

R2 Direction Register (W)

R2DD

ADDRESS : 0C5

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R2 Pull-up Control Register (W)

R2PC

ADDRESS :0FA

RESET VALUE : 00

1: Without pull-up
0: With pull-up

Open drain select

R2 Open drain Assign Register (W)

R2ODC

ADDRESS :0DF

RESET VALUE : 00

0: Push-pull
1: Open drain

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

10. CLOCK GENERATOR

Clock generating circuit consists of Clock Pulse Generator
(C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch
Dog Timer. The clock applied to the Xin pin divided by
two is used as the internal system clock.

Prescaler consist of 12-bit binary counter. The clock sup-
plied from oscillation circuit is input to prescaler(fex)

The divided output from each bit of prescaler is provided
to periphera hardwarel

Clock to peripheral hardware can be stopped by bit4 (EN-
PCK) of CKCTLR Register. ENPCK is set to "1" in reset

state.

Clock Control Register (W)

CKCTLR

ADDRESS : 0C7

INITIAL VALUE : --110111b

ENPCK 0: Stopped

1: Provided

Figure 10-1 Block diagram of Clock Generator

Internal system clock (CPU clock)

PRESCALER

Peripheral clock

128

256

512

1024

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS10

CLOCK PULSE

(MHz)

PS0

PS3

PS2

PS4

PS1

PS10

PS9

PS5

PS6

PS7

Frequency

period

500K

250K

125K

62.5K

250n

500n

16u

32u

64u

256u

128u

3.906K

7.183K

15.63K

31.25K

PS8

GENERATOR

OSC

CIRCUIT

PS11

PS12

1.953K

512u

0.976K

1024u

PS11 PS12

2048

4096

fex

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

10.1 Oscillation Circuit

Oscillation circuit is designed to be used either with a ce-
ramic resonator or crystal oscillator. Figure 10-2 shows
circuit diagrams using a crystal (or ceramic) oscillator. As
shown in the diagram, oscillation circuits can be construct-
ed by connecting a oscillator between Xout and Xin. Colck
from oscillation circuit makesCPU clock via clock pulse
generator, and then enters prescaler to make peripheral
hardware clock. Alternately, the oscillator may be driven
from an esternal source as Figure 10-3 . In the STOP
mode,oscillation stop, Xout state goes to "HIGH" , Xin
state goes to "LOW" , and built-in feed back resistor is dis-
abled.

Oscillation circuit is designed to be used either with a ce-
ramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components. In addition, see Figure 10-
4 for the layout of the crystal.

Note: Minimize the wiring length. Do not allow the wiring to
intersect with other signal conductors. Do not allow the wir-
ing to come near changing high current. Set the potential of
the grounding position of the oscillator capacitor to that of
V

. Do not ground it to any ground pattern where high cur-

rent is present. Do not fetch signals from the oscillator.

Figure 10-4 Recommend Layout of Oscillator PCB

circuit

Figure 10-2 External Crystal(Ceramic) oscillator circuit

Figure 10-3 External clock input circuit

Xout

Xin

Vss

Cout

Cin

Xout

Xin

Vss

OPEN

External
Clock
Source

OUT

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Frequency

Resonator Maker

Part Name

Load Capacitor

Operating Voltage

2.00MHz

ZTT2.00

Cin=Cout=open

2.0~3.6

ZTA2.00

Cin=Cout=30pF

2.0~3.6

MURATA

CSTLS2M00G56-B0

Cin=Cout=open

2.0~3.6

MURATA

CSTCC2.00MG0H6

Cin=Cout=open

2.0~3.6

MURATA

CSTCC2M00G56-R0

Cin=Cout=open

2.0~3.6

4.00MHz

ZTT4.00

Cin=Cout=open

2.0~3.6

ZTA4.00

Cin=Cout=30pF

2.0~3.6

MURATA

CSTS0400MG06

Cin=Cout=open

2.0~3.6

MURATA

CSTLS4M00G56-B0

Cin=Cout=open

2.0~3.6

MURATA

CSTCR4M00G55-R0

Cin=Cout=open

2.0~3.6

TDK

FCR4.0MC5

Cin=Cout=open

2.0~3.6

TDK

FCR4.0MSC5

Cin=Cout=open

2.0~3.6

CORETECK

CRT4.00MS

Cin=Cout=open

2.0~3.6

CORETECK

CRM4.00MS

Cin=Cout=30pF

2.0~3.6

Table 10-1 Recommendalbe resonator

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

11. BASIC INTERVAL TIMER

The HMS81004E/08E/16E/24E/32E has one 8-bit Basic
Interval Timer that is free-run and can not stop. Block dia-
gram is shown in Figure 11-1 .

The Basic Interval Timer generates the time base for
Standby release time, watchdog timer counting, and etc. It
also provides a Basic interval timer interrupt (IFBIT). As
the count overflow from FF

to 00

, this overflow causes

the interrupt to be generated.

-8bit binary up-counter

-Use the bit output of prescaler as input to secure the oscil-
lation stabilization time after power-on

-Secures the oscillation stabilization time in standby mode
(stop mode) release

-Contents of B.I.T can be read

-Provides the clock for watch dog timer

The Basic Interval Timer is controlled by the clock control
register (CKCTLR) shown in Figure 11-2 . If bit3(BTCL)
of CKCTLR is set to "1", B.I.T is cleared, and then, after
one machine cycle, BTCL becomes "0", and B.I.T starts
counting. BTCL is set to ``0`` in reset state.

The input clock of B.I.T can be selected from the prescaler
within a range of 2us to 256us by clock input selection bits
(BTS2~BTS0). (at fex = 4MHz). In reset state, or power
on reset, BTS2="1", BTS1= "1", BTS0= "1" to secure the
longest oscillation stabilization time. B.I.T can generate
the wide range of basic interval time interrupt request (IF-
BIT) by selecting prescaler output.

By reading of the Basic Interval Timer Register (BITR),
we can read counter value of B.I.T. Because B.I.T can be
cleared or read, the spending time up to maximum 65.5ms
can be available. B.I.T is read-only register. If B.I.T reg-
ister is written, then CKCTLR register with same address
is written.

Figure 11-1 Block diagram of Basic Interval Timer

MUX

Basic Interval Timer Interrupt

Select Input clock 3

Basic Interval Timer

source
clock

8-bit up-counter

BTS[2:0]

BTCL

1024

512

256

128

To Watchdog timer (WDTR)

CKCTLR

clear

overflow

Internal bus line

clock control register

[0C7

]

IFBIT

Read

r
esca

ler

BITR

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Figure 11-2 CKCTLR AND BITR

BTS[2:0]

CPU Source clock

B.I.T. Input

clock@4Mhz(us)

Standby release

time(ms)

000
001
010
011
100
101
110
111

128

256

512

1024

2
4
8

16
32
64

128
256

0.512
1.024
2.048
4.096
8.192

16.384
32.768
65.536

BTCL

BTS1

Basic Interval Timer source clock select
000: f

XIN

001: f

XIN

010: f

XIN

011: f

XIN

100: f

XIN

128

101: f

XIN

256

110: f

XIN

512

111: f

XIN

1024

Clear bit
0: Normal operation, free-run
1: Clear 8-bit counter (BITR) to "0" and count up again.

INITAIL VALUE: --110111

ADDRESS: 0C7

CKCTLR

INITIAL VALUE: Undefined

ADDRESS: 0C7

BITR

Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.

Caution:

8-BIT FREE-RUN BINARY COUNTER

BTS0

BTS2

BTCL

ENPCK

This bit becomes to "0" automatically after one machine cycle.

Periphral clock
0:stopped
1:provided

WDTON

Watch Dog Timer function control
0:6bit timer
1:Watch Dog Timer

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

12. WATCH DOG TIMER

Watch Dog Timer (WDT) consists of 6-bit binary counter,
6-bit comparator, and Watch Dog Timer Register
(WDTR).Watch Dog Timer can be used 6-bit general Tim-
er or specific Watch dog timer by setting bit5 (WDTON)
of Clock Control Register (CKCTLR).By assigning
bit6(WDTCL) of WDTR, 6-bit counter can be cleared.

WDT Interrupt (IFWDT) interval is determined by the in-
terrupt IFBIT interval of Basic Interval Timer and the val-
ue of WDT Register.

-Interval of IFWDT = (IFBIT interval) * (WDTR value)

As IFBIT (Basic Interval Timer Interrupt Request) is used
for input clock of WDT, Input clock cycle is possible from
512 us to 65,536 us by BTS. (at fex = 4MHz)

*At Hardware reset time,WDT starts automatically.
Therefore the user must select the CKCTLR and WDTR
before WDT overflow.

-Reset WDTR value = 0F

,=15

-Interval of WDT = 65,536 * 15 = 983040 us

(about 1second )

N o t e : W h e n W D T R R e g i s t e r v a l u e i s 6 3 ( 3 F h )
(Caution) : Do not use "0" for WDTR Register value.

Device come into the reset state by WDT

Figure 12-1 Block diagram of Watch Dog Timer

IFWDT

WDT
INTERRUPT

WDTR (6-bit)

WDT (6-bit)

Comparator

WDT

BTCL

INITIAL VALUE: -0001111

ADDRESS: 0C8

WDTR

WDTCL

[0C8

]

WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0

Watch Dog Timer Operation
0:Free-run
1:Automatically cleared, after one machine cycle

IFBIT

WDTON

To Reset circuit

Clear 6

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

13. Timer0, Timer1, Timer2

(1) Timer Operation Mode

Timer consists of 16bit binary counter Timer0 (T0), 8bit
binary Timer1 (T1), Timer2 (T2), Timer Data Register,
Timer Mode Register (TM01, TM0, TM1, TM2) and con-
trol circuit. Timer Data Register Consists of Timer0 High-
MSB Data Register (T0HMD), Timer0 High-LSB Data
Register (T0HLD), Timer0 Low-MSB Data Register
(T0LMD), Timer0 Low-LSB Data Register (T0LLD),
Timer1 High Data Register (T1HD), Timer1 Low Data

Register (T1LD), Timer2 Data Register (T2DR). Any of
the PS0 ~ PS5, PS11 and external event input EC can be
selected as clock source for T0. Any of the PS0 ~ PS3, PS7
~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12
can be selected as clock source for T2.

* Relevant Port Mode Register (PMR1 : 00C9h) value
should be assigned for event counter.

Timer0

- 16-bit Interval Timer
- 16-bit Event Counter
- 16-bit Input Capture
- 16-bit rectangular-wave output

- Single/Modulo-N Mode
- Timer Output Initial Value Setting
- Timer0~Timer1 combination Logic Output
- One Interrupt Generating Every 2nd
Counter Overflow

Timer1

- 8-bit Interval Timer
- 8-bit rectangular-wave output

Timer2

- 8-bit Interval Timer
- 8-bit rectangular-wave output
- Modulo-N Mode

Table 13-1 Timer Operation

16bit Timer (T0)

8bit Timer (T1)

8bit Timer (T2)

Resolution

MAX. Count

Resolution

MAX. Count

Resolution

MAX. Count

PS0 (0.25us)

16,384us

PS0 (0.25us)

64us

PS5 (8us)

2,048us

PS1 (0.5us)

32,768us

PS1 (0.5us)

128us

PS6 (16us)

4,096us

PS2 (1us)

65,536us

PS2 (1us)

256us

PS7 (32us)

8,192us

PS3 (2us)

131,072us

PS3 (2us)

512us

PS8 (64us)

16,384us

PS4 (4us)

262,144us

PS7 (32us)

8,192us

PS9 (128us)

32,768us

PS5 (8us)

524,288us

PS8 (64us)

16,384us

PS10 (256us)

65,536us

PS11 (512us)

33,554,432us

PS9 (128us)

32,768us

PS11 (512us)

131,072us

PS10 (256us)

65,536us

PS12 (1024us)

262,144us

Table 13-2 Function of Timer & Counter

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Figure 13-1 Block Diagram of Timer/Counter

T0HMD T0LMD

T0LMD

T0LLD

T1HD

T1LD

T2DR

Timer0 (16bit)

Polarity

Timer2(8bit)

Timer1(8bit)

Selection

Edge

Selection

Tout

Logic

BTC L

T O U T1 TO U T0

T0O U TP

TO U TS TO U TB

T0IN IT T1IN IT

TM01

from
EC/R14

from
INT2/R12
(Capture Signal)

T0OUT

(R17)

TOUT

(REMOUT)

T1OUT

(R16)

T2OUT

(R15)

BT C L

INITIAL VALUE: 00

ADDRESS: 0DA

TM01

T O U T 1 T O U T 0

R/W

T0O U TP

Timer 01 mode register

TOUT LOGIC

0: Timer1 output low
1: Timer1 output high

Timer1 output initial value

0: T0OUT Polarity Equal to TOUT Logic input signal
1: T0OUT Polarity Reverse to TOUT Logic input signal

T0OUT Polarity Selection

(TOUT Logic or TOUTB)
0: Bit(TOUTB) Output Through REMOUT

REMOUT Port Output Selection

0: REMOUT Output Low
1: REMOUT Output High

REMOUT Port Bit Control

R/W

TO U TS T O U T B

00: AND of T0 OUTPUT and T1 OUTPUT
01: NAND of T0 OUTPUT and T1 OUTPUT
10: OR of T0 OUTPUT and T1 OUTPUT
11: NOR of T0 OUTPUT and T1 OUTPUT

T 0IN IT T 1IN IT

1: TOUT Logic Output Through REMOUT

0: Timer0 output low
1: Timer0 output high

Timer0 output initial value

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Figure 13-2 Block Diagram of Timer0

BTC L

T 0C N

T 0IFS

INITIAL VALUE: 00

ADDRESS: 0D0

TM0

T0SL2

T 0SL1 T0SL0

R/W

T0M O D

Timer 0 mode register

Timer0 input clock select (fex=4Mhz)

0: Modulo-N
1: Single Mode

0: Interrupt Every Count Overflow
1: Interrupt Every 2nd Count Overflow

Timer0 Single/Moudol-N select

Timer0 Interrupt select

0: Count Pause
1: Count Continuation

Timer0 Counter Continuation/Pause Control

0: Timer/Counter
1: Input capture (PS1:not supporting

Timer0 Interrupt select

0: Timer0 Stop
1: Tiemr0 Start after clear

Timer0 Start/Stop control

R/W

C AP0

T0ST

input cature)

000: PS0 250ns
001: PS1 500ns
010: PS2 1us
011: PS3 2us
100: PS4 4us
101: PS5 8us
110: PS11 512us
111: EC

T 0 S L [2 :0 ]

M U X

0 0 0

0 0 1

0 1 0

P S 4

P S 5

P S 11

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

E d g e D e te cto r

EC PIN

IFINT2

INT2
INTERRUPT

capture

IEDS[5:4]

Comparator

INT2/R12 PIN

clear

l
e

T0HC

T0LC

T0 COUNTER (16-bit)

[0D5

][0D6

]

16 BITS

MSB

LSB

P S 3

P S 2

P S 1
P S 0

T0MOD T0CN

T0ST

delay

clear

CAP0

MUX(16-bit)

T0HMD

T0HLD

T0LMD

T0LLD

[0D3

][0D4

]

[0D5

][0D6

]

CAP0

OUTPUT

GEN.

Interrupt

GEN.

T0INIT

T0OUT

T0IFS

IFT0

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Figure 13-3 Block Diagram of Timer1

T 1S L [2 :0 ]

M U X

0 00

0 01

0 10

P S 7

P S 8

P S 9

0 11

1 00

1 01

1 10

1 11

Comparator

clear

r
e

scal

T1 COUNTER (8-bit)

P S 3

P S 2

P S 1
P S 0

T1MOD T1CN

T1ST

[0D8

]

OUTPUT

GEN.

Interrupt

GEN.

T1INIT

T1OUT

T1IFS

IFT1

P S 1 0

T1 COUNT REG.

MUX(8-bit)

T1HD(8-bit)

T1LD(8-bit)

[0D7

]

[0D8

]

BT C L

T1C N

INITIAL VALUE: 00

ADDRESS: 0D1

TM1

T1SL2

T 1S L1 T 1SL0

R/W

T1M O D

Timer 1 mode register

Timer1 input clock select (fex=4Mhz)

0: Modulo-N
1: Single Mode

0: Interrupt Every Count Overflow
1: Interrupt Every 2nd Count Overflow

Timer1 Single/Moudol-N select

Timer1 Interrupt select

0: Count Pause
1: Count Continuation

Timer1 Counter Continuation/Pause Control

0: Timer1 Stop
1: Tiemr1 Start after clear

Timer1 Start/Stop control

R/W

T1S T

000: PS0 250ns
001: PS1 500ns
010: PS2 1us
011: PS3 2us
100: PS7 32us
101: PS8 64us
110: PS9 128us
111: PS10 256us

T 1IFS

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Figure 13-4 Block Diagram of Timer2

T 2S L [2 :0 ]

M U X

0 00

0 01

0 10

P S 9

P S 1 0

P S 1 1

0 11

1 00

1 01

1 10

1 11

Comparator

clear

r
e

scal

T2 COUNTER (8-bit)

P S 8

P S 7

P S 6
P S 5

T2CN

T2ST

[0D9

]

OUTPUT

GEN.

Interrupt

GEN.

T2OUT

IFT2

P S 1 2

T2 COUNT REG.

[0D9

]

T2DR

BTC L

T2C N

INITIAL VALUE: 00

ADDRESS: 0D2

TM2

T2SL2

T 2S L1 T2SL0

R/W

Timer 2 mode register

Timer2 input clock select (fex=4Mhz)

0: Count Pause
1: Count Continuation

Timer2 Counter Continuation/Pause Control

0: Timer2 Stop
1: Tiemr2 Start after clear

Timer2 Start/Stop control

T2ST

000: PS5 8us
001: PS6 16us
010: PS7 32us
011: PS8 64us
100: PS9 128us
101: PS10 256us
110: PS11 512us
111: PS12 1,024us

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

2) Timer0, Timer1

TIMER0 and TIMER1 have an up-counter. When value of
the up-counter reaches the content of Timer Data Register

(TDR), the up-counter is cleared to "00h", and interrupt
(IFT0, IFT1) is occured at the next clock.

For Timer0, the internal clock (PS) and the external clock
(EC) can be selected as counter clock. But Timer1 and
Timer2 use only internal clock. As internal clock. Timer0
can be used as internal-timer which period is determined
by Timer Data Register (TDR). Chosen as external
clock, Timer0 executes as event-counter. The counter ex-
ecution of Timer0 and Timer1 is controlled by T0CN,
T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0
and TM1. T0CN, T1CN are used to stop and start Timer0
and Timer1 without clearing the counter. T0ST, T1ST is
used to clear the counter. For clearing and starting the
counter, T0ST or T1ST should be temporarily set to "0"
and then set to "1". T0CN, T1CN, T0ST and T1ST should
be set "1", when Timer counting-up. Controlling of
CAP0 enables Timer0 as input capture. By programming
of CAP0 to "1", the period of signal from INT2 can be
measured and then, event counter value for INT2 can be
read. During counting-up, value of counter can be read-
Timer execution is stopped by the reset signal(RE-

SET="L")

Note: In the process of reading 16-bit Timer Data, first
read the upper 8-bit data. Then read the lower 8-bit data,
and read the upper 8-bit data again. If the earlier read up-
per 8-bit data are matched with the later read upper 8-bit
data, read 16-bit data are correct. If not, caution should be
taken in the selection of upper 8-bit data.

(Example)

1) Upper 8-bit Read 0A 0A

2) Lower 8-bit Read FF 01

3) Upper 8-bit Read 0B 0B

=====================

0AFF 0B01

Figure 13-5 Operation of Timer0

Timer 0 (IFT0)
Interrupt

T0 Data

TIME

Occur interrupt

Interrupt period

-c

MATCH

(TDR = T0)

T0 Value

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

3) Single/Modulo-N Mode

Timer0 (Timer1) can select initial (T0INIT, T1INIT of
TM01) output level of Timer Output port. If initial level is
"L", Low-Data Register value of Timer Data Register is
transferred to comparator and T0OUT (T1OUT) is to be
"Low", if initial level is High? High -Data Register is
transferred and to be "High". Single Mode can be set by
Mode Select bit (T0MOD, T1MOD) of Timer Mode Reg-
ister (TM0, TM1) to "1" When used as Single Mode, Tim-
er counts up and compares with value of Data Register. If
the result is same, Time Out interrupt occurs and level
of Timer Output port toggle, then counter stops as reset
state. When used as Modulo-N Mode, T0MOD (T1MOD)

should be set "0". Counter counts up until the value of
Data Register and occurs Time-out interrupt. The level of
Timer Output port toggle and repeats process of

counting the value which is selected in Data Register.
During Modulo-N Mode, If interrupt select bit (T0IFS,
T1IFS) of Mode Register is "0", Interrupt occurs on every
Time-out. If it is "1", Interrupt occurs every second time-
out.

Note: Timer Output is toggled whenever time out happen

(4) Timer 2

Timer2 operates as a up-counter. The content of T2DR are
compared with the contents of up-counter. If a match is
found. Timer2 interrupt (IFT2) is generated and the up-
counter is cleared to "00h". Therefore, Timer2 executes
as a interval timer. Interrupt period is determined by the
count source clock for the Timer2 and content of T2DR.

When T2ST is set to "1", count value of Timer 2 is cleared
and starts counting-up. For clearing and starting the
Timer2. T2ST have to set to "1" after set to "0". In order to
write a value directly into the T2DR, T2ST should be set
to "0". Count value of Timer2 can be read at any time.

Figure 13-8 Operation Diagram for Single/Modulo-N Mode

[ Single Mode ]

[ Module-N Mode ]

8bit/16bit

Timer Enable initial

8bit/16bit
counting

value toggle

counting

Timer Enable initial

value toggle

Timer-output toggle

Int occurs (IFS=1) Each 2nd time out

Int occurs (IFS=0) when Time out

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

14. INTERRUPTS

The HMS81004E/08E/16E/24E/32E interrupt circuits
consist of Interrupt Mode Register (MOD), Interrupt en-
able register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Priority circuit and Master enable flag ("I"
flag of PSW). 8 interrupt sources are provided. The config-
uration of interrupt circuit is shown in Figure 14-1 .

The HMS81004E/08E/16E/24E/32E contains 8 interrupt
sources; 3 externals and 5 internals. Nested interrupt ser-
vices with priority control is also possible. Software inter-
rupt is non-maskable interrupt, the others are all maskable
interrupts.

- 8 interrupt source (2Ext, 3Timer, BIT, WDT and
Key Scan)

- 8 interrupt vector

- Nested interrupt control is possible

- Programmable interrupt mode
(Hardware and software interrupt accept mode)

- Read and write of interrupt request flag are possible.

- In interrupt accept, request flag is automatically cleared.

Figure 14-1 Block Diagram of Interrupt

INT1

INT2

Watch Dog Timer

WDTR

IENL

Interrupt Enable

IRQL

IRQH

Interrupt

Vector

Address

Generator

Internal bus line

Release STOP

To CPU

Interrupt Master
Enable Flag

I-flag

IENH

r
i
o

ty C

ont

rol

I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.

INT2R

T0R

BITR

KSCNR

Key Scan

Basic Interval Timer

INT1R

T2R

T1R

Timer 2

Timer 1

Timer 0

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

14.1 Interrupt priority and sources

Each interrupt vector is independent and has its own pri-
ority. Software interrupt (BRK) is also available. Interrupt

source classification is shown in Table 14-1.

14.2 Interrupt control register

I flag of PSW is a interrupt mask enable flag. When I flag
= "0", all interrupts become disable. When I flag = "1", in-
terrupts can be selectively enabled and disabled by con-
tents of corresponding Interrupt Enable Register. When
interrupt is occured, interrupt request flag is set, and Inter-
rupt request is detected at the edge of interrupt signal. The
accepted interrupt request flag is automatically cleared
during interrupt cycle process. The interrupt request flag
maintains "1" until the interrupt is accepted or is cleared in
program. In reset state, interrupt request flag register
(IRQH, IRQL) is cleared to "0". It is possible to read the
state of interrupt register and to mainpulate the contents of
register and to generate interrupt. (Refer to software inter-
rupt)

Reset/Interrupt

Symbol

Priority

Hardware Reset

RESET

Key Scan

KSCNR

External Interrupt1

INT1R

External Interrupt2

INT2R

Timer0

T0R

Timer1

T1R

Timer2

T2R

Watch Dog Timer

WDTR

Basic Interval Timer

BITR

BRK Instruction

BRK

Table 14-1 Interrupt Source

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

14.3 Interrupt accept mode

The interrupt priority order is determined by bit (IM1,
IM0) of IMOD register. The condition allow for accepting
interrupt is set state of the interrupt mask enable flag and

the interrupt enable bit must be "1". In Reset state, these
IP3 - IP0 registers become all "0".

Figure 14-2 Interrupt Enable & Request Flag

0: Disable
1: Enable

VALUE

R/W

INITIAL VALUE: 000- 000-

ADDRESS: 0CE

IENH

INT1E

MSB

LSB

T0E

T1E

INT2E

R/W

External interrupt 1

INITIAL VALUE: -00- ----

ADDRESS: 0CC

IENL

MSB

LSB

Timer1

R/W

Basic Interval Timer

Watchdog timer

External interrupt 2

Key scan

WDTE

R/W

BITE

KSCNE

T2E

Timer2

Timer0

R/W

INITIAL VALUE: 000- 000-

ADDRESS: 0CF

IRQH

INT1R

MSB

LSB

T0R

T1R

INT2R

R/W

External interrupt 1

INITIAL VALUE: -00- ----

ADDRESS: 0CD

IRQL

MSB

LSB

Timer1

R/W

Basic Interval Timer

Watchdog timer

External interrupt 2

Key scan

WDTR

R/W

BITR

KSCNR

T2R

Timer2

Timer0

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

14.4 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the
interrupt latch is cleared to "0" by a reset or an instruction. Inter-
rupt acceptance sequence requires 8

XIN

after the completion of

the current instruction execution. The interrupt service task is ter-
minated upon execution of an interrupt return instruction [RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

"0" to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following
interrupts is temporarily disabled.

2. Interrupt request flag for the interrupt source accepted is

cleared to "0".

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is

read from the vector table address and the entry address
is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

Figure 14-3 Interrupt Accept Mode & Selection by IP3~IP0

BT C L

IM 1

INITIAL VALUE: --00_0000

ADDRESS: 0CA

IMOD

IP1

IP0

R/W

IM 0

Interrupt mode register

Selection interrupt

00: Fixed by hardware
01: Changeable by IP3~IP0

Priority

R/W

0001: KSCNR
0010: INT1R
0011: INT2R
0101: T0R
0110: T1R
0111: T2R
1010: WDTR
1011: BITR

IP 2

IP 3

1x: Interrupt is inhibited

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Figure 14-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

A interrupt request is not accepted until the I-flag is set to "1"
even if a requested interrupt has higher priority than that of the
current interrupt being serviced.

When nested interrupt service is required, the I-flag should be set
to "1" by "EI" instruction in the interrupt service program. In this
case, acceptable interrupt sources are selectively enabled by the
individual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program counter and
the program status word are automatically saved on the stack, but
accumulator and other registers are not saved itself. These regis-
ters are saved by the software if necessary. Also, when multiple
interrupt services are nested, it is necessary to avoid using the
same data memory area for saving registers.

The following method is used to save/restore the general-purpose

registers.

Example: Register save using push and pop instructions

General-purpose register save/restore using push and pop instruc-
tions;

V.L.

System clock

Address Bus

SP-1

SP-2

V.H.

New PC

V.L.

Data Bus

Not used

PCH

PCL

PSW

ADL

OP code

ADH

Instruction Fetch

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.

External Interrupt1

012

0E3

0FFF8

0FFF9

0E312

0E313

Entry Address

Correspondence between vector table address for Exteranl Interrupt1
and the entry address of the interrupt service program.

Vector Table Address

INTxx:

PUSH

;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.

interrupt processing

POP

RETI

;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN

main task

interrupt
service task

saving
registers

restoring
registers

acceptance of

interrupt

interrupt return

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

14.5 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.

Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK inter-
rupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.

Each processing step is determined by B-flag as shown in Figure
14-5

Figure 14-5 Execution of BRK/TCALL0

14.6 Multi Interrupt

If two requests of different priority levels are received simulta-
neously, the request of higher priority level is serviced. If re-
quest s of the i nt err upt are recei ved at t he same ti me
simultaneously, an internal polling sequence determines by hard-
ware which request is serviced.

However, multiple processing through software for special fea-
tures is possible. Generally when an interrupt is accepted, the I-
flag is cleared to disable any further interrupt. But as user sets I-
flag in interrupt routine, some further interrupt can be serviced
even if certain interrupt is in progress.

Example: During Timer1 interrupt is in progress, INT1 interrupt
serviced without any suspend.

TIMER1:

PUSH

LDM

IENH,#40H

;

Enable INT1 only

LDM

IENL,#00H

;

Disable other

;

Enable Interrupt

:
:

:
:
LDM

IENH,#0FFH

;

Enable all interrupts

LDM

IENL,#0FFH

POP

RETI

Figure 14-6 Execution of Multi Interrupt

14.7 External Interrupt

The external interrupt on INT1 and INT2 pins are edge triggered
depending on the edge selection register IEDS (address 0D8

) as

shown in Figure14-7.

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

TCALL0

ROUTINE

RET

BRK or

TCALL0

enable INT1

TIMER 1
service

INT1
service

Main Program
service

Occur
TIMER1 interrupt

Occur
INT1

disable other

enable INT1
enable other

In this example, the INT1 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Response Time

The INT1 ~ INT2 edge are latched into IFINT1 ~ IFINT2 at every
machine cycle. The values are not actually polled by the circuitry
until the next machine cycle. If a request is active and conditions
are right for it to be acknowledged, a hardware subroutine call to
the requested service routine will be the next instruction to be ex-
ecuted. The DIV itself takes twelve cycles. Thus, a minimum of
twelve complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution of the
first instruction of the service routine.

Figure 14-8 shows interrupt response timings.

Figure 14-8 Interrupt Response Timing Diagram

14.8 Key Scan Input Processing

Key Scan Interrupt is generated by detecting low or high
Input from each Input pin (R0, R1) is one of the sources
which release standby (SLEEP, STOP) mode. Key Scan
ports are all 16bit which are controlled by Standby Mode
Release Register (SMRR0, SMRR1). Key Input is consid-
ered as Interrupt, therefore, KSCNE bit of IEHN should be

set for correct interrupt executing, SLEEP mode and STOP
mode, the rest of executing is the same as that of external
Interrupt. Each SMRR Register bit is allowed for each port
(for Bit= "0", no Key Input, for Bit= "1", Key Input avail-
able). At reset, SMRR becomes "00h". So, there is no Key
Input source.

Figure 14-7 External Interrupt Block Diagram

IFINT1

INT1 pin

INT1 INTERRUPT

IFINT2

INT2 pin

INT2 INTERRUPT

IEDS

[0CBH]

Edge selection
Register

BT C L

IED 2H

INITIAL VALUE: 0000_0000

ADDRESS: 0CB

IEDS

Ext. Int. Edge Selection reg.

01: Falling Edge Selection
10: Rising Edge Selection

IED2*

11: Both Edsg Selection

IED 2L IE D 1H

IED 1L

01: Falling Edge Selection
10: Rising Edge Selection

IED1*

11: Both Edsg Selection

Interrupt
goes
active

Interrupt
latched

Interrupt
processing

Interrupt
routine

8 f

XIN

period

max. 12 f

XIN

period

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Standby release level control register (SRLC) can select
the key scan input level "L" or "H" for standby release by
each bit pin (R0, R1). Standby release level control register

(SRLC) is write-only register and initialized as "00h" in re-
set state.

Figure 14-9 Block Diagram of Key Scan Block

BT C L

INITIAL VALUE: 00

ADDRESS: 0DC

SMRR0

KR 07

R 03

R 02

R 0 1

R 04

R 05

R 06
R 07

R 0 0

R0 PORT LOGIC

R 13

R 12

R 1 1

R 14

R 15

R 16
R 17

R 1 0

SMRR0

SRLC0

R1 PORT LOGIC

SMRR1

SRLC1

Internal
Key Scan
Input

KR 06

KR 05

K R 04

KR 03

KR 02

K R 01

K R 00

KR 0*

1: Select
0: N o S elect

BT C L

INITIAL VALUE: 00

ADDRESS: 0DD

SMRR1

KR 17

KR 16

KR 15

K R 14

KR 13

KR 12

K R 11

K R 10

KR 1*

1: Select
0: N o S elect

BT C L

INITIAL VALUE: 00

ADDRESS: 0F6

SRLC0

KLR 07

K LR 06 KLR 05

KLR 04 KLR 03 K LR 02 K LR01 K LR 00

KLR 0*
1: H igh
0: Low

BT C L

INITIAL VALUE: 00

ADDRESS: 0F7

SRLC1

K LR 17

K LR 16 K LR 15

KLR 14 K LR 13 K LR 12 KLR 11 KLR10

K LR 1*
1: H igh
0: Low

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

15. STANDBY FUNCTION

15.1 Sleep Mode

SLEEP mode can be entered by setting the bit of SLEEP
mode register (SLPM). In the mode, CPU clock stops but
oscillator keeps running. B.I.T and a part of peripheral
hardware execute, but prescalerís output which provide
clock to peripherals can be stopped by program. (Except,
PS10 can't stopped.) In SLEEP mode, more consuming
power can be saved by not using other peripheral hardware
except for B.I.T. By setting ENPCK (peripheral clock con-
trol bit) of CKCTLR (clock control register) to "0", periph-
eral hardware halted, and SLEEP mode is entered. To
release SLEEP mode by BITR (basic interval timer inter-
rupt), bit10 of prescaler should be selected as B.I.T input
clock before entering SLEEP mode. "NOP" instruction
should be follows setting of SLEEP mode for rising pre-
charge time of data bus line.

(ex) setting of SLEEP mode : set the bit of SLEEP

; mode register (SLPM)

NOP : NOP instruction

15.2 STOP MODE

STOP mode can be entered by STOP instruction during
program. In STOP mode, oscillator is stopped to make all
clocks stop, which leads to less power consumption. All
registers and RAM data are preserved. "NOP" instruction
should be follows STOP instruction for rising precharge

time of Data Bus line.

(ex) STOP : STOP instruction execution

NOP : NOP instruction

Sleep Mode Control Register (W)

SLPM

ADDRESS : 0F0

INITIAL VALUE : -------0b

SLPM0

1: sleep mode

Clock Control Register (W)

CKCTLR

ADDRESS : 0C7

INITIAL VALUE : --110111b

ENPCK 0: Stopped

1: Provided

0: Sleep mode release

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

15.3 STANDBY MODE RELEASE

Release of STANDBY mode is executed by RESET input
and Interrupt signal. Register value is defined when Reset.
When there is a release signal of STOP mode (Interrupt,
RESET input), the instruction execution starts after stabi-
lization oscillation time is set by value of BTS2 ~ BTS0
and set ENPCK to "1".

Figure 15-1 Block Diagram of Standby Circuit

OSC
Circuit

Clock Pulse
Generator

CPU Clock

Release Signal from Interrupt

RESETB

STOP

Control Signal

Overflow Detection

it7

Prescaler

Clear

MUX

Basic
Interval
Timer

Clear

Release Signal

SLEEP

STOP

RESETB

KSCN(Key Input)

INT1,INT2

B.I.T.

Table 15-1 Release Signal of Standby Mode

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

Release Factor

Release Method

RESETB

By RESETB Pin=Low level, Standby mode is releas and system is initialized

KSCN(Key Input)

Standby mode is released by low input of selected pin by key scan Input(SMRR0,SMRR1).
In case of interrupt mask enable flag= "0", program executes just after standby instruction,
if flag= "1" enters each interrupt service routine.

INT1,INT2

When external interrupt (INT1,INT2)

enable flag is "1", standby mode is released at the

rising edge of each terminal. When standby mode is released at interrupt. Mask Enable
flag= "0", program executes from the next instruction of standby instruction. When "1",
enters each interrupt service routine.

Basic Interval

Timer(IFBIT)

When B.I.T. is executed only by bit10 of prescaler(PS10), SLEEP mode can be released.
Interrupt release SLEEP mode , when BIT interrupt enable flag is "1". When standby mode
is released at interrupt. Mask enable flag= "0", program executes from the next instruction
of SLEEP instruction. When "1", enters each interrupt service routine.

Table 15-2

Figure 15-2 Block Diagram of Standby Circuit

[SLEEP MODE]

Xin

SLEEP command

SLEEP mode

release by interrupt

RESET

Longer than 2 machine cycle

[STOP MODE]

Xin

STOP mode

release by interrupt

RESET

Stable OSC.time

Program setting time by CKCTLR

Longer than stabe OSC. Time

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

15.4 RELEASE OPERATION OF STANDBY MODE

After standby mode is released, the operation begins ac-
cording to content of related interrupt register just before

standby mode start (Figure 15-3).

(1) Interrupt Enable Flag(I) of PSW = "0"

Release by only interrupt which interrupt enable flag =
"1", and starts to execute from next to standby instruction
(SLEEP or STOP).

(2) Interrupt Enable Flag(I) of PSW = "1"

Released by only interrupt which each interrupt enable flag
= "1", and jump to the relevant interrupt service routine.

Note: When STOP instruction is used, B.I.T should guar-
antee the stabilization oscillation time. Thus, just before en-

tering STOP mode, clock of bit10 (PS10) of prescaler is
selected or peripheral hardware clock control bit (ENPCK)
to "1", Therefore the clock necessary for stabilization oscil-
lation time should be input into B.I.T. otherwise, standby
mode is released by reset signal. In case of interrupt re-
quest flag and interrupt enable flag are both "1", standby
mode is not entered.

Figure 15-3 Standby Mode Release Flow

STOP Command

Interrupt Request GEN.

Int. enable reg.

Standby Mode

PSW
I Flag

Standby Mode Release

Interrupt Service Routine

Standby Next Command
Execution

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

16. RESET FUNCTION

16.1 EXTERNAL RESET

The RESET pin should be held at low for at least 2machine
cycles with the power supply voltage within the operating
voltage range and must be connected 0.1uF capacitor for

stable system initialization. The RESET pin contains a
Schmitt trigger with an internal pull-up resistor.

16.2 POWER ON RESET

Power On Reset circuit automatically detects the rise of
power voltage (the rising time should be within 50ms) the
power voltage reaches a certain level, RESET terminal is
maintained at "L" Level until a crystal ceramic oscillator
oscillates stably. After power applies and starting of oscil-
lation, this reset state is maintained for about oscillation
cycle of 219 (about 65.5ms : at 4MHz).The execution of
built-in Power On Reset circuit is as follows :

(1) Latch the pulse from Power On Detection Pulse Gener-
ator circuit, and reset Prescaler, B.I.T and B.I.T Overflow

detection circuit.

(2) Once B.I.T Overflow detection circuit is reset. Then,
Prescaler starts to count.

(3) Prescaler output is inputted into B.I.T and PS10 of
Prescaler output is automatically selected. If overflow of
B.I.T is detected, Overflow detection circuit is set.

4) Reset circuit generates maximum period of reset pulse
from Prescaler and B.I.T

Figure 16-1 RESET Pin connection

RESET

GND

0.1uF capacitor

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

16.3 Low Voltage Detection Mode

(1) Low voltage detection condition

An on board voltage comparator checks that VDD is at the
required level to ensure correct operation of the device. If
VDD is below a certain level, Low voltage detector forces
the device into low voltage detection mode.

(2) Low Voltage Detection Mode

There is no power consumption except stop current, stop
mode release function is disabled. All I/O port is config-
ured as input mode and Data memory is retained until volt-
age through external capacitor is worn out. In this mode,

all port can be selected with Pull-up resistor by Mask op-
tion. If there is no information on the Mask option sheet
,the default pull up option (all port connect to pull-up resis-
tor ) is selected.

(3) Release of Low Voltage Detection Mode

Reset signal result from new battery(normally 3V) wakes
the low voltage detection mode and come into normal reset
state. It depends on user whether to execute RAM clear
routine or not

Figure 16-4 Timing Diagram of Reset

MAIN PROGRAM

Oscillator

pin)

FFFE FFFF

Stabilization Time

RESET

ADDRESS

DATA

Start

ADL

ADH

BUS

RESET Process Step

~~
~~

ADL and ADH are start addresses of interrupt service routine as vector contents.

Figure 16-5 Low Voltage vs Temperature

1.55

1.60

1.65

1.70

1.75

1.80

1.85

-25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

LVD(V)

Temperature (

A. MASK ORDER SHEET

1. Customer Information

Company Name

2. Device Information

4. Marking Specification

5. Delivery Schedule

Customer Sample

Date

YYYY

Risk Order

YYYY

Quantity

Hynix Confirmation

Application

Order Date

Tel:

Fax:

Package

20SOP

20PDIP

6. ROM Code Verification

Verification D ate:

YYYY

Approval Date:

YYYY

P lease confirm our verification data.

I agree w ith your verification data and confirm
you to m ake m ask set.

Check Sum:

Tel:

Fax:

Name &
Signature:

Tel:

Fax:

Name &
Signature:

Mask Data

File Name: ( .OTP)

(Please check mark into )

pcs

Check Sum ( @27c256)

Customer should write inside thick line box.

This box is written after "6.Verification".

28SOP

28SKDIP

24SOP

24SKDIP

YYWW

KOREA

Customer's logo

Customer logo is not required.

YYWW

KOREA

HMS810

Customer's part number

If the customer logo must be used in the special mark, please submit a clean original of the logo.

04/08/16/24/32

Name&Signature:

JUNE 2001

MASK ORDER & VERIFICATION SHEET

HMS810

E -UE

Lot Number

Hynix ROM Code
Number

YYYY

28PIN DIE

HMS810

E -UE

3. Inclusion of pull-up resistor in Low Volatage Detection mode

Port R00 R01 R02 R03 R04 R05 R06 R07

R10 R11 R12 R13 R14 R15 R16 R17

R20 R21 R22 R23 R24

Y/N

*1 : is not avilable for 20PIN. So default option is pull-up on.

*2 : is not avilable for 20PIN & 24PIN. So default option is pull-up on.

APPENDIX

JUNE 2001 Ver 1.00

lxxi

B. INSTRUCTION

B.1 Terminology List

Terminology

Description

Accumulator

X - register

Y - register

PSW

Program Status Word

#imm

8-bit Immediate data

Direct Page Offset Address

!abs

Absolute Address

[ ]

Indirect expression

{ }

{ }+

.bit

Bit Position

A.bit

Bit Position of Accumulator

dp.bit

Bit Position of Direct Page Memory

M.bit

Bit Position of Memory Data (000

~0FFF

)

rel

Relative Addressing Data

upage

U-page (0FF00

~0FFFF

) Offset Address

Table CALL Number (0~15)

Addition

Upper Nibble Expression in Opcode

Subtraction

Multiplication

Division

( )

Contents Expression

AND

Exclusive OR

NOT

Assignment / Transfer / Shift Left

Shift Right

Exchange

Equal

Not Equal

Bit Position

APPENDIX

lxxii

JUNE 2001 Ver 1.00

B.2 Instruction Map

LOW

HIGH

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

000

SET1
dp.bit

BBS

A.bit,rel

BBS

dp.bit,rel

ADC

#imm

ADC

dp+X

ADC

!abs

ASL

TCALL

SETA1

.bit

BIT

POP

PUSH

BRK

001

CLRC

SBC

#imm

SBC

dp+X

SBC

!abs

ROL

TCALL

CLRA1

.bit

COM

POP

PUSH

BRA

rel

010

CLRG

CMP

#imm

CMP

dp+X

CMP

!abs

LSR

TCALL

NOT1

M.bit

TST

POP

PUSH

PCALL

Upage

011

#imm

dp+X

!abs

ROR

TCALL

OR1

OR1B

CMPX

POP

PSW

PUSH

PSW

RET

100

CLRV

AND

#imm

AND

dp+X

AND

!abs

INC

TCALL

AND1

AND1B

CMPY

CBNE

dp+X

TXSP

INC

101

SETC

EOR

#imm

EOR

dp+X

EOR

!abs

DEC

TCALL

EOR1

EOR1B

DBNE

XMA

dp+X

TSPX

DEC

110

SETG

LDA

#imm

LDA

dp+X

LDA
!abs

TXA

LDY

TCALL

LDC

LDCB

LDX

dp+Y

XCN

DAS

111

LDM

dp,#imm

STA

dp+X

STA
!abs

TAX

STY

TCALL

STC

M.bit

STX

dp+Y

XAX

STOP

LOW

HIGH

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

000

BPL

rel

CLR1

dp.bit

BBC

A.bit,rel

BBC

dp.bit,rel

ADC

{X}

ADC

!abs+Y

ADC

[dp+X]

ADC

[dp]+Y

ASL
!abs

ASL

dp+X

TCALL

JMP

!abs

BIT

!abs

ADDW

LDX

#imm

JMP

[!abs]

001

BVC

rel

SBC

{X}

SBC

!abs+Y

SBC

[dp+X]

SBC

[dp]+Y

ROL

!abs

ROL

dp+X

TCALL

CALL

!abs

TEST

!abs

SUBW

LDY

#imm

JMP

[dp]

010

BCC

rel

CMP

{X}

CMP

!abs+Y

CMP

[dp+X]

CMP

[dp]+Y

LSR
!abs

LSR

dp+X

TCALL

MUL

TCLR1

!abs

CMPW

CMPX

#imm

CALL

[dp]

011

BNE

rel

{X}

!abs+Y

[dp+X]

[dp]+Y

ROR

!abs

ROR

dp+X

TCALL

DBNE

CMPX

!abs

LDYA

CMPY

#imm

RETI

100

BMI

rel

AND

{X}

AND

!abs+Y

AND

[dp+X]

AND

[dp]+Y

INC

!abs

INC

dp+X

TCALL

DIV

CMPY

!abs

INCW

INC

TAY

101

BVS

rel

EOR

{X}

EOR

!abs+Y

EOR

[dp+X]

EOR

[dp]+Y

DEC

!abs

DEC

dp+X

TCALL

XMA

{X}

XMA

DECW

DEC

TYA

110

BCS

rel

LDA

{X}

LDA

!abs+Y

LDA

[dp+X]

LDA

[dp]+Y

LDY
!abs

LDY

dp+X

TCALL

LDA
{X}+

LDX
!abs

STYA

XAY

DAA

111

BEQ

rel

STA

{X}

STA

!abs+Y

STA

[dp+X]

STA

[dp]+Y

STY
!abs

STY

dp+X

TCALL

STA
{X}+

STX
!abs

CBNE

XYX

NOP

APPENDIX

JUNE 2001 Ver 1.00

lxxiii

B.3 Instruction Set

Arithmetic / Logic Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

ADC #imm

Add with carry.

ADC dp

( A ) + ( M ) + C

ADC dp + X

ADC !abs

NV--H-ZC

ADC !abs + Y

ADC [ dp + X ]

ADC [ dp ] + Y

ADC { X }

AND #imm

Logical AND

AND dp

( A )

( M )

AND dp + X

AND !abs

N-----Z-

AND !abs + Y

AND [ dp + X ]

AND [ dp ] + Y

AND { X }

ASL A

Arithmetic shift left

ASL dp

N-----ZC

ASL dp + X

ASL !abs

CMP #imm

Compare accumulator contents with memory contents
( A ) - ( M )

CMP dp

CMP dp + X

CMP !abs

N-----ZC

CMP !abs + Y

CMP [ dp + X ]

CMP [ dp ] + Y

CMP { X }

CMPX #imm

Compare X contents with memory contents

CMPX dp

( X ) - ( M )

N-----ZC

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

CMPY dp

( Y ) - ( M )

N-----ZC

CMPY !abs

COM dp

1'S Complement : ( dp )

~( dp )

N-----Z-

DAA

Decimal adjust for addition

N-----ZC

DAS

Decimal adjust for subtraction

N-----ZC

DEC A

Decrement

N-----Z-

DEC dp

( M ) - 1

N-----Z-

DEC dp + X

N-----Z-

DEC !abs

N-----Z-

DEC X

N-----Z-

DEC Y

N-----Z-

7 6 5 4 3 2 1 0

"0"

APPENDIX

lxxiv

JUNE 2001 Ver 1.00

DIV

Divide : YA / X Q: A, R: Y

NV--H-Z-

EOR #imm

Exclusive OR

EOR dp

( A )

( M )

EOR dp + X

EOR !abs

N-----Z-

EOR !abs + Y

EOR [ dp + X ]

EOR [ dp ] + Y

EOR { X }

INC A

Increment

N-----ZC

INC dp

( M ) + 1

N-----Z-

INC dp + X

N-----Z-

INC !abs

N-----Z-

INC X

N-----Z-

INC Y

N-----Z-

LSR A

Logical shift right

LSR dp

N-----ZC

LSR dp + X

LSR !abs

MUL

Multiply : YA

N-----Z-

OR #imm

Logical OR

OR dp

( A )

( M )

OR dp + X

OR !abs

N-----Z-

OR !abs + Y

OR [ dp + X ]

OR [ dp ] + Y

OR { X }

ROL A

Rotate left through Carry

ROL dp

N-----ZC

ROL dp + X

ROL !abs

ROR A

Rotate right through Carry

ROR dp

N-----ZC

ROR dp + X

ROR !abs

SBC #imm

Subtract with Carry

SBC dp

( A ) - ( M ) - ~( C )

SBC dp + X

SBC !abs

NV--HZC

SBC !abs + Y

SBC [ dp + X ]

SBC [ dp ] + Y

SBC { X }

TST dp

Test memory contents for negative or zero, ( dp ) - 00

N-----Z-

XCN

Exchange nibbles within the accumulator
A

N-----Z-

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

7 6 5 4 3 2 1 0

"0"

7 6 5 4 3 2 1 0

APPENDIX

JUNE 2001 Ver 1.00

lxxv

Register / Memory Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

LDA #imm

Load accumulator

LDA dp

( M )

LDA dp + X

LDA !abs

LDA !abs + Y

N-----Z-

LDA [ dp + X ]

LDA [ dp ] + Y

LDA { X }

LDA { X }+

X- register auto-increment : A

( M ) , X

X + 1

LDM dp,#imm

Load memory with immediate data : ( M )

imm

--------

LDX #imm

Load X-register

LDX dp

( M )

N-----Z-

LDX dp + Y

LDX !abs

LDY #imm

Load Y-register

LDY dp

( M )

N-----Z-

LDY dp + X

LDY !abs

STA dp

Store accumulator contents in memory

STA dp + X

( M )

STA !abs

STA !abs + Y

--------

STA [ dp + X ]

STA [ dp ] + Y

STA { X }

STA { X }+

X- register auto-increment : ( M )

A, X

X + 1

STX dp

Store X-register contents in memory

STX dp + Y

( M )

--------

STX !abs

STY dp

Store Y-register contents in memory

STY dp + X

( M )

--------

STY !abs

TAX

Transfer accumulator contents to X-register : X

N-----Z-

TAY

Transfer accumulator contents to Y-register : Y

N-----Z-

TSPX

Transfer stack-pointer contents to X-register : X

N-----Z-

TXA

Transfer X-register contents to accumulator: A

N-----Z-

TXSP

Transfer X-register contents to stack-pointer: sp

N-----Z-

TYA

Transfer Y-register contents to accumulator: A

N-----Z-

XAX

Exchange X-register contents with accumulator :X

--------

XAY

Exchange Y-register contents with accumulator :Y

--------

XMA dp

Exchange memory contents with accumulator

XMA dp+X

( M )

N-----Z-

XMA {X}

XYX

Exchange X-register contents with Y-register : X

--------

APPENDIX

lxxvi

JUNE 2001 Ver 1.00

16-BIT operation

Bit Manipulation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

ADDW dp

16-Bits add without Carry
YA

( YA ) ( dp +1 ) ( dp )

NV--H-ZC

CMPW dp

Compare YA contents with memory pair contents :
(YA)

(dp+1)(dp)

N-----ZC

DECW dp

Decrement memory pair
( dp+1)( dp)

( dp+1) ( dp) - 1

N-----Z-

INCW dp

Increment memory pair
( dp+1) ( dp)

( dp+1) ( dp ) + 1

N-----Z-

LDYA dp

Load YA
YA

( dp +1 ) ( dp )

N-----Z-

STYA dp

Store YA
( dp +1 ) ( dp )

--------

SUBW dp

16-Bits subtract without carry
YA

( YA ) - ( dp +1) ( dp)

NV--H-ZC

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

AND1 M.bit

Bit AND C-flag : C

( C )

( M .bit )

-------C

AND1B M.bit

Bit AND C-flag and NOT : C

( C )

~( M .bit )

-------C

BIT dp

Bit test A with memory :

MM----Z-

BIT !abs

( A )

( M ) , N

( M

) , V

( M

)

CLR1 dp.bit

Clear bit : ( M.bit )

"0"

--------

CLRA1 A.bit

Clear A bit : ( A.bit )

"0"

--------

CLRC

Clear C-flag : C

"0"

-------0

CLRG

Clear G-flag : G

"0"

--0-----

CLRV

Clear V-flag : V

"0"

-0--0---

EOR1 M.bit

Bit exclusive-OR C-flag : C

( C )

( M .bit )

-------C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

( C )

~(M .bit)

-------C

LDC M.bit

Load C-flag : C

( M .bit )

-------C

LDCB M.bit

Load C-flag with NOT : C

~( M .bit )

-------C

NOT1 M.bit

Bit complement : ( M .bit )

~( M .bit )

--------

OR1 M.bit

Bit OR C-flag : C

( C )

( M .bit )

-------C

OR1B M.bit

Bit OR C-flag and NOT : C

( C )

~( M .bit )

-------C

SET1 dp.bit

Set bit : ( M.bit )

"1"

--------

SETA1 A.bit

Set A bit : ( A.bit )

"1"

--------

SETC

Set C-flag : C

"1"

-------1

SETG

Set G-flag : G

"1"

--1-----

STC M.bit

Store C-flag : ( M .bit )

--------

TCLR1 !abs

Test and clear bits with A :
A - ( M ) , ( M )

( M )

~( A )

N-----Z-

TSET1 !abs

Test and set bits with A :
A - ( M ) , ( M )

( M )

( A )

N-----Z-

APPENDIX

JUNE 2001 Ver 1.00

lxxvii

Branch / Jump Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

BBC A.bit,rel

4/6

Branch if bit clear :

--------

BBC dp.bit,rel

5/7

if ( bit ) = 0 , then pc

( pc ) + rel

BBS A.bit,rel

4/6

Branch if bit set :

--------

BBS dp.bit,rel

5/7

if ( bit ) = 1 , then pc

( pc ) + rel

BCC rel

2/4

Branch if carry bit clear
if ( C ) = 0 , then pc

( pc ) + rel

--------

BCS rel

2/4

Branch if carry bit set
if ( C ) = 1 , then pc

( pc ) + rel

--------

BEQ rel

2/4

Branch if equal
if ( Z ) = 1 , then pc

( pc ) + rel

--------

BMI rel

2/4

Branch if minus
if ( N ) = 1 , then pc

( pc ) + rel

--------

BNE rel

2/4

Branch if not equal
if ( Z ) = 0 , then pc

( pc ) + rel

--------

BPL rel

2/4

Branch if plus
if ( N ) = 0 , then pc

( pc ) + rel

--------

BRA rel

Branch always
pc

( pc ) + rel

--------

BVC rel

2/4

Branch if overflow bit clear
if (V) = 0 , then pc

( pc) + rel

--------

BVS rel

2/4

Branch if overflow bit set
if (V) = 1 , then pc

( pc ) + rel

--------

CALL !abs

Subroutine call

CALL [dp]

M( sp)

( pc

), sp

sp - 1, M(sp)

(pc

), sp

sp - 1,

if !abs, pc

abs ; if [dp], pc

( dp ), pc

( dp+1 ) .

--------

CBNE dp,rel

5/7

Compare and branch if not equal :

--------

CBNE dp+X,rel

6/8

if ( A )

( M ) , then pc

( pc ) + rel.

DBNE dp,rel

5/7

Decrement and branch if not equal :

--------

DBNE Y,rel

4/6

if ( M )

0 , then pc

( pc ) + rel.

JMP !abs

Unconditional jump

JMP [!abs]

jump address

--------

JMP [dp]

PCALL upage

U-page call
M(sp)

( pc

), sp

sp - 1, M(sp)

( pc

sp - 1, pc

( upage ), pc

"0FF

" .

--------

TCALL n

Table call : (sp)

( pc

), sp

sp - 1,

M(sp)

( pc

),sp

sp - 1,

(Table vector L), pc

(Table vector H)

--------

APPENDIX

lxxviii

JUNE 2001 Ver 1.00

Control Operation & Etc.

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

BRK

Software interrupt : B

"1", M(sp)

(pc

), sp

sp-1,

M(s)

(pc

), sp

sp - 1, M(sp)

(PSW), sp

sp -1,

( 0FFDE

) , pc

( 0FFDF

) .

---1-0--

Disable all interrupts : I

"0"

-----0--

Enable all interrupt : I

"1"

-----1--

NOP

No operation

--------

POP A

sp + 1, A

M( sp )

POP X

sp + 1, X

M( sp )

--------

POP Y

sp + 1, Y

M( sp )

POP PSW

sp + 1, PSW

M( sp )

restored

PUSH A

M( sp )

A , sp

sp - 1

PUSH X

M( sp )

X , sp

sp - 1

--------

PUSH Y

M( sp )

Y , sp

sp - 1

PUSH PSW

M( sp )

PSW , sp

sp - 1

RET

Return from subroutine
sp

sp +1, pc

M( sp ), sp

sp +1, pc

M( sp )

--------

RETI

Return from interrupt
sp

sp +1, PSW

M( sp ), sp

sp + 1,

M( sp ), sp

sp + 1, pc

M( sp )

restored

STOP

Stop mode ( halt CPU, stop oscillator )

--------

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HMS81032TL

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HMS81032TL