HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

1. OVERVIEW ....................................................................................................................... 1

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2. BLOCK DIAGRAM ........................................................................................................... 4

3. PIN ASSIGNMENT ........................................................................................................... 5

4. PACKAGE DIAGRAM ...................................................................................................... 6

5. PIN FUNCTION ................................................................................................................. 9

6. PORT STRUCTURES ..................................................................................................... 11

7. ELECTRICAL CHARACTERISTICS .............................................................................. 16

7.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6 Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8. MEMORY ORGANIZATION ........................................................................................... 22

8.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.4 Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9. I/O PORTS ...................................................................................................................... 34

9.1 RA and RAIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2 RB and RBIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3 RC and RCIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.4 RD and RDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10. CLOCK GENERATOR ................................................................................................. 38

10.1 Oscillation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11. BASIC INTERVAL TIMER ............................................................................................ 40

12. TIMER / COUNTER ...................................................................................................... 41

12.1 8-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

12.2 16-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.3 8-bit Compare Output (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.4 8-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.5 16-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.6 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13. BUZZER OUTPUT FUNCTION .................................................................................... 50

14. ANALOG TO DIGITAL CONVERTER .......................................................................... 51

15. INTERRUPTS ............................................................................................................... 54

15.1 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
15.2 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

16. WATCHDOG TIMER .................................................................................................... 59

17. POWER SAVING MODE .............................................................................................. 60

17.1 Minimizing Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

18. RESET .......................................................................................................................... 66

19. POWER FAIL PROCESSOR ........................................................................................ 68

20. OTP PROGRAMMING .................................................................................................. 70

20.1 DEVICE CONFIGURATION AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

APPENDIX

Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

HMS87C1304A / HMS87C1302A
HMS87C1204A / HMS87C1202A

HMS87C1104A / HMS87C1102A

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

1. OVERVIEW

1.1 Description

The HMS87C1X0XA is an advanced CMOS 8-bit microcontroller with 4K/2K bytes of EPROM. The Hynix
HMS87C1X0XA is a powerful microcontroller which provide a highly flexible and cost effective solution to many small
applications such as controller for battery charger. The HMS87C1X0XA provides the following standard features: 4K/2K
bytes of EPROM, 128bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit high speed PWM output, programmable
buzzer driving port, power-on reset circuit, on-chip oscillator and clock circuitry. In addition, the HMS87C1X0XA supports
power saving modes to reduce power consumption.

This document is only explained for the base of HMS87C1304A, the other's eliminated functions are same as below.

1.2 Features

� 4K/2K Bytes On-chip Program Memory

� 128 Bytes of On-chip Data RAM

(Included stack memory)

� Instruction Cycle Time:

- 250nS at 8MHz

� Programmable I/O pins

(LED direct driving can be source and sink)
- HMS87C1304A/1302A : 19
- HMS87C1204A/1202A : 15
- HMS87C1104A/1102A : 11

� 2.0V to 5.5V Wide Operating Range

� 8-bit A/D Converter

- 8 channels

� One 8-bit Basic Interval Timer

� Two 8-bit Timer / Counters

� One 10-bit High Speed PWM Outputs

� Watchdog timer

� Seven Interrupt sources

- External input: 2 ( 1 for HMS87C1104/2A )
- A/D Conversion: 1
- Timer: 4

� One Programmable Buzzer Driving port

( except HMS87C1104/2A )
- 500Hz ~ 130kHz

Device name

EPROM

RAM

EXT.INT

BUZ

I/O

Operating

Voltage

Package

HMS87C1304A

4K bytes

128bytes

2.0 ~ 5.5V

24 SKDIP or SOP

HMS87C1302A

2K bytes

128bytes

2.0 ~ 5.5V

24 SKDIP or SOP

HMS87C1204A

4K bytes

128bytes

2.0 ~ 5.5V

20 PDIP or SOP

HMS87C1202A

2K bytes

128bytes

2.0 ~ 5.5V

20 PDIP or SOP

HMS87C1104A

4K bytes

128bytes

2.0 ~ 5.5V

16 PDIP or SOP

HMS87C1102A

2K bytes

128bytes

2.0 ~ 5.5V

16 PDIP or SOP

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

� Oscillator Type

- Crystal
- Ceramic Resonator
- RC-oscillation ( C can be omitted )

� Power-On Reset

� Noise Immunity Circuit

- Power Fail Processor

� Power Down Mode

- STOP mode
- Wake-up Timer mode
- Internal RC-WDT mode

1.3 Development Tools

The HMS87C1X0XA is supported by a full-featured mac-
ro assembler, an in-circuit emulator CHOICE-Dr

and

OTP programmers.

The marco assembler operates under the MS-Windows 95/
98

The OTP programmer can be supplied three types of pro-
grammer such as emulator add-on board type single pro-
grammer (Dr.Writer

), univeral stand-alone type single

programmer (CHOICE-SIGMA

) and gang type pro-

grammer (CHOICE-SIGMA

). .

Figure 1-1 In Circuit Emulator CHOICE-Dr.

Figure 1-2 OTP Single Programmer Dr.Writer

Figure 1-3 OTP Gang Programmer CHOICE-GANG4

In Circuit

Emulators

CHOICE-Dr.

Assembler

Hynix Macro Assembler

OTP

Programmer

Single Programmer : Dr. Writer

Universal Programmer : CHOICE-

SIGMA

Gang Programmer : CHOICE-GANG4

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

3. PIN ASSIGNMENT

RA3 / AN3

RA2 / AN2

RA1 / AN1

RA0 / EC0

RC1

RC0

RESET

OUT

AN4 / RA4

AN5 / RA5

AN6 / RA6

AN7 / RA7

RD0

RD1

24 SKDIP

RD3

RD2

RA3 / AN3

RA2 / AN2

RA1 / AN1

RA0 / EC0

RC1

RC0

RESET

OUT

AN4 / RA4

AN5 / RA5

AN6 / RA6

AN7 / RA7

AN0 / AV

REF

/ RB0

BUZ / RB1

INT0 / RB2

INT1 / RB3

PWM0 / COMP0 / RB4

24 SOP

RD3

RD2

AN0 / AV

REF

/ RB0

BUZ / RB1

INT0 / RB2

INT1 / RB3

PWM0 / COMP0 / RB4

RD1

RD0

RA3 / AN3

RA2 / AN2

RA1 / AN1

RA0 / EC0

RC1

RC0

RESET

OUT

AN4 / RA4

AN5 / RA5

AN6 / RA6

AN7 / RA7

20 PDIP

RA3 / AN3

RA2 / AN2

RA1 / AN1

RA0 / EC0

RC1

RC0

RESET

OUT

AN4 / RA4

AN5 / RA5

AN6 / RA6

AN7 / RA7

AN0 / AV

REF

/ RB0

BUZ / RB1

INT0 / RB2

INT1 / RB3

PWM0 / COMP0 / RB4

20 SOP

AN0 / AV

REF

/ RB0

BUZ / RB1

INT0 / RB2

INT1 / RB3

PWM0 / COMP0 / RB4

RA3 / AN3

RA2 / AN2

RA1 / AN1

RA0 / EC0

RESET

OUT

AN4 / RA4

AN5 / RA5

AN6 / RA6

AN7 / RA7

16 PDIP

RA3 / AN3

RA2 / AN2

RA1 / AN1

RA0 / EC0

RESET

OUT

AN4 / RA4

AN5 / RA5

AN6 / RA6

AN7 / RA7

AN0 / AV

REF

/ RB0

INT0 / RB2

PWM0 / COMP0 / RB4

16 SOP

AN0 / AV

REF

/ RB0

INT0 / RB2

PWM0 / COMP0 / RB4

HMS87C1304(2)A SK

HMS87C1304(2)A D

HMS87C1204(2)A

HMS87C1204(2)A D

HMS87C1104(2)A

HMS87C1104(2)A D

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

5. PIN FUNCTION

: Supply voltage.

: Circuit ground.

RESET: Reset the MCU.

: Input to the inverting oscillator amplifier and input to

the internal main clock operating circuit.

OUT

: Output from the inverting oscillator amplifier.

RA0~RA7: RA is an 8-bit, CMOS, bidirectional I/O port.
RA pins can be used as outputs or inputs according to "1"
or "0" written the their Port Direction Register(RAIO).

In addition, RA serves the functions of the various special
features in Table 5-1.

RB0~RB4: RB is an 8-bit, CMOS, bidirectional I/O port.
RB pins can be used as outputs or inputs according to "1"
or "0" written the their Port Direction Register(RBIO).

RB serves the functions of the various following special
features

Table 5-2.

RC0, RC1: RC is a 2-bit, CMOS, bidirectional I/O port.
RC pins can be used as outputs or inputs according to "1"
or "0" written the their Port Direction Register(RCIO).

And these pins are not available in HMS87C1104(2)A.

RD0~RD3: RD is a 4-bit, CMOS, bidirectional I/O port.
RC pins can be used as outputs or inputs according to "1"
or "0" written the their Port Direction Register(RDIO).

And these pins are not available in HMS87C1204(2)A and
HMS87C1104(2)A.

Port pin

Alternate function

RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7

EC0 ( Event Counter Input Source )
AN1 ( Analog Input Port 1 )
AN2 ( Analog Input Port 2 )
AN3 ( Analog Input Port 3 )
AN4 ( Analog Input Port 4 )
AN5 ( Analog Input Port 5 )
AN6 ( Analog Input Port 6 )
AN7 ( Analog Input Port 7 )

Table 5-1 RA Port

Port pin

Alternate function

RB0

RB1

RB2
RB3

RB4

1. These pins are not available in HMS87C1104(2)A.

AN0 ( Analog Input Port 0 )
AV

REF

( External Analog Reference Pin

)
BUZ ( Buzzer Driving Output Port )
INT0 ( External Interrupt Input Port 0 )
INT1 ( External Interrupt Input Port 1 )
PWM0 (PWM0 Output)
COMP0 (Timer1 Compare Output)

Table 5-2 RB Port

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

PIN NAME

PIN NUMBER

In/Out

Function

87C1304(2)A

87C1204(2)A

87C1104(2)A

Basic

Sencondary

Supply voltage

Circuit ground

RESET

Reset signal input

OUT

RA0 (EC0)

I/O (Input)

8-bit general

I/O ports

External Event Counter input 0

RA1 (AN1)

I/O (Input)

Analog Input Port 1

RA2 (AN2)

I/O (Input)

Analog Input Port 2

RA3 (AN3)

I/O (Input)

Analog Input Port 3

RA4 (AN4)

I/O (Input)

Analog Input Port 4

RA5 (AN5)

I/O (Input)

Analog Input Port 5

RA6 (AN6)

I/O (Input)

Analog Input Port 6

RA7 (AN7)

I/O (Input)

Analog Input Port 7

RB0 (AVref/AN0)

I/O (Input)

5-bit general

I/O ports

Analog Input Port 0
/ Analog Reference

RB1 (BUZ)

I/O (Input)

Buzzer Driving Output

RB2 (INT0)

I/O (Input)

External Interrupt Input 0

RB3 (INT1)

I/O (Output)

External Interrupt Input 1

RB4 (PWM0/
COMP0)

I/O (Output/

Output)

PWM0 Output or Timer1
Compare Output

RC0

I/O

2-bit general

I/O ports

RC1

I/O

RD0 6

I/O

4-bit general

I/O ports

RD1

I/O

RD2

I/O

RD3

I/O

Table 5-3 Pin Description

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage ........................................... -0.3 to +6.0 V

Storage Temperature ................................-40 to +125

�

Voltage on any pin with respect to Ground (V

)

............................................................... -0.3 to V

+0.3

Maximum current out of V

pin ........................200 mA

Maximum current into V

pin ..........................150 mA

Maximum current sunk by (I

per I/O Pin) ........25 mA

Maximum output current sourced by (I

per I/O Pin)

...............................................................................15 mA

Maximum current (

) ....................................150 mA

Maximum current (

).................................... 100 mA

Note: Stresses above those listed under "Absolute Maxi-

mum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional op-
eration of the device at any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect device reliability.

7.2 Recommended Operating Conditions

7.3 A/D Converter Characteristics

=25

�

C, V

=0V, V

=5.12V @

XIN

=8MHz, V

=3.072V @

XIN

=4MHz)

Parameter

Symbol

Condition

Specifications

Unit

Min.

Max.

Supply Voltage

XIN

=8MHz

4.5

5.5

XIN

=4.2MHz

2.0

5.5

Operating Frequency

XIN

=4.5~5.5V

MHz

=2.0~5.5V

4.2

MHz

Operating Temperature

OPR

-20

�

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

Analog Input Voltage Range

AIN

AVREFS=0

AVREFS=1

REF

Analog Power Supply Input Voltage Range

REF

=5V

=3V

2.4

Overall Accuracy

ACC

�

1.0

�

1.5

LSB

Non-Linearity Error

NLE

�

1.0

�

1.5

LSB

Differential Non-Linearity Error

DNLE

�

1.0

�

1.5

LSB

Zero Offset Error

ZOE

�

0.5

�

1.5

LSB

Full Scale Error

FSE

�

0.25

�

0.5

LSB

Gain Error

NLE

�

1.0

�

1.5

LSB

Conversion Time

CONV

XIN

=8MHz

�

XIN

=4MHz

REF

Input Current

REF

AVREFS=1

0.5

1.0

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

7.4 DC Electrical Characteristics

=-20~85

�

C, V

=2.0~5.5V

=0V)

Parameter

Symbol

Pin

Condition

Specifications

Unit

Min.

Typ.

Max.

Input High Voltage

IH1

RESET

0.8 V

IH2

, Hysteresis Input

0.8 V

IH3

Normal Input

0.7 V

Input Low Voltage

IL1

RESET

0.2 V

IL2

, Hysteresis Input

0.2 V

IL3

Normal Input

0.3 V

Output High Voltage

All Output Port

=5V, I

=-5mA

-1

Output Low Voltage

All Output Port

=5V, I

=10mA

Input Pull-up Current

RB2, RB3, RD0, RD1

=5V

-450

-380

-300

�

Input High
Leakage Current

IH1

All Pins (except X

)

=5V

�

IH2

=5V

�

Input Low
Leakage Current

IL1

All Pins (except X

)

=5V

-5

�

IL2

=5V

-15

�

Hysteresis

| V

Hysteresis Input

=5V

0.5

PFD Voltage

PFD1

PFD Level = 0, V

=5V

2.0

2.5

3.0

PFD2

PFD Level = 1, V

=3V

1.5

1.7

1.9

Internal RC WDT
Period

RCWDT

=5.0V, f

XIN

=8MHz

200

�

=3.0V, f

XIN

=4MHz

150

300

Operating Current

=5.5V, f

XIN

=8MHz

=3.0V, f

XIN

=4MHz

Wake-up Timer Mode
Current

WKUP

=5.5V, f

XIN

=8MHz

0.1

0.5

=3.0V, f

XIN

=4MHz

0.03

0.1

RCWDT Mode
Current at STOP
Mode

RCWDT

=5.5V

�

=3.0V

Stop Mode Current

STOP

=5.5V, f

XIN

=8MHz

0.7

1.6

�

=3.0V, f

XIN

=4MHz

0.2

0.8

External RC
Oscillator Frequency

OUT

=5V,

R=10K

, C=20pF

MHz

=5V,

R=10K

1. Hysteresis Input: RA0, RB2, RB3

2. This parameter is valid when the bit PUPSELx is selected and set the input mode or interrupt input function.
3. This value is measured under NOP instruction execution.

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

7.6 Typical Characteristics

This graphs and tables provided in this section are for de-
sign guidance only and are not tested or guaranteed.

In some graphs or tables the data presented are out-
side specified operating range (e.g. outside specified
V

range). This is for information only and devices

are guaranteed to operate properly only within the
specified range.

The data presented in this section is a statistical summary
of data collected on units from different lots over a period
of time. "Typical" represents the mean of the distribution
while "max" or "min" represents (mean + 3

) and (mean

) respectively where

is standard deviation

Ta= 25

�

Ta=25

�

(mA)

(V)

Normal Operation (NOP)

(MHz)

XIN

(V)

Operating Area

XIN

= 8MHz

4MHz

WKUP

2.0

1.5

1.0

0.5

(mA)

(V)

Wake-up Timer Mode

RCWDT

(

�

(V)

RC-WDT in Stop Mode

Ta=25

�

XIN

= 8MHz

4MHz

Ta=25

�

STOP

2.0

1.5

1.0

0.5

(

�

(V)

STOP Mode

XIN

= 8MHz

-25

�

RCWDT

= 180uS

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

, V

=5V

(mA)

(V)

, V

=5V

-20

-15

-10

-5

(mA)

(V)

0.5

1.5

2.5

XIN

=4MHz

IH1

(V)

IH1

(V)

IH2

(V)

IH2

(V)

Ta=25

�

X IN

= 4M H z

Ta=25

�

, RESET

Hysteresis input

-25

�

-25

�

IH3

(V)

IH3

(V)

X IN

=4M H z

Ta=25

�

Normal input

XIN

=4MHz

IL1

(V)

IL1

(V)

IL2

(V)

IL2

(V)

Ta=25

�

X IN

=4M H z

Ta=25

�

, RESET

Hysteresis input

IL3

(V)

IL3

(V)

X IN

=4M H z

Ta=25

�

Normal input

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

8. MEMORY ORGANIZATION

The HMS87C1X0XA has separate address spaces for Pro-
gram memory and Data Memory. Program memory can
only be read, not written to. It can be up to 2K/4K bytes of

Program memory. Data memory can be read and written to
up to 128 bytes including the stack area.

8.1 Registers

This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.

Figure 8-1 Configuration of Registers

Accumulator: The Accumulator is an 8-bit general pur-
pose register, used for data operation such as transfer, tem-
porary saving, and conditional judgement, etc.

The Accumulator can be used as a 16-bit register with Y
Register as shown below.

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the spec-
ified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have in-
crement, decrement, comparison and data transfer func-
tions, and they can be used as simple accumulators.

Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).

Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.

The stack can be located at any position within 00

to 7F

of the internal data memory. The SP is not initialized by
hardware, requiring to write the initial value (the location
with which the use of the stack starts) by using the initial-
ization routine. Normally, the initial value of "7F

" is

used.

Note: The Stack Pointer must be initialized by software be-

cause its value is undefined after RESET.
Example: To initialize the SP
LDX

#07FH

TXSP

; SP

Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset rou-
tine address (PC

:0FF

, PC

:0FE

Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3. It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.

[Zero flag Z]

This flag is set when the result of an arithmetic operation
or data transfer is "0" and is cleared by any other result.

ACCUMULATOR

X REGISTER

Y REGISTER

STACK POINTER

PROGRAM COUNTER

PROGRAM STATUS
WORD

PCL

PCH

PSW

Two 8-bit Registers can be used as a "YA" 16-bit Register

Stack Address (000

~ 07F

)

Hardware fixed

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

Figure 8-3 PSW (Program Status Word) Register

[Interrupt disable flag I]

This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to "0". This flag immedi-
ately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.

[Half carry flag H]

After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-

dress.

[Overflow flag V]

This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
ceeds +127(7F

) or -128(80

). The CLRV instruction

clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.

NEGATIVE FLAG

MSB

LSB

RESET VALUE: 00

PSW

OVERFLOW FLAG

BRK FLAG

CARRY FLAG RECEIVES

ZERO FLAG

INTERRUPT ENABLE FLAG

CARRY OUT

HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

8.2 Program Memory

A 16-bit program counter is capable of addressing up to
64K bytes, but these devices have 4K/2K bytes program
memory space only physically implemented. Accessing a
location above FFFF

will cause a wrap-around to 0000

Figure 8-4, shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFE

and FFFF

as shown in Figure 8-5.

As shown in Figure 8-4, each area is assigned a fixed loca-
tion in Program Memory. Program Memory area contains
the user program.

Figure 8-4 Program Memory Map

Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL in-
stead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.

Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0

for TCALL15, 0FFC2

for

TCALL14, etc., as shown in Figure 8-6.

Example: Usage of TCALL

The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to loca-
tion 0FFFA

. The interrupt service locations spaces 2-byte

interval: 0FFF8

and 0FFF9

for External Interrupt 1,

0FFFA

and 0FFFB

for External Interrupt 0, etc.

As for the area from 0FF00

to 0FFFF

, if any area of

them is not going to be used, its service location is avail-
able as general purpose Program Memory.

Figure 8-5 Interrupt Vector Area

PROGRAM

MEMORY

TCALL

AREA

INTERRUPT

VECTOR AREA

F000H

FEFFH
FF00H

FFC0H

FFDFH
FFE0H

FFFFH

PCALL

AREA

F800H

302

04A

LDA

#5
TCALL

0FH

;

1BYTE INSTR UCTIO N

;

INSTEAD O F 3 BYTES

;

NO R M AL C ALL

;
;TABLE CALL ROUTINE
;
FUNC_A:

LDA

LRG0

RET

;
FUNC_B:

LDA

LRG1

RET

;
;TABLE CALL ADD. AREA
;

ORG

0FFC0H

;

TCALL ADDRESS AREA

FUNC_A

FUNC_B

0FFE0

Address

Vector Area Memory

Basic Interval Interrupt Vector Area

A/D Converter Interrupt Vector Area

Timer/Counter 1 Interrupt Vector Area

Timer/Counter 0 Interrupt Vector Area

External Interrupt 0 Vector Area

RESET Vector Area

External Interrupt 1 Vector Area

Watchdog Timer Interrupt Vector Area

"-" means reserved area.

NOTE:

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

Figure 8-6 PCALL and TCALL Memory Area

PCALL

rel

4F35

PCALL 35H

TCALL

TCALL

0FFC0

Address

Program Memory

0FF00

Address

PCALL Area Memory

0FFFF

PCALL Area

(256 Bytes)

* means that the BRK software interrupt is using
same address with TCALL0.

NOTE:

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

TCALL 8

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

0FF35H

0FF00H

0FFFFH

11111111 11010110

01001010

PC:

0FFD6H

0FF00H

0FFFFH

0FFD7H

0F125H

Reverse

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

Example: The usage software example of Vector address and the initialize part.

ORG

0FFE0H

NOT_USED

; (0FFE0)

NOT_USED

; (0FFE2)

NOT_USED

; (0FFE4)

BIT_INT

; (0FFE6) Basic Interval Timer

WDT_INT

; (0FFE8) Watchdog Timer

AD_INT

; (0FFEA) A/D

NOT_USED

; (0FFEC)

NOT_USED

; (0FFEE)

NOT_USED

; (0FFF0)

NOT_USED

; (0FFF2)

TMR1_INT

; (0FFF4) Timer-1

TMR0_INT

; (0FFF6) Timer-0

INT1

; (0FFF8) Int.1

INT0

; (0FFFA) Int.0

NOT_USED

; (0FFFC)

RESET

; (0FFFE) Reset

ORG

0F000H

;********************************************
;

MAIN PROGRAM

;*******************************************
;
RESET:

;Disable All Interrupts

LDX

RAM_CLR: LDA

;RAM Clear(!0000H->!007FH)

STA

{X}+

CMPX

#080H

BNE

RAM_CLR

;

LDX

#07FH

;Stack Pointer Initialize

TXSP

;

CALL

INITIAL

;

LDM

RA, #0

;Normal Port A

LDM

RAIO,#1000_0010B

;Normal Port Direction

LDM

RB, #0

;Normal Port B

LDM

RBIO,#0000_0010B

;Normal Port Direction

:
:
LDM

PFDR,#0

;Enable Power Fail Detector

:
:

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

8.3 Data Memory

Figure 8-7 shows the internal Data Memory space availa-
ble. Data Memory is divided into two groups, a user RAM
(including Stack) and control registers.

Figure 8-7 Data Memory Map

User Memory

The HMS87C1X0XA has 128

�

8 bits for the user memory

(RAM).

Control Registers

The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0

to 0FF

Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.

More detailed informations of each register are explained
in each peripheral section.

Note: Write only registers can not be accessed by bit ma-

nipulation instruction. Do not use read-modify-write
instruction. Use byte manipulation instruction.

Example; To write at CKCTLR

LDM

CKCTLR,#09H ;Divide ratio

�

USER

MEMORY

CONTROL

REGISTERS

0000H

00BFH

00C0H

00FFH

PAGE0

(including STACK)

007FH

0080H

Address

Symbol

R/W

RESET

Value

Addressing

m ode

0C0H
0C1H
0C2H
0C3H
0C4H
0C5H
0C6H
0C7H

0CAH
0CBH
0CCH

RAIO

RBIO

RCIO

RDIO

RAFUNC
RBFUNC

PUPSEL

R/W

W
W
W
W

Undefined

0000_0000

Undefined

0000_0000

Undefined

----_--00

Undefined

----_0000

0000_0000

----_0000

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte
byte
byte
byte

0D0H
0D1H
0D1H
0D1H
0D2H
0D3H
0D3H
0D4H
0D4H
0D4H
0D5H

TM0

TDR0

CDR0

TM1

TDR1

T1PPR

CDR1

T1PDR

PWM0HR

R/W

W
W

R
R

R/W

--00_0000

0000_0000

1111_1111

0000_0000

1111_1111

0000_0000

----_0000

byte, bit

byte
byte
byte

byte, bit

byte
byte
byte
byte

byte, bit

byte

0DEH

BUR

1111_1111

byte

0E2H
0E3H
0E4H
0E5H
0E6H

0EAH
0EBH

0ECH
0ECH
0EDH
0EDH

0EFH

IENH

IENL

IRQH

IRQL
IEDS

ADCM

ADCR

BITR

CKCTLR

WDTR
WDTR

PFDR

R/W
R/W
R/W
R/W
R/W
R/W

R
R

R/W

0000_----

000-_----

0000_----

000-_----

----_0000

--00_0001

Undefined

0000_0000

-001_0111

0000_0000

0111_1111

----_0100

byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit

byte
byte
byte
byte
byte

byte, bit

Table 8-1 Control Registers

1. "byte, bit" means that register can be addressed by not only bit

but byte manipulation instruction.

2. "byte" means that register can be addressed by only byte

manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for
clearing bit.

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

Note: Several names are given at same address. Refer to

below table.

Stack Area

The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.

When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.

The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save.

Addr.

When read

When write

Timer
Mode

Capture

Mode

PWM
Mode

Timer
Mode

PWM
Mode

D1H

CDR0

TDR0

D3H

TDR1

T1PPR

D4H

CDR1

T1PDR

ECH

BITR

CKCTLR

Table 8-2 Various Register Name in Same Address

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C0H

RA Port Data Register

C1H

RAIO

RA Port Direction Register

C2H

RB Port Data Register

C3H

RBIO

RB Port Direction Register

C4H

RC Port Data Register

C5H

RCIO

RC Port Direction Register

C6H

RD Port Data Register

C7H

RDIO

RD Port Direction Register

CAH

RAFUNC

ANSEL7

ANSEL6

ANSEL5

ANSEL4

ANSEL3

ANSEL2

ANSEL1

ANSEL0

CBH

RBFUNC

TMR2OV

EC1I

PWM1O

PWM0O

INT1I

INT0I

BUZO

AVREFS

CCH

PUPSEL

PUPSEL3 PUPSEL2 PUPSEL1 PUPSEL0

D0H

TM0

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

D1H

T0/TDR0/
CDR0

Timer0 Register / Timer0 Data Register / Capture0 Data Register

D2H

TM1

POL

16BIT

PWM0E

CAP1

T1CK1

T1CK0

T1CN

T1ST

D3H

TDR1/
T1PPR

Timer1 Data Register / PWM0 Period Register

D4H

T1/CDR1/
T1PDR

Timer1 Register / Capture1 Data Register / PWM0 Duty Register

D5H

PWM0HR

PWM0 High Register

DEH

BUR

BUCK1

BUCK0

BUR5

BUR4

BUR3

BUR2

BUR1

BUR0

E2H

IENH

INT0E

INT1E

T0E

T1E

E3H

IENL

ADE

WDTE

BITE

E4H

IRQH

INT0IF

INT1IF

T0IF

T1IF

E5H

IRQL

ADIF

WDTIF

BITIF

E6H

IEDS

IED1H

IED1L

IED0H

IED0L

EAH

ADCM

ADEN

ADS2

ADS1

ADS0

ADST

ADSF

EBH

ADCR

ADC Result Data Register

ECH

BITR

Basic Interval Timer Data Register

ECH

CKCTLR

WAKEUP

RCWDT

WDTON

BTCL

BTS2

BTS1

BTS0

EDH

WDTR

WDTCL

7-bit Watchdog Counter Register

EFH

PFDR

PFDOPR

PFDIS

PFDM

PFDS

Table 8-3 Control Registers of HMS87C1X0XA

These registers of shaded area can not be accessed by bit manipulation instruction as "SET1, CLR1", but should be accessed by
register operation instruction as "LDM dp,#imm".

1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.
2.The register PFDR only be implemented on devices, not on In-circuit Emulator.

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

8.4 Addressing Mode

The HMS87C1X0XA uses six addressing modes;

� Register addressing

� Immediate addressing

� Direct page addressing

� Absolute addressing

� Indexed addressing

� Register-indirect addressing

(1) Register Addressing

(2) Immediate Addressing

#imm

In this mode, second byte (operand) is accessed as a data
immediately.

Example:

0435

ADC

#35H

E45535

LDM

35H,#55H

(3) Direct Page Addressing

In this mode, a address is specified within direct page.

Example;

C535

LDA

35H

RAM[35H]

(4) Absolute Addressing

!abs

Absolute addressing sets corresponding memory data to
Data, i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY

Example;

0735F0

ADC

!0F035H

ROM[0F035H]

A+35H+C

MEMORY

0F100

data

55H

data

0035

0F102

0F101

data

0035

0F551

data

0F550

0F100

data

0F035

0F102

0F101

A+data+C

address: 0F035

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

983500

INC

!0035H

RAM[035H]

(5) Indexed Addressing

X indexed direct page (no offset)

{X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15

LDA

{X}

;ACC

RAM[X].

X indexed direct page, auto increment

{X}+

In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.

LDA, STA

Example; X=35

LDA

{X}+

X indexed direct page (8 bit offset)

dp+X

This address value is the second byte (Operand) of com-
mand plus the data of

-register. And it assigns the mem-

ory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; X=015

C645

LDA

45H+X

0F100

data

0035

0F102

0F101

data+1

data

address: 0035

data

0F550

data

36H

data

0F551

data

0F550

45H+15H=5AH

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

Y indexed direct page (8 bit offset)

dp+Y

This address value is the second byte (Operand) of com-
mand plus the data of Y-register, which assigns Memory in
Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute

!abs+Y

Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify mem-
ory in whole area.

Example; Y=55

D500FA

LDA

!0FA00H+Y

(6) Indirect Addressing

Direct page indirect

[dp]

Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.

JMP, CALL

Example;

3F35

JMP

[35H]

X indexed indirect

[dp+X]

Processes memory data as Data, assigned by 16-bit pair
m e m o r y w h i c h i s d e t e r m i n e d b y p a i r d a t a
[dp+X+1][dp+X] Operand plus

X-register data in Direct

page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; X=10

1625

ADC

[25H+X]

0F100

data

0FA55

0FA00H+55H=0FA55H

0F102

0F101

jump to address 0F30A

0FA00

0F30A

0F405

0FA00

0F405

data

A + data + C

25 + X(10) = 35

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

9. I/O PORTS

The HMS87C1X0XA has four ports, RA, RB, RC and RD.
These ports pins may be multiplexed with an alternate
function for the peripheral features on the device. In gen-
eral, when a initial reset state, all ports are used as a general
purpose input port.

All pins have data direction registers which can set these
ports as output or input. An "1" in the port direction regis-
ter defines the corresponding port pin as output. Converse-
ly, write "0" to the corresponding bit to specify as an input
pin. For example, to use the even numbered bit of RA as
output ports and the odd numbered bits as input ports, write
"55

" to address C1

(RA direction register) during initial

setting as shown in Figure 9-1.

Reading data register reads the status of the pins whereas
writing to it will write to the port latch.

Figure 9-1 Example of port I/O assignment

9.1 RA and RAIO registers

RA is an 8-bit bidirectional I/O port (address C0

). Each

port can be set individually as input and output through the
RAIO register (address C1

RA1~RA7 ports are multiplexed with Analog Input Port
(AN1~AN7) and RA0 port is multiplexed with Event
Counter Input Port (EC0)

Figure 9-2 Registers of Port RA

The control register RAFUNC (address CA

) controls to

select alternate function. After reset, this value is "0", port
may be used as general I/O ports. To select alternate func-
tion such as Analog Input or External Event Counter Input,
write "1" to the corresponding bit of RAFUNC.Regardless
of the direction register RAIO, RAFUNC is selected to use
as alternate functions, port pin can be used as a correspond-
ing alternate features (RA0/EC0 is controlled by RB-
FUNC)

I: INPUT PORT

WRITE "55H" TO PORT RA DIRECTION REGISTER

RA DATA

RB DATA

RA DIRECTION

RB DIRECTION

C0H

C1H

C2H

C3H

BIT

0 PORT

O: OUTPUT PORT

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

INPUT / OUTPUT DATA

0 : INPUT PORT

1 : OUTPUT PORT

DIRECTION SELECT

RA Data Register

ADDRESS : C0H
RESET VALUE : Undefined

RA Direction Register

RAIO

ADDRESS : C1H
RESET VALUE : 00000000

ANSEL0

RA Function Selection Register

RAFUNC

ADDRESS : CAH
RESET VALUE : 00000000

ANSEL7

ANSEL1

ANSEL2

ANSEL3

ANSEL4

ANSEL5

ANSEL6

0 : RB0
1 : AN0

0 : RA1
1 : AN1

0 : RA2
1 : AN2

0 : RA3
1 : AN3

0 : RA4
1 : AN4

0 : RA5
1 : AN5

0 : RA6
1 : AN6

0 : RA7
1 : AN7

PORT

RAFUNC.7~0

Description

RA7/AN7

RA7 (Normal I/O Port)

AN7 (ADS2~0=111)

RA6/AN6

RA6 (Normal I/O Port)

AN6 (ADS2~0=110)

RA5/AN5

RA5 (Normal I/O Port)

AN5 (ADS2~0=101)

RA4/AN4

RA4 (Normal I/O Port)

AN4 (ADS2~0=100)

RA3/AN3

RA3 (Normal I/O Port)

AN3 (ADS2~0=011)

RA2/AN2

RA2 (Normal I/O Port)

AN2 (ADS2~0=010)

RA1/AN1

RA1 (Normal I/O Port)

AN1 (ADS2~0=001)

RA0/EC0

1. This port is not an Analog Input port, but Event Counter clock

source input port. EC0 is controlled by setting TOCK2~0 = 111.
The bit RAFUNC.0 (ANSEL0) controls the RB0/AN0/AVref port
(Refer to Port RB).

RA0 (Normal I/O Port)

EC0 (T0CK2~0=111)

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

9.2 RB and RBIO registers

RB is a 5-bit bidirectional I/O port (address C2

). Each pin

can be set individually as input and output through the
RBIO register (address C3

). In addition, Port RB is mul-

tiplexed with various special features. The control register
RBFUNC (address CB

) controls to select alternate func-

tion. After reset, this value is "0", port may be used as gen-
eral I/O ports. To select alternate function such as External
interrupt or Timer compare output, write "1" to the corre-

sponding bit of RBFUNC.

Regardless of the direction register RBIO, RBFUNC is se-
lected to use as alternate functions, port pin can be used as
a corresponding alternate features.

And RB2/INT0, RB3/INT1 have a function of pull-up
transistor by setting the PUPSEL0 and PUPSEL1 of
PUPSEL register.

Figure 9-3 Registers of Port RB

RB4

RB3 RB2 RB1 RB0

INPUT / OUTPUT DATA

0 : INPUT PORT

1 : OUTPUT PORT

DIRECTION SELECT

RB Data Register

ADDRESS : C2H
RESET VALUE : Undefined

RB Direction Register

RBIO

ADDRESS : C3H
RESET VALUE : ---00000

AVREFS

RB Function Selection Register

RBFUNC

ADDRESS : CBH
RESET VALUE : ---00000

BUZO

INT0I

INT1I

PWM0O

0 : RB0 when ANSEL0 = 0

1 : AV

REF

0 : RB1
1 : BUZ Output

0 : RB4
1 : PWM0 Output or

0 : RB2
1 : INT0

0 : RB3
1 : INT1

PUPSEL0

Pull-up Selection Register

PUPSEL

ADDRESS : CCH
RESET VALUE : ----0000

PUPSEL1

0 : No Pull-up
1 : With Pull-up

IED0L

Interrupt Edge Selection Register

IEDS

ADDRESS : E6H
RESET VALUE : ----0000

IED0H

IED1L

IED1H

External Interrupt Edge Select

INT0

INT1

00 : Normal I/O port
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)

Compare Output

RB0 / INT0 Pull-up

RB1 / INT1 Pull-up

AN0 when ANSEL0 = 1

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

9.3 RC and RCIO registers

RC is a 2-bit bidirectional I/O port (address C4

). Each

pin can be set individually as input and output through the

RCIO register (address C5

Figure 9-4 Registers of Port RC

PORT

RBFUNC.4~0

Description

RB4/

PWM0/

COMP0

RB4 (Normal I/O Port)

PWM0 Output /
Timer1 Compare Output

RB3/INT1

RB3 (Normal I/O Port)

External Interrupt Input 1

RB2/INT0

RB2 (Normal I/O Port)

External Interrupt Input 0

RB1/BUZ

RB1 (Normal I/O Port)

Buzzer Output

RB0/AN0/

REF

1. When ANSEL0 = "0", this port is defined for normal I/O port

(RB0).

When ANSEL0 = "1" and ADS2~0 = "000", this port can be

used Analog Input Port (AN0).

RB0 (Normal I/O Port)/
AN0 (ANSEL0=1)

2. When this bit set to "1", this port defined for AV

REF

, so it can

not be used Analog Input Port AN0 and Normal I/O Port
RB0.

External Analog Reference
Voltage

RC1

RC0

INPUT / OUTPUT DATA

0 : INPUT PORT

1 : OUTPUT PORT

DIRECTION SELECT

RC Data Register

ADDRESS : C4H
RESET VALUE : Undefined

RC Direction Register

RCIO

ADDRESS : C5H
RESET VALUE : ------00

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

9.4 RD and RDIO registers

RD is a 4-bit bidirectional I/O port (address C6

). Each

pin can be set individually as input and output through the
RDIO register (address C7

)

And RD0, RD1 have a function of pull-up transistor by set-
ting the PUPSEL2 and PUPSEL3 of PUPSEL register.

Figure 9-5 Registers of Port RD

RD2 RD1 RD0

INPUT / OUTPUT DATA

0 : INPUT PORT

1 : OUTPUT PORT

DIRECTION SELECT

RD Data Register

ADDRESS : C6H
RESET VALUE : Undefined

RD Direction Register

RDIO

ADDRESS : C7H
RESET VALUE : -----0000

RD3

Pull-up Selection Register

PUPSEL

ADDRESS : CCH
RESET VALUE : ----0000

0 : No Pull-up
1 : With Pull-up

RD0 Pull-up

RD1 Pull-up

PUPSEL2

PUPSEL3

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

10. CLOCK GENERATOR

The clock generator produces the basic clock pulses which
provide the system clock to be supplied to the CPU and pe-
ripheral hardware.

The main system clock oscillator oscillates

with a crystal resonator or a ceramic resonator

connected to the

Xin and Xout pins. External clocks can be input to the main
system clock oscillator. In this case, input a clock signal to
the Xin pin and open the Xout pin.

Figure 10-1 Block Diagram of Clock Pulse Generator

10.1 Oscillation Circuit

and X

OUT

are the input and output, respectively, a in-

verting amplifier which can be set for use as an on-chip os-
cillator, as shown in Figure 10-2.

Figure 10-2 Oscillator Connections

To drive the device from an external clock source, Xout
should be left unconnected while Xin is driven as shown in
Figure 10-3. There are no requirements on the duty cycle
of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum high and low times specified on
the data sheet must be observed.

Oscillation circuit is designed to be used either with a ce-
ramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate

values of external components.

Figure 10-3 External Clock Connections

Note: When using a system clock oscillator, carry out wir-

ing in the broken line area in Figure 10-2 to prevent
any effects from wiring capacities.
- Minimize the wiring length.
- Do not allow wiring to intersect with other signal
conductors.
- Do not allow wiring to come near changing high
current.
- Set the potential of the grounding position of the
oscillator capacitor to that of V

. Do not ground to

any ground pattern where high current is present.
- Do not fetch signals from the oscillator.

In addition, the HMS87C1X0XA has an ability for the ex-
ternal RC oscillated operation. It offers additional cost sav-
ings for timing insensitive applications. The RC

Internal system clock

PRESCALER

CLOCK PULSE

�

Peripheral clock

�

128

�

256

�

512

�

1024

�

GENERATOR

�

2048

STOP

WAKEUP

XIN

OSCILLATION

CIRCUIT

OUT

Vss

Recommended: C1, C2 = 30pF

�

10pF for Crystals

R1 = 1M

OUT

Vss

OPEN

External
Clock
Source

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

oscillator frequency is a function of the supply voltage, the
external resistor (R

EXT

) and capacitor (C

EXT

) values, and

the operating temperature.

The user needs to take into account variation due to toler-
ance of external R and C components used.

Figure 10-4 shows how the RC combination is connected
to the HMS87C1X0XA.

Figure 10-4 RC Oscillator Connections

External capacitor (C

EXT

) can be omitted for more cost

saving. However, the characteristics of external R only os-
cillation are more variable than external RC oscillation.

Figure 10-5 R Oscillator Connections

The oscillator frequency, divided by 4, is output from the
Xout pin, and can be used for test purpose or to synchroze
other logic.

To set the RC oscillation, it should be programmed
RCOPT bit to "1" to CONFIG (707F

). ( Refer to Section

"20.1". )

OUT

Vdd

EXT

XIN

�

EXT

Cint

6pF

OUT

XIN

�

EXT

INT

6pF

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

11. BASIC INTERVAL TIMER

The HMS87C1X0XA has one 8-bit Basic Interval Timer
that is free-run, can not stop. Block diagram is shown in
Figure 11-1.The 8-bit Basic interval timer register (BITR)
is increased every internal count pulse which is divided by
prescaler. Since prescaler has divided ratio by 8 to 1024,
the count rate is 1/8 to 1/1024 of the oscillator frequency.
As the count overflows from FF

to 00

, this overflow

causes to generate the Basic interval timer interrupt. The
BITF is interrupt request flag of Basic interval timer.

When write "1" to bit BTCL of CKCTLR, BITR register is
cleared to "0" and restart to count-up. The bit BTCL be-
comes "0" after one machine cycle by hardware.

If the STOP instruction executed after writing "1" to bit
WAKEUP of CKCTLR, it goes into the wake-up timer
mode. In this mode, all of the block is halted except the os-
cillator, prescaler (only fxin

�

2048) and Timer0.

If the STOP instruction executed after writing "1" to bit
RCWDT of CKCTLR, it goes into the internal RC oscillat-
ed watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON de-
cides Watchdog Timer or the normal 7-bit timer

Note: All control bits of Basic interval timer are in CKCTLR

). Address EC

is read as BITR, writ-

ten to CKCTLR. Therefore, the CKCTLR can not be
accessed by bit manipulation instruction.

Figure 11-1 Block Diagram of Basic Interval Timer

Figure 11-2 CKCTLR: Clock Control Register

�

128

�

256

�

512

�

1024

�

MUX

XIN

BITR (8BIT)

BITIF

BTS[2:0]

Internal RC OSC

Basic Interval Timer
Interrupt

BTCL

Clear

To Watchdog Timer

STOP

WAKEUP

RCWDT

Clock Control Register

CKCTLR

ADDRESS : ECH
RESET VALUE : -0010111

WAKEUP

RCWDT

WDTON

BTCL

BTS2

BTS1

BTS0

Basic Interval Timer Clock Selection

000 : f

XIN

�

001 : f

XIN

�

100 : f

XIN

�

128

101 : f

XIN

�

256

110 : f

XIN

�

512

111 : f

XIN

�

1024

010 : f

XIN

�

011 : f

XIN

�

Symbol

Function Description

WAKEUP

1 : Enables Wake-up Timer
0 : Disables Wake-up Timer

RCWDT

1 : Enables Internal RC Watchdog Timer
0 : Disables Internal RC Watchdog Time

WDTON

1 : Enables Watchdog Timer
0 : Operates as a 7-bit Timer

BTCL

1 : BITR is cleared and BTCL becomes "0" automatically
after one machine cycle, and BITR continue to count-up

Bit Manipulation Not Available

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

12. TIMER / COUNTER

The HMS87C1X0XA has two Timer/Counter registers.
Each module can generate an interrupt to indicate that an
event has occurred (i.e. timer match).

Timer 0 and Timer 1 can be used either two 8-bit Timer/
Counter or the one 16-bit Timer/Counter by combining
them.

In the "timer" function, the register is increased every in-
ternal clock input. Thus, one can think of it as counting in-
ternal clock input. Since a least clock consists of 2 and
most clock consists of 2048 oscillator periods, the count
rate is 1/2 to 1/2048 of the oscillator frequency in Timer0.
And Timer1 can use the same clock source too. In addition,
Timer1 has more fast clock source (1/1 to 1/8).

In the "counter" function, the register is increased in re-
sponse to a 0-to-1 (rising edge) transition at its correspond-
ing external input pin, EC0(Timer 0).

Note:

If changing the Timer value or starting again, it

should be stop the timer clock firstly, and then
set Timer register value.

Ex)

LDM TM0,#00001100B

LDM TDR,#7FH

LDM TM0,#00010111B

In addition the "capture" function, the register is increased
in response external interrupt same with timer function.
When external interrupt edge input, the count register is
captured into capture data register CDRx.

Timer1 is shared with "PWM" function and "Compare
output" function

It has seven operating modes: "8-bit timer/counter", "16-
bit timer/counter", "8-bit capture", "16-bit capture", "8-bit
compare output", "16-bit compare output" and "10-bit
PWM" which are selected by bit in Timer mode register
TMx as shown in Figure 12-1 and Table 12-1.

Figure 12-1 Timer Mode Register (TM0, TM1)

Timer 0 Mode Register

TM0

ADDRESS : D0H
RESET VALUE : --000000

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

Timer 1 Mode Register

TM1

ADDRESS : D2H
RESET VALUE : 00000000

POL

16BIT

PWM0E

CAP1

T1CK1

T1CK0

T1CN

T1ST

CAP0

Capture mode selection bit.
0 : Disables Capture
1 : Enables Capture

T0CN

Continue control bit
0 : Stop counting
1 : Start counting continuously

T0CK[2:0]

Input clock selection

000 : f

XIN

�

2, 100 : f

XIN

�

128

001 : f

XIN

�

4, 101 : f

XIN

�

512

010 : f

XIN

�

8, 110 : f

XIN

�

2048

011 : f

XIN

�

32, 111 : External Event ( EC0 )

T0ST

Start control bit
0 : Stop counting
1 : Start counting

POL

PWM Output Polarity
0 : Duty active low
1 : Duty active high

T1CK[2:0]

Input clock selection

00 : f

XIN

10 : f

XIN

�

01 : f

XIN

�

2 11 : using the Timer 0 clock

16BIT

16-bit mode selection
0 : 8-bit mode
1 : 16-bit mode

T1CN

Continue control bit
0 : Stop counting
1 : Start counting continuously

PWM0E

PWM enable bit
0 : Disables PWM
1 : Enables PWM

T1ST

Start control bit
0 : Stop counting
1 : Start counting

CAP1

Capture mode selection bit.
0 : Disables Capture
1 : Enables Capture

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

12.1 8-bit Timer/Counter Mode

The HMS87C1X0XA has four 8-bit Timer/Counters, Tim-
er 0 and Timer 1 as shown in Figure 12-2.

The "timer" or "counter" function is selected by mode reg-
isters TMx as shown in Figure 12-1 and Table 12-1. To use

as an 8-bit timer/counter mode, bit CAP0 of TM0 is
cleared to "0" and bits 16BIT of TM1 should be cleared to
"0"(Table 12-1).

Figure 12-2 8-bit Timer / Counter Mode

16BIT

CAP0

CAP1

PWME

T0CK[2:0]

T1CK[1:0]

PWMO

TIMER 0

TIMER1

XXX

8-bit Timer

111

8-bit Event Counter

8-bit Capture

XXX

8-bit Capture

8-bit Compare output

XXX

8-bit Timer/Counter

10-bit PWM

XXX

16-bit Timer

111

16-bit Event Counter

XXX

16-bit Capture

XXX

16-bit Compare output

Table 12-1 Operating Modes of Timer 0 and Timer 1

1. X: The value "0" or "1" corresponding your operation.

�

TM0

ADDRESS : D0H
RESET VALUE : --000000

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

TM1

ADDRESS : D2H
RESET VALUE : 00000000

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

�

128

�

512

�

XIN

EC0

Edge Detector

MUX

T0 (8-bit)

TDR0 (8-bit)

T0IF

CLEAR

COMPARATOR

TIMER 0
INTERRUPT

T1 (8-bit)

TDR1 (8-bit)

T1IF

CLEAR

COMPARATOR

TIMER 1
INTERRUPT

T0ST

0 : Stop
1 : Start

T1ST

0 : Stop
1 : Start

T0CN

T1CN

T0CK[2:0]

T1CK[1:0]

F/F

COMP0 PIN

�

2048

X: The value "0" or "1" corresponding your operation.

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

These timers have each 8-bit count register and data regis-
ter. The count register is increased by every internal or ex-
ternal clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by con-
trol bits T0CK2, T0CK1 and T0CK0 of register TM0) and
1, 2, 8 (selected by control bits T1CK1 and T1CK0 of reg-
ister TM1). In the Timer 0, timer register T0 increases
from 00

until it matches TDR0 and then reset to 00

. The

match output of Timer 0 generates Timer 0 interrupt

(latched in T0F bit). As TDRx and Tx register are in same
address, when reading it as a Tx, written to TDRx.

In counter function, the counter is increased every 0-to 1
(rising edge) transition of EC0 pin. In order to use counter
function, the bit RA0 of the RA Direction Register RAIO
is set to "0". The Timer 0 can be used as a counter by pin
EC0 input, but Timer 1 can not.

Figure 12-3 Counting Example of Timer Data Registers

Figure 12-4 Timer Count Operation

Timer 1 (T1IF)
Interrupt

TDR1

TIME

Occur interrupt

Interrupt period

up-

count

n-1

= P

x (n+1)

Timer 1 (T1IF)
Interrupt

TDR1

TIME

Occur interrupt

stop

clear & start

disable

enable

Start & Stop

T1ST

T1CN
Control count

up-

unt

T1ST = 0

T1ST = 1

T1CN = 0

T1CN = 1

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

12.2 16-bit Timer/Counter Mode

The Timer register is being run with 16 bits. A 16-bit timer/
counter register T0, T1 are increased from 0000

until it

matches TDR0, TDR1 and then resets to 0000

. The

match output generates Timer 0 interrupt not Timer 1 in-
terrupt.

The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0SL0.

In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to "1" respectively.

Figure 12-5 16-bit Timer / Counter Mode

12.3 8-bit Compare Output (16-bit)

The HMS87C1X0XA has a function of Timer Compare
Output. To pulse out, the timer match can goes to port
pin(COMP0) as shown in Figure 12-2 and Figure 12-5.
Thus, pulse out is generated by the timer match. These op-
eration is implemented to pin, RB4/COMP0/PWM.

This pin output the signal having a 50: 50 duty square

wave, and output frequency is same as below equation.

In this mode, the bit PWMO of RB function register (RB-
FUNC) should be set to "1", and the bit PWME of timer1
mode register (TM1) should be set to "0".

In addition, 16-bit Compare output mode is available, also.

12.4 8-bit Capture Mode

The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP1 of timer mode register TM1
for Timer 1) as shown in Figure 12-6.

As mentioned above, not only Timer 0 but Timer 1 can also
be used as a capture mode.

The Timer/Counter register is increased in response inter-
nal or external input. This counting function is same with
normal timer mode, and Timer interrupt is generated when
timer register T0 (T1) increases and matches TDR0
(TDR1).

TM0

ADDRESS : D0H
RESET VALUE : --000000

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

TM1

ADDRESS : D2H
RESET VALUE : 00000000

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

�

128

�

512

�

XIN

EC0

Edge Detector

MUX

T1 (8-bit)

TDR1 (8-bit)

T0IF

CLEAR

COMPARATOR

TIMER 0

INTERRUPT

T0 (8-bit)

TDR0 (8-bit)

T0ST

0 : Stop
1 : Start

T0CN

T0CK[2:0]

F/F

COMP0 PIN

�

2048

X: The value "0" or "1" corresponding your operation.

C OMP

Oscillation Frequency

Prescaler Value

TDR

)

(

�

--------------------------------------------------------------------------------

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.

For example, in Figure 12-8, the pulse width of captured
signal is wider than the timer data value (FF

) over 2

times. When external interrupt is occurred, the captured
value (13

) is more little than wanted value. It can be ob-

tained correct value by counting the number of timer over-
flow occurrence.

Timer/Counter still does the above, but with the added fea-
ture that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be cap-
tured into registers CDRx (CDR0, CDR1), respectively.

After captured, Timer x register is cleared and restarts by
hardware.

It has three transition modes: "falling edge", "rising edge",
"both edge" which are selected by interrupt edge selection
register IEDS (Refer to External interrupt section). In ad-
dition, the transition at INTx pin generate an interrupt.

Note: The CDRx, TDRx and Tx are in same address. In

the capture mode, reading operation is read the
CDRx, not Tx because path is opened to the CDRx,
and TDRx is only for writing operation.

Figure 12-6 8-bit Capture Mode

�

TM0

ADDRESS : D0H
RESET VALUE : --000000

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

TM1

ADDRESS : D2H
RESET VALUE : 00000000

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

�

128

�

512

�

XIN

EC0

Edge Detector

MUX

T0 (8-bit)

CDR0 (8-bit)

T0IF

CLEAR

COMPARATOR

TIMER 0
INTERRUPT

T0ST

0 : Stop
1 : Start

T0CN

T1CN

T0CK[2:0]

T1CK[1:0]

TDR0 (8-bit)

INT0IF

INT 0
INTERRUPT

INT0

T1 (8-bit)

CDR1 (8-bit)

T1IF

CLEAR

COMPARATOR

TIMER 1
INTERRUPT

TDR1 (8-bit)

INT1IF

INT 1
INTERRUPT

INT1

T0ST

0 : Stop
1 : Start

IEDS[1:0]

IEDS[3:2]

CAPTURE

�

2048

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

12.5 16-bit Capture Mode

16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits.

The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.

In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to "1" respectively.

Figure 12-9 16-bit Capture Mode

12.6 PWM Mode

The HMS87C1X0XA has a high speed PWM (Pulse
Width Modulation) functions which shared with Timer1.

In PWM mode, pin RB4/COMP0/PWM0 outputs up to a
10-bit resolution PWM output. This pin should be config-
ure as a PWM output by setting "1" bit PWM0O in RB-
FUNC register.

The period of the PWM output is determined by the
T1PPR (PWM0 Period Register) and PWM0HR[3:2]
(bit3,2 of PWM0 High Register) and the duty of the PWM
output is determined by the T1PDR (PWM0 Duty Regis-
ter) and PWM0HR[1:0] (bit1,0 of PWM0 High Register).

The user writes the lower 8-bit period value to the T1PPR
and the higher 2-bit period value to the PWM0HR[3:2].

A n d w r i t e s d u t y v a l u e t o t h e T 1 P D R a n d t h e
PWM0HR[1:0] same way.

The T1PDR is configure as a double buffering for glitch-
less PWM output. In Figure 12-10, the duty data is trans-
ferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle)

PWM Period = [PWM0HR[3:2]T1PPR] X Source Clock

PWM Duty = [PWM0HR[1:0]T1PDR] X Source Clock

The relation of frequency and resolution is in inverse pro-
portion. Table 12-2 shows the relation of PWM frequency
vs. resolution.

TM0

ADDRESS : D0H
RESET VALUE : --000000

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

TM1

ADDRESS : D2H
RESET VALUE : 00000000

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

�

128

�

512

�

XIN

EC0

Edge Detector

MUX

T0 + T1 (16-bit)

TDR1

T0IF

CLEAR

COMPARATOR

TIMER 0

INTERRUPT

T0ST

0 : Stop
1 : Start

T0CN

T0CK[2:0]

TDR0

INT0IF

INT 0
INTERRUPT

INT0

IEDS[1:0]

CAPTURE

CDR1

CDR0

(8-bit)

�

2048

X: The value "0" or "1" corresponding your operation.

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

If it needed more higher frequency of PWM, it should be
reduced resolution.

The bit POL of TM1 decides the polarity of duty cycle.

If the duty value is set same to the period value, the PWM
output is determined by the bit POL (1: High, 0: Low). And
if the duty value is set to "00

", the PWM output is deter-

mined by the bit POL (1: Low, 0: High).

It can be changed duty value when the PWM output. How-
ever the changed duty value is output after the current pe-
riod is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 12-12. As it were, the absolute duty time is not
changed in varying frequency. But the changed period val-
ue must greater than the duty value.

Note:

If changing the Timer1 to PWM function, it

should be stop the timer clock firstly, and then
set period and duty register value. If user
writes register values while timer is in opera-
tion, these register could be set with certain
values.

Ex)

LDM TM1,#00H
LDM T1PPR,#00H
LDM T1PDR,#00H
LDM PWM0HR,#00H
LDM RBFUNC,#0001_1100B
LDM TM1,#1010_1011B

Figure 12-10 PWM Mode

Resolution

Frequency

T1CK[1:0] =

00(125nS)

T1CK[1:0] =

01(250nS)

T1CK[1:0] =

10(1uS)

10-bit

7.8KHz

3.9KHz

0.98KHZ

9-bit

15.6KHz

7.8KHz

1.95KHz

8-bit

31.2KHz

15.6KHz

3.90KHz

7-bit

62.5KHz

31.2KHz

7.81KHz

Table 12-2 PWM Frequency vs. Resolution at 8MHz

�

PWM0HR

ADDRESS : D5H
RESET VALUE : ----0000

PW M 0HR3 PW M0HR2 PW M0HR1 PW M0HR0

MUX

T1CN

T1CK[1:0]

T1 (8-bit)

T1ST

0 : Stop
1 : Clear and Start

CLEAR

COMPARATOR

T1PDR(8-bit)

PWM0HR[1:0]

T1PPR(8-bit)

PWM0HR[3:2]

T1PDR(8-bit)

POL

PWM0O

RB4/

PWM0

T0 clock source

XIN

TM1

ADDRESS : D2H
RESET VALUE : 00000000

P O L

16BIT

PW ME

C A P1

T1C K1

T1C K0

T 1C N

T 1S T

[RBFUNC.4]

Period High

Duty High

Slave

Master

Bit Manipulation Not Available

X: The value "0" or "1" corresponding your operation.

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

Figure 12-11 Example of PWM at 8MHz

Figure 12-12 Example of Changing the Period in Absolute Duty Cycle (@8MHz)

XIN

PWM

3FF

POL=1

PWM
POL=0

Duty Cycle [80H x 125nS = 16uS]

Period Cycle [3FFH x 125nS = 127.875uS, 7.8KHz]

PWM0HR = 0CH

T1PPR = FFH

T1PDR = 80H

T1CK[1:0] = 00 (f

XIN

)

PWM0HR3 PWM0HR2

PWM0HR1 PWM0HR0

T1PPR (8-bit)

T1PDR (8-bit)

Period

Duty

FFH

80H

Source

PWM
POL=1

Duty Cycle

Period Cycle [0EH x 1uS = 14uS, 71KHz]

P W M 0 H R = 0 0H

T 1 P P R = 0 E H

T 1 P D R = 0 5H

T 1 C K [1:0 ] = 10 (1 uS )

01 02

0B 0C 0D 0E

01 02

06 07

01 02

03 04

[05H x 1uS = 5uS]

Duty Cycle

[05H x 1uS = 5uS]

Period Cycle [0AH x 1uS = 10uS, 100KHz]

Duty Cycle

[05H x 1uS = 5uS]

Write T1PPR to 0AH

Period changed

clock

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

13. BUZZER OUTPUT FUNCTION

The buzzer driver consists of 6-bit binary counter, the
buzzer register BUR and the clock selector. It generates
square-wave which is very wide range frequency (480
Hz~250 KHz at f

XIN

= 4 MHz) by user programmable

counter.

Pin RB1 is assigned for output port of Buzzer driver by set-
ting the bit BUZO of RBFUNC to "1".

The 6-bit buzzer counter is cleared and start the counting
by writing signal to the register BUR. It is increased from
00H until it matches 6-bit register BUR.

Also, it is cleared by counter overflow and count up to out-
put the square wave pulse of duty 50%.

The bit 0 to 5 of BUR determines output frequency for
buzzer driving. Frequency calculation is following as
shown below.

The bits BUCK1, BUCK0 of BUR selects the source clock
from prescaler output.

Figure 13-1 Buzzer Driver

BUZ

(

)

Oscillator Frequency

Prescaler Ratio

BUR

(

)

�

------------------------------------------------------------------------------

BUR

ADDRESS : DEH
RESET VALUE : 11111111

BUCK1

BUCK0

BUR5

BUR4

BUR3

BUR2

BUR1

BUR0

�

XIN

MUX

COUNTER (6-bit)

BUR (6-bit)

F/F

COMPARATOR

BUCK[1:0]

RB1/BUZ PIN

�

Input clock selection

00 : f

XIN

�

01 : f

XIN

�

10 : f

XIN

�

11 : f

XIN

�

Buzzer Period Data

BUZO

[RBFUNC.1]

Bit Manipulation Not Available

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

14. ANALOG TO DIGITAL CONVERTER

The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has eight analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which gen-
erates the result via successive approximation.

The analog reference voltage is selected to V

or AV

REF

by setting of the bit AVREFS in RBFUNC register. If ex-
ternal analog reference AV

REF

is selected, the bit ANSEL0

should not be set to "1", because this pin is used to an an-
alog reference of A/D converter.

The A/D module has two registers which are the control
register ADCM and A/D result register ADCR. The
ADCM register, shown in Figure 14-2, controls the opera-
tion of the A/D converter module. The port pins can be
configure as analog inputs or digital I/O.

To use analog inputs, each port is assigned analog input
port by setting the bit ANSEL[7:0] in RAFUNC register.
And selected the corresponding channel to be converted by
setting ADS[2:0].

The processing of conversion is start when the start bit
ADST is set to "1". After one cycle, it is cleared by hard-
ware. The register ADCR contains the results of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADCR, the A/D conversion status bit
ADSF is set to "1", and the A/D interrupt flag ADIF is set.
The block diagram of the A/D module is shown in Figure
14-1. The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conver-
sion is in process. The conversion time takes maximum 10
uS (at f

XIN

=8 MHz).

Figure 14-1 A/D Converter Block Diagram

RB0/AN0/AV

REF

ANSEL0 (RAFUNC.0)

RA1/AN1

ANSEL1

RA2/AN2

ANSEL2

RA3/AN3

ANSEL3

RA4/AN4

ANSEL4

RA5/AN5

ANSEL5

RA6/AN6

ANSEL6

RA7/AN7

ANSEL7

000

001

010

011

100

101

110

111

AVREFS (RBFUNC.0)

ADEN

S/H

Successive

Approximation

Circuit

A D IF

Resistor

Ladder

Circuit

ADS[2:0]

ADCR(8-bit)

Sample & Hold

A/D Interrupt

ADDRESS : EBH
RESET VALUE : Undefined

A/D Result Register

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

Figure 14-2 A/D Converter Registers

Figure 14-3 A/D Converter Operation Flow

A/D Converter Cautions

(1) Input range of AN0 to AN7

The input voltage of AN0 to AN7 should be within the
specification range. In particular, if a voltage above

(or AV

REF

)

or below V

is input (even if within the absolute

maximum rating range), the conversion value for that channel can
not be indeterminate. The conversion values of the other channels
may also be affected.

(2) Noise countermeasures

In order to maintain 8-bit resolution, attention must be paid to
noise on pins AV

REF

(or V

) and AN0 to AN7. Since

the effect

increases in proportion to the output impedance of the an-
alog input source, it is recommended that

a capacitor be con-

nected externally as shown in Figure 14-4 in order to reduce
noise.

Figure 14-4 Analog Input Pin Connecting Capacitor

ADCM

ADDRESS : EAH
RESET VALUE : --000001

ADEN

ADS2

ADS1

ADS0

ADST

ADSF

Reserved

Analog Channel Select

A/D Status bit
0 : A/D Conversion is in process
1 : A/D Conversion is completed

A/D Start bit
1 : A/D Conversion is started
After 1 cycle, cleared to "0"
0 : Bit force to zero

000 : Channel 0 (RB0/AN0)
001 : Channel 1 (RA1/AN1)
010 : Channel 2 (RA2/AN2)

011 : Channel 3 (RA3/AN3)
100 : Channel 4 (RA4/AN4)
101 : Channel 5 (RA5/AN5)
110 : Channel 6 (RA6/AN6)
111 : Channel 7 (RA7/AN7)

A/D Enable bit
1 : A/D Conversion is enable

0 : A/D Converter module shut off
and consumes no operation current

A/D Control Register

ADCR

ADDRESS : EBH
RESET VALUE : Undefined

ADCR7

ADCR6

ADCR5

ADCR4

ADCR3

ADCR2

ADCR1

ADCR0

A/D Result Data Register

ENABLE A/D CONVERTER

A/D START (ADST = 1)

NOP

ADSF = 1

A/D INPUT CHANNEL SELECT

ANALOG REFERENCE SELECT

READ ADCR

YES

AN0~AN7

100~1000pF

Analog
Input

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

(3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7

The analog input pins AN0 to AN7 also function as input/
output port (PORT RA and RB0) pins. When A/D conver-
sion is performed with any of pins AN0 to AN7 selected,
be sure not to execute a PORT input instruction while con-
version is in progress, as this may reduce the conversion
resolution.

Also, if digital pulses are applied to a pin adjacent to the
pin in the process of A/D conversion, the expected A/D
conversion value may not be obtainable due to coupling

noise. Therefore, avoid applying pulses to pins adjacent to
the pin undergoing A/D conversion.

(4) AV

REF

pin input impedance

A series resistor string of approximately 10K

is connected be-

tween the AV

REF

pin and the V

pin.

Therefore, if the output impedance of the reference voltage
source is high, this will result in parallel connection

to the

series resistor string between the AV

REF

pin and the V

pin, and

there will be a large reference voltage error.

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

15. INTERRUPTS

The HMS87C1X0XA interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Interrupt Edge Selection Register (IEDS),
priority circuit and Master enable flag("I" flag of PSW).
The configuration of interrupt circuit is shown in Figure
15-1and Interrupt priority is shown in Table 15-1.

The External Interrupts INT0 and INT1 can each be transi-
tion-activated (1-to-0, 0-to-1 and both transition).

The flags that actually generate these interrupts are bit
INT0IF and INT1IF in Register IRQH. When an external
interrupt is generated, the flag that generated it is cleared

by the hardware when the service routine is vectored to
only if the interrupt was transition-activated.

The Timer 0 and Timer 1 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective tim-
er/counter register. The AD converter Interrupt is generat-
ed by ADIF which is set by finishing the analog to digital
conversion. The Watch dog timer Interrupt is generated by
WDTIF which set by a match in Watch dog timer register
(when the bit WDTON is set to "0"). The Basic Interval
Timer Interrupt is generated by BITIF which is set by a
overflowing of the Basic Interval Timer Register(BITR).

Figure 15-1 Block Diagram of Interrupt Function

BIT

BITIF

WDTIF

WDT

A/D Converter

Timer 1

Timer 0

External Int. 1

External Int. 0

IENH

Interrupt Enable

IRQH

IRQL

Interrupt

Vector

Address

Generator

Internal bus line

Release STOP

To CPU

Interrupt Master
Enable Flag

I Flag

IENL

i
o

ty Control

I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.

INT0IF

INT1IF

T0IF

T1IF

ADIF

IEDS

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in IRQH,
IRQL) except Power-on reset and software BRK interrupt.

Interrupt enable registers are shown in Figure 15-2. These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is "0", a corre-
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.

Figure 15-2 Interrupt Enable Registers and Interrupt Request Registers

When an interrupt is occurred, the I-flag is cleared and dis-
able any further interrupt, the return address and PSW are
pushed into the stack and the PC is vectored to. Once in the
interrupt service routine the source(s) of the interrupt can
be determined by polling the interrupt request flag bits.

The interrupt request flag bit(s) must be cleared by soft-
ware before re-enabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read and
written.

Reset/Interrupt

Symbol

Priority

Vector Addr.

Hardware Reset
External Interrupt 0
External Interrupt 1
Timer 0
Timer 1
A/D Converter
Watch Dog Timer
Basic Interval Timer

RESET
INT0
INT1
Timer 0
Timer 1
A/D C
WDT
BIT

1
2
3
4
5
6
7

FFFE

FFFA

FFF8

FFF6

FFF4

FFEA

FFE8

FFE6

Table 15-1 Interrupt Priority

IENH

ADDRESS : E2H
RESET VALUE : 0000----

INT0E

INT1E

T0E

T1E

Interrupt Enable Register High

IENL

ADDRESS : E3H
RESET VALUE : 000-----

ADE

WDTE

BITE

Interrupt Enable Register Low

IRQH

ADDRESS : E4H
RESET VALUE : 0000----

INT0IF

INT1IF

T0IF

T1IF

Interrupt Request Register High

IRQL

ADDRESS : E5H
RESET VALUE : 000-----

ADIF

WDTIF

BITIF

Interrupt Request Register Low

0 : Disable
1 : Enable

Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.

0 : Not occurred
1 : Interrupt request is occurred

Shows the interrupt occurrence

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

15.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an in-
struction. Interrupt acceptance sequence requires 8 f

OSC

�

s at f

XIN

=4MHz) after the completion of the current in-

struction execution. The interrupt service task is terminat-
ed upon execution of an interrupt return instruction
[RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

"0" to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following
interrupts is temporarily disabled.

2. Interrupt request flag for the interrupt source accepted is

cleared to "0".

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is

read from the vector table address and the entry address
is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

Figure 15-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

A interrupt request is not accepted until the I-flag is set to
"1" even if a requested interrupt has higher priority than
that of the current interrupt being serviced.

When nested interrupt service is required, the I-flag should
be set to "1" by "EI" instruction in the interrupt service
program. In this case, acceptable interrupt sources are se-
lectively enabled by the individual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. These registers are saved by the software
if necessary. Also, when multiple interrupt services are
nested, it is necessary to avoid using the same data memory
area for saving registers.

V.L.

System clock

Address Bus

SP-1

SP-2

V.H.

New PC

V.L.

Data Bus

Not used

PCH

PCL

PSW

ADL

OP code

ADH

Instruction Fetch

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.

Basic Interval Timer

012

0F3

0FFE6

0FFE7

0F312

0F313

Entry Address

Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.

Vector Table Address

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

The following method is used to save/restore the general-
purpose registers.

Example: Register save using push and pop instructions

General purpose register save/restore using push and pop
instructions;

BRK Interrupt

Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.

Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin-
guish BRK from TCALL 0.

Each processing step is determined by B-flag as shown in
Figure 15-4.

Figure 15-4 Execution of BRK/TCALL0

Multi Interrupt

If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.

However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.

Figure 15-5 Execution of Multi Interrupt

Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.

TIMER1:

PUSH

LDM

IENH,#80H

;

Enable INT0 only

LDM

IENL,#0

;

Disable other

;

Enable Interrupt

:
:
:
:
:
:
LDM

IENH,#0F0H

;

Enable all interrupts

LDM

IENL,#0E0H

POP

RETI

INTxx:

PUSH

;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.

interrupt processing

POP

RETI

;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN

main task

interrupt
service task

saving
registers

restoring
registers

acceptance of

interrupt

interrupt return

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

TCALL0

ROUTINE

RET

BRK or

TCALL0

enable INT0

TIMER 1
service

INT0
service

Main Program
service

Occur
TIMER1 interrupt

Occur
INT0

disable other

enable INT0
enable other

In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

15.2 External Interrupt

The external interrupt on INT0 and INT1 pins are edge
triggered depending on the edge selection register IEDS
(address 0E6

) as shown in Figure 15-6.

The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.

Figure 15-6 External Interrupt Block Diagram

Example: To use as an INT0 and INT1

:
:

;

**** Set port as an input port RB2

LDM

RBIO,#1111_1011B

;

**** Set port as an interrupt port

LDM

RBFUNC,#04H

;

**** Set Falling-edge Detection

LDM

IEDS,#0000_0001B

Response Time

The INT0 and INT1 edge are latched into INT0IF and
INT1IF at every machine cycle. The values are not actually
polled by the circuitry until the next machine cycle. If a re-
quest is active and conditions are right for it to be acknowl-
edged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The
DIV itself takes twelve cycles. Thus, a minimum of twelve
complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution
of the first instruction of the service routine.

Figure 15-7 shows interrupt response timings.

Figure 15-7 Interrupt Response Timing Diagram

INT0IF

INT0 pin

INT0 INTERRUPT

INT1IF

INT1 pin

INT1 INTERRUPT

IEDS

[0E6

]

dge

l
e

ction

INT0 edge select

Ext. Interrupt Edge Selection

IEDS

ADDRESS : 0E6

RESET VALUE : ----0000

00 : Int. disable

01 : falling
10 : rising
11 : both

INT1 edge select

00 : Int. disable
01 : falling
10 : rising
11 : both

Interrupt
goes
active

Interrupt
latched

Interrupt
processing

Interrupt
routine

8 f

OSC

max. 12 f

OSC

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

16. WATCHDOG TIMER

The purpose of the watchdog timer is to detect the mal-
function (runaway) of program due to external noise or
other causes and return the operation to the normal condi-
tion. The watchdog timer has two types of clock source.

The first type is an on-chip RC oscillator which does not
require any external components. This RC oscillator is sep-
arate from the external oscillator of the Xin pin. But the in-
ternal RC oscillated clock source should be activated by
execution of STOP instruction. It means that the watchdog
timer can not run even if the clock on the Xin pin of the
device has been stopped, for example, by entering the
STOP mode.

The other type is a prescaled system clock.

The watchdog timer consists of 7-bit binary counter and
the watchdog timer data register. The source clock of
WDT is overflow of Basic Interval Timer. When the value
of 7-bit binary counter is equal to the lower 7 bits of
WDTR, the interrupt request flag is generated. This can be
used as WDT interrupt or CPU reset signal in accordance
with the bit WDTON .

Note: Because the watchdog timer counter is enabled af-

ter clearing Basic Interval Timer and setting the
Watchdog Timer Register, maximum error of timer
is depend on prescaler ratio of Basic Interval Timer.

The 7-bit binary counter is cleared by setting WDTCL(bit7
of WDTR) and the WDTCL is cleared automatically after
1 machine cycle.

The RC oscillated watchdog timer is activated by setting
the bit RCWDT of CKCTLR and executing the STOP in-
struction as shown below.

The RC oscillation period is variable according to the tem-
perature, V

and process variations from part to part (ap-

proximately, 120~180uS at 5V). The following equation
shows the RC oscillated watchdog timer time-out.

R C W D T

= C L K

R C

�2

�[

W D T R .6 ~ 0 ]+ (C L K

R C

�2

)/2

w h ere, C L K

R C

= 1 2 0 ~ 1 8 0 u S

In addition, this watchdog timer can be used as a simple 7-
bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.

WDT

= [WDTR.6~0]

�
�
�
�

Interval of BIT

Figure 16-1 Block Diagram of Watchdog Timer

:
LDM

CKCTLR,#3FH

; enable the RC-osc WDT

LDM

WDTR,#0FFH

; set the WDT period

STOP

; enter the STOP mode

NOP
NOP

; RC-osc WDT running

�

128

�

256

�

512

�

1024

�

MUX

XIN

BITR (8-bit)

BTS[2:0]

Internal RC OSC

Basic Interval Timer
Interrupt

BTCL

Clear

Watchdog Timer

BITIF

7-bit Counter

WDTR (8-bit)

OFD

WDTCL

WDTON

Interrupt Request

CPU RESET

Clock Control Register

CKCTLR

ADDRESS : ECH
RESET VALUE : -0010111

WAKEUP RCWDT

WDTON

BTCL

BTS2

BTS1

BTS0

Watchdog Timer Register

WDTR

ADDRESS : EDH
RESET VALUE : 01111111

WDTCL

7-bit Watchdog Counter Register

Overflow Detection

Bit Manipulation Not Available

STOP

WAKEUP

RCWDT

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

17. POWER SAVING MODE

For applications where power consumption is a critical
factor, device provides three kinds of power saving func-
tions, STOP mode, Wake-up Timer mode and internal RC-
oscillated watchdog timer mode.

The power saving function is activated by execution of
STOP instruction after setting the corresponding bit
(WAKEUP, RCWDT) of CKCTLR.

Table 17-1 shows the status of each Power Saving Mode

Note: Before executing STOP instruction, clear all in-

terrupt request flag. Because if the interrupt re-
quest flag is set before STOP instruction, the MCU
runs as if it doesn't perform STOP instruction, even
though the STOP instruction is completed. So insert
two lines to clear all interrupt request flags (IRQH,
IRQL) before STOP instruction as shown each ex-
ample.

17.1 Stop Mode

In the Stop mode, the on-chip oscillator is stopped. With
the clock frozen, all functions are stopped, but the on-chip
RAM and Control registers are held. The port pins out the
values held by their respective port data register, port di-
rection registers. Oscillator stops and the systems internal
operations are all held up.

� The states of the RAM, registers, and latches valid

immediately before the system is put in the STOP
state are all held.

� The program counter stop the address of the

instruction to be executed after the instruction
"STOP" which starts the STOP operating mode.

The Stop mode is activated by execution of STOP in-
struction after setting the bit WAKEUP and RCWDT
of CKCTLR to "00". (This register should be written
by byte operation. If this register is set by bit manipu-
lation instruction, for example "set1" or "clr1" instruc-
tion, it may be undesired operation)

In the Stop mode of operation, V

can be reduced to min-

imize power consumption. Care must be taken, however,

to ensure that V

is not reduced before the Stop mode is

invoked, and that V

is restored to its normal operating

level, before the Stop mode is terminated.

The reset should not be activated before V

is restored to

its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.

Note: After STOP instruction, at least two or more NOP

instruction should be written

Ex)

LDM CKCTLR,#0000_1110B

LDM IRQH,#0

LDM IRQL,#0

STOP

NOP

In the STOP operation, the dissipation of the power asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
of the STOP feature. This point should be little current

Peripheral

STOP

Wake-up Timer

Internal RC-WDT

RAM

Retain

Control Registers

Retain

I/O Ports

Retain

CPU

Stop

Timer0

Stop

Operation

Stop

Oscillation

Stop

Oscillation

Stop

Prescaler

Stop

�

2048 only

Stop

Internal RC oscillator

Stop

Oscillation

Entering Condition

CKCTLR[6,5]

Power Saving Release

Source

RESET, INT0, INT1

RESET, INT0, INT1,

Timer0

RESET, INT0, INT1,

RC-WDT

Table 17-1 Power Saving Mode

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

flows when the input level is stable at the power voltage
level (V

), however, when the input level gets high-

er than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal into the
high-impedance state, a current flow across the ports input
transistor, requiring to fix the level by pull-up or other
means.

Release the STOP mode

The exit from STOP mode is hardware reset or external in-
terrupt. Reset re-defines all the Control registers but does
not change the on-chip RAM. External interrupts allow
both on-chip RAM and Control registers to retain their val-
ues.

After releasing STOP mode, instruction execution is divid-
ed into two ways by I-flag(bit2 of PSW).
If I-flag = 1, the normal interrupt response takes place. If I-
flag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vec-
tor to interrupt service routine. (refer to Figure 17-1)

When exit from Stop mode by external interrupt, enough
oscillation stabilization time is required to normal opera-
tion. Figure 17-2 shows the timing diagram. When release
the Stop mode, the Basic interval timer is activated on
wake-up. It is increased from 00

until FF

. The count

overflow is set to start normal operation. Therefore, before
STOP instruction, user must be set its relevant prescaler di-
vide ratio to have long enough time (more than 20msec).
This guarantees that oscillator has started and stabilized.

By reset, exit from Stop mode is shown in Figure 17-3.

Minimizing Current Consumption in Stop Mode

The Stop mode is designed to reduce power consumption.
To minimize the current consumption during Stop mode,

the user should turn-off output drivers that are sourcing or
sinking current, if it is practical. Weak pull-ups on port
pins should be turned off, if possible. All inputs should be
either as V

or at V

(or as close to rail as possible).

An intermediate voltage on an input pin causes the input
buffer to draw a significant amount of current.

Figure 17-1 STOP Releasing Flow by Interrupts

Figure 17-2 Timing of STOP Mode Release by External Interrupt

IEXX

STOP

INSTRUCTION

STOP Mode

Interrupt Request

STOP Mode Release

I-FLAG

Interrupt Service Routine

INSTRUCTION

Master Interrupt

Enable Bit PSW[2]

Corresponding Interrupt

Enable Bit (IENH, IENL)

STOP Mode

Normal Operation

Oscillator

pin)

N+1

N+2

N-1

N-2

Clear Basic Interval Timer

STOP Instruction Execution

Normal Operation

Stabilization Time

> 20mS

Internal

Clock

External
Interrupt

BIT

Counter

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

Figure 17-3 Timing of STOP Mode Release by RESET

17.2 Wake-up Timer Mode

In the Wake-up Timer mode, the on-chip oscillator is not
stopped. Except the Prescaler (only 2048 divided ratio) and
Timer0, all functions are stopped, but the on-chip RAM
and Control registers are held. The port pins out the values
held by their respective port data register, port direction
registers.

The Wake-up Timer mode is activated by execution of
STOP instruction after setting the bit WAKEUP of
CKCTLR to "1". (This register should be written by
byte operation. If this register is set by bit manipulation
instruction, for example "set1" or "clr1" instruction, it
may be undesired operation)

Note: After STOP instruction, at least two or more NOP in-

struction should be written

Ex)

LDM TDR0,#0FFH

LDM TM0,#0001_1011B

LDM CKCTLR,#0100_1110B

LDM IRQH,#0

LDM IRQL,#0

STOP

NOP

In addition, the clock source of timer0 should be select-
ed to 2048 divided ratio. Otherwise, the wake-up func-
tion can not work. And the timer0 can be operated as
16-bit timer with timer1 (refer to timer function). The
period of wake-up function is varied by setting the tim-
er data register 0, TDR0.

Release the Wake-up Timer mode

The exit from Wake-up Timer mode is hardware reset,
Timer0 overflow or external interrupt. Reset re-defines all
the Control registers but does not change the on-chip
RAM. External interrupts and Timer0 overflow allow both
on-chip RAM and Control registers to retain their values.

If I-flag = 1, the normal interrupt response takes place. If I-
flag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vec-
tor to interrupt service routine (refer to Figure 17-1).

When exit from Wake-up Timer mode by external inter-
rupt or timer0 overflow, the oscillation stabilization time is
not required to normal operation. Because this mode do not
stop the on-chip oscillator shown as Figure 17-4.

Figure 17-4 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt

STOP Mode

Oscillator

pin)

STOP Instruction Execution

Stabilization Time

= 64mS @4MHz

Internal

Clock

Internal

RESET

Time can not be controlled by software

Wake-up Timer Mode

Oscillator

pin)

STOP Instruction

Normal Operation

CPU

Clock

Request

Interrupt

Execution

Do not need Stabilization Time

(stop the CPU clock)

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

17.3 Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Watchdog Timer mode, the
on-chip oscillator is stopped. But internal RC oscillation
circuit is oscillated in this mode. The on-chip RAM and
Control registers are held. The port pins out the values held
by their respective port data register, port direction regis-
ters.

The Internal RC-Oscillated Watchdog Timer mode is
activated by execution of STOP instruction after set-
ting the bit WAKEUP and RCWDT of CKCTLR to
"01". (This register should be written by byte opera-
tion. If this register is set by bit manipulation instruc-
tion, for example "set1" or "clr1" instruction, it may be
undesired operation)

Note: After STOP instruction, at least two or more NOP in-

struction should be written

Ex)

LDM WDTR,#1111_1111B

LDM CKCTLR,#0010_1110B

LDM IRQH,#0

LDM IRQL,#0

STOP

NOP

Release the Internal RC-Oscillated Watchdog Timer mode

The exit from Internal RC-Oscillated Watchdog Timer
mode is hardware reset or external interrupt. Reset re-de-
fines all the Control registers but does not change the on-

chip RAM. External interrupts allow both on-chip RAM
and Control registers to retain their values.

If I-flag = 1, the normal interrupt response takes place. In
this case, if the bit WDTON of CKCTLR is set to "0" and
the bit WDTE of IENH is set to "1", the device will exe-
cute the watchdog timer interrupt service routine.(Figure
17-5) However, if the bit WDTON of CKCTLR is set to
"1", the device will generate the internal RESET signal
and execute the reset processing. (Figure 17-6)

If I-flag = 0, the chip will resume execution starting with
the instruction following the STOP instruction. It will not
vector to interrupt service routine (refer to Figure 17-1).

When exit from Internal RC-Oscillated Watchdog Timer
mode by external interrupt, the oscillation stabilization
time is required for normal operation. Figure 17-5 shows
the timing diagram. When release the Internal RC-Oscil-
lated Watchdog Timer mode, the basic interval timer is ac-
tivated on wake-up. It is increased from 00

until FF

. The

count overflow is set to start normal operation. Therefore,
before STOP instruction, user must be set its relevant pres-
caler divide ratio to have long enough time (more than
20msec). This guarantees that oscillator has started and
stabilized.

By reset, exit from internal RC-Oscillated Watchdog Tim-
er mode is shown in Figure 17-6.

Figure 17-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt

RCWDT Mode

Normal Operation

Oscillator

pin)

N+1

N+2

N-1

N-2

Clear Basic Interval Timer

STOP Instruction Execution

Normal Operation

Stabilization Time

> 20mS

Internal

Clock

External
Interrupt

BIT

Counter

Internal

RC Clock

(or WDT Interrupt)

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

Figure 17-6 Internal RCWDT Mode Releasing by RESET

17.4 Minimizing Current Consumption

The Stop mode is designed to reduce power consumption.
To minimize current drawn during Stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.

Note: In the STOP operation, the power dissipation asso-

ciated with the oscillator and the internal hardware
is lowered; however, the power dissipation associat-
ed with the pin interface (depending on the external
circuitry and program) is not directly determined by
the hardware operation of the STOP feature. This
point should be little current flows when the input
level is stable at the power voltage level (V

);

however, when the input level becomes higher than
the power voltage level (by approximately 0.3V), a
current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal
into the high-impedance state, a current flow across
the ports input transistor, requiring it to fix the level
by pull-up or other means.

It should be set properly that current flow through port
doesn't exist.

First conseider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn't
flow.

But input voltage level should be V

or V

. Be careful

that if unspecified voltage, i.e. if uncertain voltage level
(not V

or V

) is applied to input pin, there can be little

current (max. 1mA at around 2V) flow.

If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up re-
sistor then it is set to output mode, i.e. to High, and if there
is external pull-down register, it is set to low.

Oscillator

pin)

Internal

Clock

Internal

RC Clock

STOP Instruction Execution

Stabilization Time

= 64mS @4MHz

Internal

RESET by WDT

RESET

RCWDT Mode

Time can not be controlled by software

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

18. RESET

The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, while the
oscillator running. After reset, 64ms (at 4 MHz) add with
7 oscillator periods are required to start execution as shown
in Figure 18-1.

Internal RAM is not affected by reset. When V

is turned

on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before reading or testing it.

Initial state of each register is shown as Table 8-1.

Figure 18-1 Timing Diagram after RESET

� Power-On Reset (POR)

The HMS87C130XA incorporates on-chip Power-On Re-
set (POR) circuitry which provides an internal chip reset
for most power-up situations. To use this feature, the user
merely ties the RESET pin to V

and setting the POREN

bit of CONFIG register ( refer to Figure 20-1).

A Power-on Reset pulse is generated on-chip when V

rise is detected approximately 1V. To take an advantage of
the Power-on Reset, just tie the RESET pin directly ( or
through the resistor ) to V

Figure 18-2 Time-out Sequence On Power-up (RESET Tied To V

): Fast V

Rise Time

A power-up example where RESET is not tied to V

shown in Figure 18-2. V

is allowed to rise and stabilize

before bringing RESET high. The chip will actually come
out of reset and start the Basic Interval Timer after RESET
goes high.

In Figure 18-3, the on-chip Power-On Reset feature is be-
ing used (RESET and V

are tied together). The V

stable before the Basic interval timer times out and there is
no problem in getting a proper reset. However, Figure 18-
4 depicts a problem situation where V

rises too slowly.

MAIN PROGRAM

Oscillator

pin)

FFFE FFFF

Stabilizing Time

= 64mS at 4MHz

RESET

ADDRESS

DATA

Start

ADL

ADH

BUS

RESET Process Step

RESET

INTERNAL RESET

Basic Interval Timer Start

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

The time between when the Basic interval timer senses a
high on the RESET pin, and when the RESET pin (and
V

) actually reach their full value, is too long. In this sit-

uation, when the Basic interval timer times out, V

has

not reached the V

(min) value and the chip is, therefore,

not guaranteed to function correctly. For such situations,
we recommend that external R circuits be used to achieve
longer POR delay times ( Figure 18-5). The POR circuit

does not produce an internal reset when V

declines

Note: When the device starts normal operation (exits the

reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be meet to
ensure operation. If these conditions are not met,
the device must be held in reset until the operating
conditions are met..

Figure 18-3 Time-out Sequence On Power-up (RESET Tied To V

): Fast V

Rise Time

Figure 18-4 TIME-OUT SEQUENCE ON POWER-UP (RESET TIED TO V

): SLOW V

RISE TIME

Figure 18-5 EXTERNAL POWERON RESET CIRCUIT (FOR SLOW V

POWER-UP)

RESET

INTERNAL POR

INTERNAL RESET

Basic Interval Timer Start

RESET

INTERNAL POR

INTERNAL RESET

Basic Interval Timer Start

RESET

- External Power-On Reset circuit is required only if VDD

power-up is too slow. The diode D helps discharge the

capacitor quickly when VDD powers down.

- R < 40 k

is recommended to make sure that voltage

drop across R does not violate the device electrical specifi-
cation

- R1 = 100

to 1k

will limit any current flowing into

RESET from external capacitor C in the event of RESET

pin breakdown due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

19. POWER FAIL PROCESSOR

The HMS87C1X0XA has an on-chip power fail detection
circuitry to immunize against power noise. A Power Fail
Detector Register, PFDR can enable (if clear/pro-
grammed) or disable (if set) the Power fail Detect circuitry.
If V

falls below 2.4~2.6V(or 1.6~1.8V) range for longer

than 50 nS, the Power fail situation may reset MCU or halt
the system clock according to PFS bit of PFDR. And pow-
er fail detect level is selectable by programming the bit
PFDLEVEL of CONFIG register when program the OTP.

As below PFDR register is not implemented on the in-cir-
cuit emulator, user can not experiment with it. Therefore,
after final development of user program, this function may
be experimented.

Note: Power fail detect level is decided by setting the bit

PFDLEVEL of CONFIG register (refer to Figure 20-
1.

Figure 19-1 Power Fail Detector

PFDR

ADDRESS : EFH
RESET VALUE : ----0100

PFDOPR

PFDIS

PFDM

PFS

Reserved

Power Fail Status
0 : Normal Operate
1 : This bit force to "1" when

Operation Mode
0 : System Clock Freeze during power fail

1 : MCU will be reset during power fail

Disable Flag
0 : Power fail detection enable

1 : Power fail detection disable

Power Fail Detector Register

Power fail was detected

PFD Operation Disable Flag
0 : Power fail detection enable

1 : Power fail detection disable

Power

Fail

Detection

Circuit

Power Noise

PFDIS

PFDOPR

PFDM

to RESET circuit

System clock freeze

PFS

But can read PFS

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

20. OTP PROGRAMMING

The HMS87C130XA is one-time PROM(OTP) microcon-
troller with 4K/2K bytes electrically programmable read
only memory.

To programming the OTP device, user must use the uni-
versal programmer which is support Hynix microcontrol-
lers.

20.1 DEVICE CONFIGURATION AREA

The Device Configuration Area can be programmed or left
unprogrammed to select device configuration such as secu-
rity bit, power on reset, RC-oscillation, PFD level select
and open drain port selection .

This area is not accessible during normal execution but is
readable and writable during program / verify.

Figure 20-1 Device Configuration Area

0 : Allow Code Read Out

1 : Prohibit Code Read Out

SECURITY BIT

0 : PFD Level High (2.4~2.6V)
1 : PFD Level Low (1.6~1.8V)

PFD Level Select

CONFIG

ADDRESS : 707FH

POREN

OPDR1

OPDR0

LOCK

PFD

RC_OPT

Configuration Register

LEVEL

0 : Normal Oscillator
1 : External RC Oscillator

RC Otion

00 : Normal Port
01 : Open Drain RA0

Open Drain Port Selection

10 : Open Drain RA0/RB2
11 : Open Drain RA0/RB2/RB3/RC0

0 : Power on RESET Disable

1 : Power on RESET Enable

Power on RESET

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

Figure 20-2 Pin Assignment ( HMS1304/2A )

A_D0

A_D1

A_D2

A_D3

EPROM Enable

A_D7

A_D6

A_D5

A_D4

CTL2

CTL1

CTL0

Pin No.

User Mode

EPROM MODE

Pin Name

Description

RA4 (AN4)

A_D4

Address Input

Data Input/Output

A12

RA5 (AN5)

A_D5

A13

RA6 (AN6)

A_D6

A14

RA7 (AN7)

A_D7

A15

Connect to V

(6.0V)

RD0

CTL0

Read/Write Control
Address/Data Control

RD1

CTL1

RBB0/AN0/AVref

CTL2

9~14

RB1~4, RD2~3

Connect to V

(6.0V)

EPROM Enable

High Active, Latch Address in falling edge

OUT

No connection

RESET

Programming Power (0V, 12.75V)

Connect to V

(0V)

19,20

RC0, 1

Connect to V

(6.0V)

RA0 (EC0)

A_D0

Address Input

Data Input/Output

RA1 (AN1)

A_D1

RA2 (AN2)

A_D2

A10

RA3 (AN3)

A_D3

A11

Table 20-1 Pin Description in EPROM Mode ( HMS1304/2A )

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

Figure 20-3 Pin Assignment ( HMS1204/2A )

Pin No.

User Mode

EPROM MODE

Pin Name

Description

RA4 (AN4)

A_D4

Address Input

Data Input/Output

A12

RA5 (AN5)

A_D5

A13

RA6 (AN6)

A_D6

A14

RA7 (AN7)

A_D7

A15

Connect to V

(6.0V)

RB0/AN0/AVref

CTL0

Read/Write Control
Address/Data Control

RB1/BUZ

CTL1

RB2/INT0

CTL2

9,10

RB3~4

Connect to V

(6.0V)

EPROM Enable

High Active, Latch Address in falling edge

OUT

No connection

RESET

Programming Power (0V, 12.75V)

Connect to V

(0V)

15,16

RC0, 1

Connect to V

(6.0V)

RA0 (EC0)

A_D0

Address Input

Data Input/Output

RA1 (AN1)

A_D1

RA2 (AN2)

A_D2

A10

RA3 (AN3)

A_D3

A11

Table 20-2 Pin Description in EPROM Mode ( HMS1204/2A )

A_D0

A_D1

A_D2

A_D3

EPROM Enable

A_D7

A_D6

A_D5

A_D4

CTL2

CTL1

CTL0

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

Figure 20-4 Pin Assignment ( HMS1104/2A )

Pin No.

User Mode

EPROM MODE

Pin Name

Description

RA4 (AN4)

A_D4

Address Input

Data Input/Output

A12

RA5 (AN5)

A_D5

A13

RA6 (AN6)

A_D6

A14

RA7 (AN7)

A_D7

A15

Connect to V

(6.0V)

RB0/AN0/AVref

CTL0

Read/Write Control
Address/Data Control

RB2/INT0

CTL1

RB4/PWM/COMP

CTL2

EPROM Enable

High Active, Latch Address in falling edge

OUT

No connection

RESET

Programming Power (0V, 12.75V)

Connect to V

(0V)

RA0 (EC0)

A_D0

Address Input

Data Input/Output

RA1 (AN1)

A_D1

RA2 (AN2)

A_D2

A10

RA3 (AN3)

A_D3

A11

Table 20-3 Pin Description in EPROM Mode ( HMS1104/2A )

A_D0

A_D1

A_D2

A_D3

EPROM Enable

A_D7

A_D6

A_D5

A_D4

CTL2

CTL1

CTL0

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

Figure 20-5 Timing Diagram in Program (Write & Verify) Mode

Figure 20-6 Timing Diagram in READ Mode

CTL0

High 8bit

DATA IN

DATA

OUT

DATA IN

DATA

OUT

EPROM
Enable

CTL1

CTL2

A_D7~

DD1H

Address
Input

Low 8bit
Address
Input

Write Mode

Verify

Low 8bit
Address
Input

Write Mode

Verify

A_D0

VDDS

VPPR

VPPS

DD1H

IHP

~~
~~

HLD1

HLD2

SET1

DLY1

DLY2

CD1

CTL0

High 8bit

DATA

EPROM
Enable

CTL1

CTL2

A_D7~

DD2H

Address
Input

Low 8bit
Address
Input

DATA

A_D0

VDDS

VPPR

VPPS

DD2H

IHP

HLD1

SET1

DLY1

CD1

CD2

CD1

Output

Low 8bit
Address
Input

High 8bit
Address
Input

Low 8bit
Address
Input

DATA
Output

After input a high address,

output data following low address input

Another high address step

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

Parameter

Symbol

MIN

TYP

MAX

Unit

Programming Supply Current

VPP

Supply Current in EPROM Mode

VDDP

Level during Programming

IHP

12.5

12.75

Level in Program Mode

DD1H

5.5

6.6

Level in Read Mode

DD2H

2.7

CTL2~0 High Level in EPROM Mode

IHC

0.8V

CTL2~0 Low Level in EPROM Mode

ILC

0.2V

A_D7~A_D0 High Level in EPROM Mode

IHAD

0.9V

A_D7~A_D0 Low Level in EPROM Mode

ILAD

0.1V

Saturation Time

VDDS

Setup Time

VPPR

Saturation Time

VPPS

EPROM Enable Setup Time after Data Input

SET1

200

EPROM Enable Hold Time after T

SET1

HLD1

500

EPROM Enable Delay Time after T

HLD1

DLY1

200

EPROM Enable Hold Time in Write Mode

HLD2

100

EPROM Enable Delay Time after T

HLD2

DLY2

200

CTL2,1 Setup Time after Low Address input and Data input

CD1

100

CTL1 Setup Time before Data output in Read and Verify Mode

CD2

100

Table 20-4 AC/DC Requirements for Program/Read Mode

HMS871C130XA/120XA/110XA

Apr. 2001 Ver 1.0

APPENDIX

A. INSTRUCTION MAP

LOW

HIGH

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

000

SET1
dp.bit

BBS

A.bit,rel

BBS

dp.bit,rel

ADC

#imm

ADC

dp+X

ADC

!abs

ASL

TCALL

SETA1

.bit

BIT

POP

PUSH

BRK

001

CLRC

SBC

#imm

SBC

dp+X

SBC

!abs

ROL

TCALL

CLRA1

.bit

COM

POP

PUSH

BRA

rel

010

CLRG

CMP

#imm

CMP

dp+X

CMP

!abs

LSR

TCALL

NOT1

M.bit

TST

POP

PUSH

PCALL

Upage

011

#imm

dp+X

!abs

ROR

TCALL

OR1

OR1B

CMPX

POP

PSW

PUSH

PSW

RET

100

CLRV

AND

#imm

AND

dp+X

AND

!abs

INC

TCALL

AND1

AND1B

CMPY

CBNE

dp+X

TXSP

INC

101

SETC

EOR

#imm

EOR

dp+X

EOR

!abs

DEC

TCALL

EOR1

EOR1B

DBNE

XMA

dp+X

TSPX

DEC

110

SETG

LDA

#imm

LDA

dp+X

LDA
!abs

TXA

LDY

TCALL

LDC

LDCB

LDX

dp+Y

XCN

DAS

111

LDM

dp,#imm

STA

dp+X

STA
!abs

TAX

STY

TCALL

STC

M.bit

STX

dp+Y

XAX

STOP

LOW

HIGH

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

000

BPL

rel

CLR1

dp.bit

BBC

A.bit,rel

BBC

dp.bit,rel

ADC

{X}

ADC

!abs+Y

ADC

[dp+X]

ADC

[dp]+Y

ASL
!abs

ASL

dp+X

TCALL

JMP

!abs

BIT

!abs

ADDW

LDX

#imm

JMP

[!abs]

001

BVC

rel

SBC

{X}

SBC

!abs+Y

SBC

[dp+X]

SBC

[dp]+Y

ROL

!abs

ROL

dp+X

TCALL

CALL

!abs

TEST

!abs

SUBW

LDY

#imm

JMP

[dp]

010

BCC

rel

CMP

{X}

CMP

!abs+Y

CMP

[dp+X]

CMP

[dp]+Y

LSR
!abs

LSR

dp+X

TCALL

MUL

TCLR1

!abs

CMPW

CMPX

#imm

CALL

[dp]

011

BNE

rel

{X}

!abs+Y

[dp+X]

[dp]+Y

ROR

!abs

ROR

dp+X

TCALL

DBNE

CMPX

!abs

LDYA

CMPY

#imm

RETI

100

BMI

rel

AND

{X}

AND

!abs+Y

AND

[dp+X]

AND

[dp]+Y

INC

!abs

INC

dp+X

TCALL

DIV

CMPY

!abs

INCW

INC

TAY

101

BVS

rel

EOR

{X}

EOR

!abs+Y

EOR

[dp+X]

EOR

[dp]+Y

DEC

!abs

DEC

dp+X

TCALL

XMA

{X}

XMA

DECW

DEC

TYA

110

BCS

rel

LDA

{X}

LDA

!abs+Y

LDA

[dp+X]

LDA

[dp]+Y

LDY
!abs

LDY

dp+X

TCALL

LDA
{X}+

LDX
!abs

STYA

XAY

DAA

111

BEQ

rel

STA

{X}

STA

!abs+Y

STA

[dp+X]

STA

[dp]+Y

STY
!abs

STY

dp+X

TCALL

STA
{X}+

STX
!abs

CBNE

XYX

NOP

HMS87C130XA/120XA/110XA

Apr. 2001 Ver 1.0

B. INSTRUCTION SET

1. ARITHMETIC/ LOGIC OPERATION

NO.

MNEMONIC

CODE

BYTE

CYCLE

OPERATION

FLAG

NVGBHIZC

ADC #imm

Add with carry.

ADC dp

( A ) + ( M ) + C

ADC dp + X

ADC !abs

NV--H-ZC

ADC !abs + Y

ADC [ dp + X ]

ADC [ dp ] + Y

ADC { X }

AND #imm

Logical AND

AND dp

( A )

( M )

AND dp + X

AND !abs

N-----Z-

AND !abs + Y

AND [ dp + X ]

AND [ dp ] + Y

AND { X }

ASL A

Arithmetic shift left

ASL dp

N-----ZC

ASL dp + X

ASL !abs

CMP #imm

Compare accumulator contents with memory contents

CMP dp

( A ) - ( M )

CMP dp + X

CMP !abs

N-----ZC

CMP !abs + Y

CMP [ dp + X ]

CMP [ dp ] + Y

CMP { X }

CMPX #imm

Compare X contents with memory contents

CMPX dp

( X ) - ( M )

N-----ZC

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

CMPY dp

( Y ) - ( M )

N-----ZC

CMPY !abs

COM dp

1'S Complement : ( dp )

~( dp )

N-----Z-

DAA

Decimal adjust for addition

N-----ZC

DAS

Decimal adjust for subtraction

N-----ZC

DEC A

Decrement

N-----Z-

DEC dp

( M ) - 1

DEC dp + X

N-----Z-

DEC !abs

DEC X

DEC Y

DIV

Divide : YA / X Q: A, R: Y

NV--H-Z-

"0"

HMS871C130XA/120XA/110XA

Apr. 2001 Ver 1.0

iii

NO.

MNEMONIC

CODE

BYTE

CYCLE

OPERATION

FLAG

NVGBHIZC

EOR #imm

Exclusive OR

EOR dp

( A )

( M )

EOR dp + X

EOR !abs

N-----Z-

EOR !abs + Y

EOR [ dp + X ]

EOR [ dp ] + Y

EOR { X }

INC A

Increment

N-----Z-

INC dp

( M ) + 1

INC dp + X

N-----Z-

INC !abs

INC X

INC Y

LSR A

Logical shift right

LSR dp

N-----ZC

LSR dp + X

LSR !abs

MUL

Multiply : YA

�

N-----Z-

OR #imm

Logical OR

OR dp

( A )

( M )

OR dp + X

OR !abs

N-----Z-

OR !abs + Y

OR [ dp + X ]

OR [ dp ] + Y

OR { X }

ROL A

Rotate left through carry

ROL dp

N-----ZC

ROL dp + X

ROL !abs

ROR A

Rotate right through carry

ROR dp

N-----ZC

ROR dp + X

ROR !abs

SBC #imm

Subtract with carry

SBC dp

( A ) - ( M ) - ~( C )

SBC dp + X

SBC !abs

NV--HZC

SBC !abs + Y

SBC [ dp + X ]

SBC [ dp ] + Y

SBC { X }

TST dp

Test memory contents for negative or zero
( dp ) - 00

N-----Z-

XCN

Exchange nibbles within the accumulator
A

N-----Z-

"0"

HMS87C130XA/120XA/110XA

Apr. 2001 Ver 1.0

2. REGISTER / MEMORY OPERATION

NO.

MNEMONIC

CODE

BYTE

CYCLE

OPERATION

FLAG

NVGBHIZC

LDA #imm

Load accumulator

LDA dp

( M )

LDA dp + X

LDA !abs

LDA !abs + Y

N-----Z-

LDA [ dp + X ]

LDA [ dp ] + Y

LDA { X }

LDA { X }+

X- register auto-increment : A

( M ) , X

X + 1

LDM dp,#imm

Load memory with immediate data : ( M )

imm

--------

LDX #imm

Load X-register

LDX dp

( M )

N-----Z-

LDX dp + Y

LDX !abs

LDY #imm

Load Y-register

LDY dp

( M )

N-----Z-

LDY dp + X

LDY !abs

STA dp

Store accumulator contents in memory

STA dp + X

( M )

STA !abs

STA !abs + Y

--------

STA [ dp + X ]

STA [ dp ] + Y

STA { X }

STA { X }+

X- register auto-increment : ( M )

A, X

X + 1

STX dp

Store X-register contents in memory

STX dp + Y

( M )

--------

STX !abs

STY dp

Store Y-register contents in memory

STY dp + X

( M )

--------

STY !abs

TAX

Transfer accumulator contents to X-register : X

N-----Z-

TAY

Transfer accumulator contents to Y-register : Y

N-----Z-

TSPX

Transfer stack-pointer contents to X-register : X

N-----Z-

TXA

Transfer X-register contents to accumulator: A

N-----Z-

TXSP

Transfer X-register contents to stack-pointer: sp

N-----Z-

TYA

Transfer Y-register contents to accumulator: A

N-----Z-

XAX

Exchange X-register contents with accumulator :X

--------

XAY

Exchange Y-register contents with accumulator :Y

--------

XMA dp

Exchange memory contents with accumulator

XMA dp+X

( M )

N-----Z-

XMA {X}

XYX

Exchange X-register contents with Y-register : X

--------

HMS871C130XA/120XA/110XA

Apr. 2001 Ver 1.0

3. 16-BIT OPERATION

4. BIT MANIPULATION

NO.

MNEMONIC

CODE

BYTE

CYCLE

OPERATION

FLAG

NVGBHIZC

ADDW dp

16-Bits add without carry
YA

( YA ) + ( dp +1 ) ( dp )

NV--H-ZC

CMPW dp

Compare YA contents with memory pair contents :
(YA)

(dp+1)(dp)

N-----ZC

DECW dp

Decrement memory pair
( dp+1)( dp)

( dp+1) ( dp) - 1

N-----Z-

INCW dp

Increment memory pair
( dp+1) ( dp)

( dp+1) ( dp ) + 1

N-----Z-

LDYA dp

Load YA
YA

( dp +1 ) ( dp )

N-----Z-

STYA dp

Store YA
( dp +1 ) ( dp )

--------

SUBW dp

16-Bits substact without carry
YA

( YA ) - ( dp +1) ( dp)

NV--H-ZC

NO.

MNEMONIC

CODE

BYTE

CYCLE

OPERATION

FLAG

NVGBHIZC

AND1 M.bit

Bit AND C-flag : C

( C )

( M .bit )

-------C

AND1B M.bit

Bit AND C-flag and NOT : C

( C )

~( M .bit )

-------C

BIT dp

Bit test A with memory :

MM----Z-

BIT !abs

( A )

( M ) , N

( M

) , V

( M

)

CLR1 dp.bit

Clear bit : ( M.bit )

"0"

--------

CLRA1 A.bit

Clear A bit : ( A.bit )

"0"

--------

CLRC

Clear C-flag : C

"0"

-------0

CLRG

Clear G-flag : G

"0"

--0-----

CLRV

Clear V-flag : V

"0"

-0--0---

EOR1 M.bit

Bit exclusive-OR C-flag : C

( C )

( M .bit )

-------C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

( C )

~(M .bit)

-------C

LDC M.bit

Load C-flag : C

( M .bit )

-------C

LDCB M.bit

Load C-flag with NOT : C

~( M .bit )

-------C

NOT1 M.bit

Bit complement : ( M .bit )

~( M .bit )

--------

OR1 M.bit

Bit OR C-flag : C

( C )

( M .bit )

-------C

OR1B M.bit

Bit OR C-flag and NOT : C

( C )

~( M .bit )

-------C

SET1 dp.bit

Set bit : ( M.bit )

"1"

--------

SETA1 A.bit

Set A bit : ( A.bit )

"1"

--------

SETC

Set C-flag : C

"1"

-------1

SETG

Set G-flag : G

"1"

--1-----

STC M.bit

Store C-flag : ( M .bit )

--------

TCLR1 !abs

Test and clear bits with A :
A - ( M ) , ( M )

( M )

~( A )

N-----Z-

TSET1 !abs

Test and set bits with A :
A - ( M ) , ( M )

( M )

( A )

N-----Z-

HMS87C130XA/120XA/110XA

Apr. 2001 Ver 1.0

5. BRANCH / JUMP OPERATION

NO.

MNEMONIC

CODE

BYTE

CYCLE

OPERATION

FLAG

NVGBHIZC

BBC A.bit,rel

4/6

Branch if bit clear :

--------

BBC dp.bit,rel

5/7

if ( bit ) = 0 , then pc

( pc ) + rel

BBS A.bit,rel

4/6

Branch if bit set :

--------

BBS dp.bit,rel

5/7

if ( bit ) = 1 , then pc

( pc ) + rel

BCC rel

2/4

Branch if carry bit clear
if ( C ) = 0 , then pc

( pc ) + rel

--------

BCS rel

2/4

Branch if carry bit set
if ( C ) = 1 , then pc

( pc ) + rel

--------

BEQ rel

2/4

Branch if equal
if ( Z ) = 1 , then pc

( pc ) + rel

--------

BMI rel

2/4

Branch if minus
if ( N ) = 1 , then pc

( pc ) + rel

--------

BNE rel

2/4

Branch if not equal
if ( Z ) = 0 , then pc

( pc ) + rel

--------

BPL rel

2/4

Branch if minus
if ( N ) = 0 , then pc

( pc ) + rel

--------

BRA rel

Branch always
pc

( pc ) + rel

--------

BVC rel

2/4

Branch if overflow bit clear
if (V) = 0 , then pc

( pc) + rel

--------

BVS rel

2/4

Branch if overflow bit set
if (V) = 1 , then pc

( pc ) + rel

--------

CALL !abs

Subroutine call

CALL [dp]

M( sp)

( pc

), sp

sp - 1, M(sp)

(pc

), sp

sp - 1,

if !abs, pc

abs ; if [dp], pc

( dp ), pc

( dp+1 ) .

--------

CBNE dp,rel

5/7

Compare and branch if not equal :

--------

CBNE dp+X,rel

6/8

if ( A )

( M ) , then pc

( pc ) + rel.

DBNE dp,rel

5/7

Decrement and branch if not equal :

--------

DBNE Y,rel

4/6

if ( M )

0 , then pc

( pc ) + rel.

JMP !abs

Unconditional jump

JMP [!abs]

jump address

--------

JMP [dp]

PCALL upage

U-page call
M(sp)

( pc

), sp

sp - 1, M(sp)

( pc

sp - 1, pc

( upage ), pc

"0FF

" .

--------

TCALL n

Table call : (sp)

( pc

), sp

sp - 1,

M(sp)

( pc

),sp

sp - 1,

(Table vector L), pc

(Table vector H)

--------

HMS871C130XA/120XA/110XA

Apr. 2001 Ver 1.0

vii

6. CONTROL OPERATION & etc.

NO.

MNEMONIC

CODE

BYTE

CYCLE

OPERATION

FLAG

NVGBHIZC

BRK

Software interrupt : B

"1", M(sp)

(pc

), sp

sp-1,

M(s)

(pc

), sp

sp - 1, M(sp)

(PSW), sp

sp -1,

( 0FFDE

) , pc

( 0FFDF

) .

---1-0--

Disable interrupts : I

"0"

-----0--

Enable interrupts : I

"1"

-----1--

NOP

No operation

--------

POP A

sp + 1, A

M( sp )

POP X

sp + 1, X

M( sp )

--------

POP Y

sp + 1, Y

M( sp )

POP PSW

sp + 1, PSW

M( sp )

restored

PUSH A

M( sp )

A , sp

sp - 1

PUSH X

M( sp )

X , sp

sp - 1

--------

PUSH Y

M( sp )

Y , sp

sp - 1

PUSH PSW

M( sp )

PSW , sp

sp - 1

RET

Return from subroutine
sp

sp +1, pc

M( sp ), sp

sp +1, pc

M( sp )

--------

RETI

Return from interrupt
sp

sp +1, PSW

M( sp ), sp

sp + 1,

M( sp ), sp

sp + 1, pc

M( sp )

restored

STOP

Stop mode ( halt CPU, stop oscillator )

--------

Электронный компонент: HMS87C1102

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